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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 6 define signext i8 @float_to_int8(float %val) {7 entry:8 %conv = fptosi float %val to i89 ret i8 %conv10 }11 12 define signext i16 @float_to_int16(float %val) {13 entry:14 %conv = fptosi float %val to i1615 ret i16 %conv16 }17 18 define i32 @float_to_int32(float %val) {19 entry:20 %conv = fptosi float %val to i3221 ret i32 %conv22 }23 24 define i64 @float_to_int64(float %val) {25 entry:26 %conv = fptosi float %val to i6427 ret i64 %conv28 }29 30 define signext i8 @double_to_int8(double %val) {31 entry:32 %conv = fptosi double %val to i833 ret i8 %conv34 }35 36 define signext i16 @double_to_int16(double %val) {37 entry:38 %conv = fptosi double %val to i1639 ret i16 %conv40 }41 42 define i32 @double_to_int32(double %val) {43 entry:44 %conv = fptosi double %val to i3245 ret i32 %conv46 }47 48 define i64 @double_to_int64(double %val) {49 entry:50 %conv = fptosi double %val to i6451 ret i64 %conv52 }53 54...55---56name: float_to_int857alignment: 1658legalized: true59regBankSelected: true60tracksRegLiveness: true61registers:62 - { id: 0, class: vecr }63 - { id: 1, class: vecr }64 - { id: 2, class: gpr }65 - { id: 3, class: gpr }66body: |67 bb.1.entry:68 liveins: $xmm069 70 ; CHECK-LABEL: name: float_to_int871 ; CHECK: liveins: $xmm072 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm073 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]74 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr75 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit76 ; CHECK: $al = COPY [[COPY2]]77 ; CHECK: RET 0, implicit $al78 %1:vecr(s128) = COPY $xmm079 %0:vecr(s32) = G_TRUNC %1(s128)80 %3:gpr(s32) = G_FPTOSI %0(s32)81 %2:gpr(s8) = G_TRUNC %3(s32)82 $al = COPY %2(s8)83 RET 0, implicit $al84 85...86---87name: float_to_int1688alignment: 1689legalized: true90regBankSelected: true91tracksRegLiveness: true92registers:93 - { id: 0, class: vecr }94 - { id: 1, class: vecr }95 - { id: 2, class: gpr }96 - { id: 3, class: gpr }97body: |98 bb.1.entry:99 liveins: $xmm0100 101 ; CHECK-LABEL: name: float_to_int16102 ; CHECK: liveins: $xmm0103 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0104 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]105 ; CHECK: %3:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr106 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit107 ; CHECK: $ax = COPY [[COPY2]]108 ; CHECK: RET 0, implicit $ax109 %1:vecr(s128) = COPY $xmm0110 %0:vecr(s32) = G_TRUNC %1(s128)111 %3:gpr(s32) = G_FPTOSI %0(s32)112 %2:gpr(s16) = G_TRUNC %3(s32)113 $ax = COPY %2(s16)114 RET 0, implicit $ax115 116...117---118name: float_to_int32119alignment: 16120legalized: true121regBankSelected: true122tracksRegLiveness: true123registers:124 - { id: 0, class: vecr }125 - { id: 1, class: vecr }126 - { id: 2, class: gpr }127body: |128 bb.1.entry:129 liveins: $xmm0130 131 ; CHECK-LABEL: name: float_to_int32132 ; CHECK: liveins: $xmm0133 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0134 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]135 ; CHECK: %2:gr32 = nofpexcept CVTTSS2SIrr [[COPY1]], implicit $mxcsr136 ; CHECK: $eax = COPY %2137 ; CHECK: RET 0, implicit $eax138 %1:vecr(s128) = COPY $xmm0139 %0:vecr(s32) = G_TRUNC %1(s128)140 %2:gpr(s32) = G_FPTOSI %0(s32)141 $eax = COPY %2(s32)142 RET 0, implicit $eax143 144...145---146name: float_to_int64147alignment: 16148legalized: true149regBankSelected: true150tracksRegLiveness: true151registers:152 - { id: 0, class: vecr }153 - { id: 1, class: vecr }154 - { id: 2, class: gpr }155body: |156 bb.1.entry:157 liveins: $xmm0158 159 ; CHECK-LABEL: name: float_to_int64160 ; CHECK: liveins: $xmm0161 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0162 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]163 ; CHECK: %2:gr64 = nofpexcept CVTTSS2SI64rr [[COPY1]], implicit $mxcsr164 ; CHECK: $rax = COPY %2165 ; CHECK: RET 0, implicit $rax166 %1:vecr(s128) = COPY $xmm0167 %0:vecr(s32) = G_TRUNC %1(s128)168 %2:gpr(s64) = G_FPTOSI %0(s32)169 $rax = COPY %2(s64)170 RET 0, implicit $rax171 172...173---174name: double_to_int8175alignment: 16176legalized: true177regBankSelected: true178tracksRegLiveness: true179registers:180 - { id: 0, class: vecr }181 - { id: 1, class: vecr }182 - { id: 2, class: gpr }183 - { id: 3, class: gpr }184body: |185 bb.1.entry:186 liveins: $xmm0187 188 ; CHECK-LABEL: name: double_to_int8189 ; CHECK: liveins: $xmm0190 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0191 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]192 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr193 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY %3.sub_8bit194 ; CHECK: $al = COPY [[COPY2]]195 ; CHECK: RET 0, implicit $al196 %1:vecr(s128) = COPY $xmm0197 %0:vecr(s64) = G_TRUNC %1(s128)198 %3:gpr(s32) = G_FPTOSI %0(s64)199 %2:gpr(s8) = G_TRUNC %3(s32)200 $al = COPY %2(s8)201 RET 0, implicit $al202 203...204---205name: double_to_int16206alignment: 16207legalized: true208regBankSelected: true209tracksRegLiveness: true210registers:211 - { id: 0, class: vecr }212 - { id: 1, class: vecr }213 - { id: 2, class: gpr }214 - { id: 3, class: gpr }215body: |216 bb.1.entry:217 liveins: $xmm0218 219 ; CHECK-LABEL: name: double_to_int16220 ; CHECK: liveins: $xmm0221 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0222 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]223 ; CHECK: %3:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr224 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY %3.sub_16bit225 ; CHECK: $ax = COPY [[COPY2]]226 ; CHECK: RET 0, implicit $ax227 %1:vecr(s128) = COPY $xmm0228 %0:vecr(s64) = G_TRUNC %1(s128)229 %3:gpr(s32) = G_FPTOSI %0(s64)230 %2:gpr(s16) = G_TRUNC %3(s32)231 $ax = COPY %2(s16)232 RET 0, implicit $ax233 234...235---236name: double_to_int32237alignment: 16238legalized: true239regBankSelected: true240tracksRegLiveness: true241registers:242 - { id: 0, class: vecr }243 - { id: 1, class: vecr }244 - { id: 2, class: gpr }245body: |246 bb.1.entry:247 liveins: $xmm0248 249 ; CHECK-LABEL: name: double_to_int32250 ; CHECK: liveins: $xmm0251 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0252 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]253 ; CHECK: %2:gr32 = nofpexcept CVTTSD2SIrr [[COPY1]], implicit $mxcsr254 ; CHECK: $eax = COPY %2255 ; CHECK: RET 0, implicit $eax256 %1:vecr(s128) = COPY $xmm0257 %0:vecr(s64) = G_TRUNC %1(s128)258 %2:gpr(s32) = G_FPTOSI %0(s64)259 $eax = COPY %2(s32)260 RET 0, implicit $eax261 262...263---264name: double_to_int64265alignment: 16266legalized: true267regBankSelected: true268tracksRegLiveness: true269registers:270 - { id: 0, class: vecr }271 - { id: 1, class: vecr }272 - { id: 2, class: gpr }273body: |274 bb.1.entry:275 liveins: $xmm0276 277 ; CHECK-LABEL: name: double_to_int64278 ; CHECK: liveins: $xmm0279 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0280 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]281 ; CHECK: %2:gr64 = nofpexcept CVTTSD2SI64rr [[COPY1]], implicit $mxcsr282 ; CHECK: $rax = COPY %2283 ; CHECK: RET 0, implicit $rax284 %1:vecr(s128) = COPY $xmm0285 %0:vecr(s64) = G_TRUNC %1(s128)286 %2:gpr(s64) = G_FPTOSI %0(s64)287 $rax = COPY %2(s64)288 RET 0, implicit $rax289 290...291