159 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 ; ModuleID = 'sitofp_legal.ll'6 source_filename = "sitofp.c"7 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"8 target triple = "x86_64-unknown-linux-gnu"9 10 ; Function Attrs: norecurse nounwind readnone uwtable11 define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 {12 entry:13 %conv = sitofp i32 %a to float14 ret float %conv15 }16 17 ; Function Attrs: norecurse nounwind readnone uwtable18 define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 {19 entry:20 %conv = sitofp i64 %a to float21 ret float %conv22 }23 24 ; Function Attrs: norecurse nounwind readnone uwtable25 define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 {26 entry:27 %conv = sitofp i32 %a to double28 ret double %conv29 }30 31 ; Function Attrs: norecurse nounwind readnone uwtable32 define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 {33 entry:34 %conv = sitofp i64 %a to double35 ret double %conv36 }37 38 attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" }39 40 !llvm.module.flags = !{!0}41 !llvm.ident = !{!1}42 43 !0 = !{i32 1, !"wchar_size", i32 4}44 !1 = !{!"clang version 7.0.0"}45 46...47---48name: int32_to_float49alignment: 1650legalized: true51regBankSelected: true52tracksRegLiveness: true53registers:54 - { id: 0, class: gpr }55 - { id: 1, class: vecr }56 - { id: 2, class: vecr }57body: |58 bb.1.entry:59 liveins: $edi60 61 ; CHECK-LABEL: name: int32_to_float62 ; CHECK: liveins: $edi63 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi64 ; CHECK: %1:fr32 = nofpexcept CVTSI2SSrr [[COPY]], implicit $mxcsr65 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %166 ; CHECK: $xmm0 = COPY [[COPY1]]67 ; CHECK: RET 0, implicit $xmm068 %0:gpr(s32) = COPY $edi69 %1:vecr(s32) = G_SITOFP %0(s32)70 %2:vecr(s128) = G_ANYEXT %1(s32)71 $xmm0 = COPY %2(s128)72 RET 0, implicit $xmm073 74...75---76name: int64_to_float77alignment: 1678legalized: true79regBankSelected: true80tracksRegLiveness: true81registers:82 - { id: 0, class: gpr }83 - { id: 1, class: vecr }84 - { id: 2, class: vecr }85body: |86 bb.1.entry:87 liveins: $rdi88 89 ; CHECK-LABEL: name: int64_to_float90 ; CHECK: liveins: $rdi91 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi92 ; CHECK: %1:fr32 = nofpexcept CVTSI642SSrr [[COPY]], implicit $mxcsr93 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %194 ; CHECK: $xmm0 = COPY [[COPY1]]95 ; CHECK: RET 0, implicit $xmm096 %0:gpr(s64) = COPY $rdi97 %1:vecr(s32) = G_SITOFP %0(s64)98 %2:vecr(s128) = G_ANYEXT %1(s32)99 $xmm0 = COPY %2(s128)100 RET 0, implicit $xmm0101 102...103---104name: int32_to_double105alignment: 16106legalized: true107regBankSelected: true108tracksRegLiveness: true109registers:110 - { id: 0, class: gpr }111 - { id: 1, class: vecr }112 - { id: 2, class: vecr }113body: |114 bb.1.entry:115 liveins: $edi116 117 ; CHECK-LABEL: name: int32_to_double118 ; CHECK: liveins: $edi119 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi120 ; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]121 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]]122 ; CHECK: $xmm0 = COPY [[COPY1]]123 ; CHECK: RET 0, implicit $xmm0124 %0:gpr(s32) = COPY $edi125 %1:vecr(s64) = G_SITOFP %0(s32)126 %2:vecr(s128) = G_ANYEXT %1(s64)127 $xmm0 = COPY %2(s128)128 RET 0, implicit $xmm0129 130...131---132name: int64_to_double133alignment: 16134legalized: true135regBankSelected: true136tracksRegLiveness: true137registers:138 - { id: 0, class: gpr }139 - { id: 1, class: vecr }140 - { id: 2, class: vecr }141body: |142 bb.1.entry:143 liveins: $rdi144 145 ; CHECK-LABEL: name: int64_to_double146 ; CHECK: liveins: $rdi147 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi148 ; CHECK: %1:fr64 = nofpexcept CVTSI642SDrr [[COPY]], implicit $mxcsr149 ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %1150 ; CHECK: $xmm0 = COPY [[COPY1]]151 ; CHECK: RET 0, implicit $xmm0152 %0:gpr(s64) = COPY $rdi153 %1:vecr(s64) = G_SITOFP %0(s64)154 %2:vecr(s128) = G_ANYEXT %1(s64)155 $xmm0 = COPY %2(s128)156 RET 0, implicit $xmm0157 158...159