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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 6 define i8 @zext_i1_to_i8(i1 %val) {7 %res = zext i1 %val to i88 ret i8 %res9 }10 11 define i16 @zext_i1_to_i16(i1 %val) {12 %res = zext i1 %val to i1613 ret i16 %res14 }15 16 define i32 @zext_i1_to_i32(i1 %val) {17 %res = zext i1 %val to i3218 ret i32 %res19 }20 21 define i64 @zext_i1_to_i64(i1 %val) {22 %res = zext i1 %val to i6423 ret i64 %res24 }25 26 define i16 @zext_i8_to_i16(i8 %val) {27 %res = zext i8 %val to i1628 ret i16 %res29 }30 31 define i32 @zext_i8_to_i32(i8 %val) {32 %res = zext i8 %val to i3233 ret i32 %res34 }35 36 define i64 @zext_i8_to_i64(i8 %val) {37 %res = zext i8 %val to i6438 ret i64 %res39 }40 41 define i32 @zext_i16_to_i32(i16 %val) {42 %res = zext i16 %val to i3243 ret i32 %res44 }45 46 define i64 @zext_i16_to_i64(i16 %val) {47 %res = zext i16 %val to i6448 ret i64 %res49 }50 51 define i64 @zext_i32_to_i64(i32 %val) {52 %res = zext i32 %val to i6453 ret i64 %res54 }55 56...57---58name: zext_i1_to_i859alignment: 1660legalized: true61regBankSelected: true62tracksRegLiveness: true63registers:64 - { id: 0, class: _ }65 - { id: 1, class: gpr }66 - { id: 2, class: gpr }67 - { id: 3, class: gpr }68 - { id: 4, class: gpr }69body: |70 bb.1 (%ir-block.0):71 liveins: $edi72 73 ; CHECK-LABEL: name: zext_i1_to_i874 ; CHECK: liveins: $edi75 ; CHECK-NEXT: {{ $}}76 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi77 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit78 ; CHECK-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def dead $eflags79 ; CHECK-NEXT: $al = COPY [[AND8ri]]80 ; CHECK-NEXT: RET 0, implicit $al81 %1:gpr(s32) = COPY $edi82 %3:gpr(s8) = G_CONSTANT i8 183 %4:gpr(s8) = G_TRUNC %1(s32)84 %2:gpr(s8) = G_AND %4, %385 $al = COPY %2(s8)86 RET 0, implicit $al87 88...89---90name: zext_i1_to_i1691alignment: 1692legalized: true93regBankSelected: true94tracksRegLiveness: true95registers:96 - { id: 0, class: _ }97 - { id: 1, class: gpr }98 - { id: 2, class: gpr }99 - { id: 3, class: gpr }100 - { id: 4, class: gpr }101body: |102 bb.1 (%ir-block.0):103 liveins: $edi104 105 ; CHECK-LABEL: name: zext_i1_to_i16106 ; CHECK: liveins: $edi107 ; CHECK-NEXT: {{ $}}108 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi109 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit110 ; CHECK-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def dead $eflags111 ; CHECK-NEXT: $ax = COPY [[AND16ri]]112 ; CHECK-NEXT: RET 0, implicit $ax113 %1:gpr(s32) = COPY $edi114 %3:gpr(s16) = G_CONSTANT i16 1115 %4:gpr(s16) = G_TRUNC %1(s32)116 %2:gpr(s16) = G_AND %4, %3117 $ax = COPY %2(s16)118 RET 0, implicit $ax119 120...121---122name: zext_i1_to_i32123alignment: 16124legalized: true125regBankSelected: true126tracksRegLiveness: true127registers:128 - { id: 0, class: _ }129 - { id: 1, class: gpr }130 - { id: 2, class: gpr }131 - { id: 3, class: gpr }132 - { id: 4, class: gpr }133body: |134 bb.1 (%ir-block.0):135 liveins: $edi136 137 ; CHECK-LABEL: name: zext_i1_to_i32138 ; CHECK: liveins: $edi139 ; CHECK-NEXT: {{ $}}140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi141 ; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def dead $eflags142 ; CHECK-NEXT: $eax = COPY [[AND32ri]]143 ; CHECK-NEXT: RET 0, implicit $eax144 %1:gpr(s32) = COPY $edi145 %3:gpr(s32) = G_CONSTANT i32 1146 %4:gpr(s32) = COPY %1(s32)147 %2:gpr(s32) = G_AND %4, %3148 $eax = COPY %2(s32)149 RET 0, implicit $eax150 151...152---153name: zext_i1_to_i64154alignment: 16155legalized: true156regBankSelected: true157tracksRegLiveness: true158registers:159 - { id: 0, class: _ }160 - { id: 1, class: gpr }161 - { id: 2, class: gpr }162 - { id: 3, class: gpr }163 - { id: 4, class: gpr }164body: |165 bb.1 (%ir-block.0):166 liveins: $edi167 168 ; CHECK-LABEL: name: zext_i1_to_i64169 ; CHECK: liveins: $edi170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi172 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF173 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit174 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def dead $eflags175 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]176 ; CHECK-NEXT: RET 0, implicit $rax177 %1:gpr(s32) = COPY $edi178 %3:gpr(s64) = G_CONSTANT i64 1179 %4:gpr(s64) = G_ANYEXT %1(s32)180 %2:gpr(s64) = G_AND %4, %3181 $rax = COPY %2(s64)182 RET 0, implicit $rax183 184...185---186name: zext_i8_to_i16187alignment: 16188legalized: true189regBankSelected: true190tracksRegLiveness: true191registers:192 - { id: 0, class: _ }193 - { id: 1, class: gpr }194 - { id: 2, class: gpr }195 - { id: 3, class: gpr }196 - { id: 4, class: gpr }197body: |198 bb.1 (%ir-block.0):199 liveins: $edi200 201 ; CHECK-LABEL: name: zext_i8_to_i16202 ; CHECK: liveins: $edi203 ; CHECK-NEXT: {{ $}}204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit206 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit207 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]208 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit209 ; CHECK-NEXT: $ax = COPY [[COPY3]]210 ; CHECK-NEXT: RET 0, implicit $ax211 %1:gpr(s32) = COPY $edi212 %3:gpr(s16) = G_CONSTANT i16 255213 %4:gpr(s16) = G_TRUNC %1(s32)214 %2:gpr(s16) = G_AND %4, %3215 $ax = COPY %2(s16)216 RET 0, implicit $ax217 218...219---220name: zext_i8_to_i32221alignment: 16222legalized: true223regBankSelected: true224tracksRegLiveness: true225registers:226 - { id: 0, class: _ }227 - { id: 1, class: gpr }228 - { id: 2, class: gpr }229 - { id: 3, class: gpr }230 - { id: 4, class: gpr }231body: |232 bb.1 (%ir-block.0):233 liveins: $edi234 235 ; CHECK-LABEL: name: zext_i8_to_i32236 ; CHECK: liveins: $edi237 ; CHECK-NEXT: {{ $}}238 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi239 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit240 ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]241 ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]242 ; CHECK-NEXT: RET 0, implicit $eax243 %1:gpr(s32) = COPY $edi244 %3:gpr(s32) = G_CONSTANT i32 255245 %4:gpr(s32) = COPY %1(s32)246 %2:gpr(s32) = G_AND %4, %3247 $eax = COPY %2(s32)248 RET 0, implicit $eax249 250...251---252name: zext_i8_to_i64253alignment: 16254legalized: true255regBankSelected: true256tracksRegLiveness: true257registers:258 - { id: 0, class: _ }259 - { id: 1, class: gpr }260 - { id: 2, class: gpr }261 - { id: 3, class: gpr }262 - { id: 4, class: gpr }263body: |264 bb.1 (%ir-block.0):265 liveins: $edi266 267 ; CHECK-LABEL: name: zext_i8_to_i64268 ; CHECK: liveins: $edi269 ; CHECK-NEXT: {{ $}}270 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi271 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF272 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit273 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def dead $eflags274 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]275 ; CHECK-NEXT: RET 0, implicit $rax276 %1:gpr(s32) = COPY $edi277 %3:gpr(s64) = G_CONSTANT i64 255278 %4:gpr(s64) = G_ANYEXT %1(s32)279 %2:gpr(s64) = G_AND %4, %3280 $rax = COPY %2(s64)281 RET 0, implicit $rax282 283...284---285name: zext_i16_to_i32286alignment: 16287legalized: true288regBankSelected: true289tracksRegLiveness: true290registers:291 - { id: 0, class: _ }292 - { id: 1, class: gpr }293 - { id: 2, class: gpr }294 - { id: 3, class: gpr }295 - { id: 4, class: gpr }296body: |297 bb.1 (%ir-block.0):298 liveins: $edi299 300 ; CHECK-LABEL: name: zext_i16_to_i32301 ; CHECK: liveins: $edi302 ; CHECK-NEXT: {{ $}}303 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi304 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit305 ; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]306 ; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]]307 ; CHECK-NEXT: RET 0, implicit $eax308 %1:gpr(s32) = COPY $edi309 %3:gpr(s32) = G_CONSTANT i32 65535310 %4:gpr(s32) = COPY %1(s32)311 %2:gpr(s32) = G_AND %4, %3312 $eax = COPY %2(s32)313 RET 0, implicit $eax314 315...316---317name: zext_i16_to_i64318alignment: 16319legalized: true320regBankSelected: true321tracksRegLiveness: true322registers:323 - { id: 0, class: _ }324 - { id: 1, class: gpr }325 - { id: 2, class: gpr }326 - { id: 3, class: gpr }327 - { id: 4, class: gpr }328body: |329 bb.1 (%ir-block.0):330 liveins: $edi331 332 ; CHECK-LABEL: name: zext_i16_to_i64333 ; CHECK: liveins: $edi334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi336 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF337 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit338 ; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def dead $eflags339 ; CHECK-NEXT: $rax = COPY [[AND64ri32_]]340 ; CHECK-NEXT: RET 0, implicit $rax341 %1:gpr(s32) = COPY $edi342 %3:gpr(s64) = G_CONSTANT i64 65535343 %4:gpr(s64) = G_ANYEXT %1(s32)344 %2:gpr(s64) = G_AND %4, %3345 $rax = COPY %2(s64)346 RET 0, implicit $rax347 348...349---350name: zext_i32_to_i64351alignment: 16352legalized: true353regBankSelected: true354tracksRegLiveness: true355registers:356 - { id: 0, class: gpr }357 - { id: 1, class: gpr }358body: |359 bb.1 (%ir-block.0):360 liveins: $edi361 362 ; CHECK-LABEL: name: zext_i32_to_i64363 ; CHECK: liveins: $edi364 ; CHECK-NEXT: {{ $}}365 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi366 ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]367 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit368 ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]369 ; CHECK-NEXT: RET 0, implicit $rax370 %0:gpr(s32) = COPY $edi371 %1:gpr(s64) = G_ZEXT %0(s32)372 $rax = COPY %1(s64)373 RET 0, implicit $rax374 375...376