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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX13; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX24; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX5125 6;7; trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b)8;9 10define <32 x i8> @abd_ext_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {11; AVX1-LABEL: abd_ext_v32i8:12; AVX1: # %bb.0:13; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm214; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm315; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm416; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm217; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm218; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm319; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm020; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm021; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm022; AVX1-NEXT: retq23;24; AVX2-LABEL: abd_ext_v32i8:25; AVX2: # %bb.0:26; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm227; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm028; AVX2-NEXT: vpsubb %ymm2, %ymm0, %ymm029; AVX2-NEXT: retq30;31; AVX512-LABEL: abd_ext_v32i8:32; AVX512: # %bb.0:33; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm234; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm035; AVX512-NEXT: vpsubb %ymm2, %ymm0, %ymm036; AVX512-NEXT: retq37 %aext = sext <32 x i8> %a to <32 x i64>38 %bext = sext <32 x i8> %b to <32 x i64>39 %sub = sub <32 x i64> %aext, %bext40 %abs = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %sub, i1 false)41 %trunc = trunc <32 x i64> %abs to <32 x i8>42 ret <32 x i8> %trunc43}44 45define <32 x i8> @abd_ext_v32i8_undef(<32 x i8> %a, <32 x i8> %b) nounwind {46; AVX1-LABEL: abd_ext_v32i8_undef:47; AVX1: # %bb.0:48; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm249; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm350; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm451; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm252; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm253; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm354; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm055; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm056; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm057; AVX1-NEXT: retq58;59; AVX2-LABEL: abd_ext_v32i8_undef:60; AVX2: # %bb.0:61; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm262; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm063; AVX2-NEXT: vpsubb %ymm2, %ymm0, %ymm064; AVX2-NEXT: retq65;66; AVX512-LABEL: abd_ext_v32i8_undef:67; AVX512: # %bb.0:68; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm269; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm070; AVX512-NEXT: vpsubb %ymm2, %ymm0, %ymm071; AVX512-NEXT: retq72 %aext = sext <32 x i8> %a to <32 x i64>73 %bext = sext <32 x i8> %b to <32 x i64>74 %sub = sub <32 x i64> %aext, %bext75 %abs = call <32 x i64> @llvm.abs.v32i64(<32 x i64> %sub, i1 true)76 %trunc = trunc <32 x i64> %abs to <32 x i8>77 ret <32 x i8> %trunc78}79 80define <16 x i16> @abd_ext_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {81; AVX1-LABEL: abd_ext_v16i16:82; AVX1: # %bb.0:83; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm284; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm385; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm486; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm287; AVX1-NEXT: vpsubw %xmm4, %xmm2, %xmm288; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm389; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm090; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm091; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm092; AVX1-NEXT: retq93;94; AVX2-LABEL: abd_ext_v16i16:95; AVX2: # %bb.0:96; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm297; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm098; AVX2-NEXT: vpsubw %ymm2, %ymm0, %ymm099; AVX2-NEXT: retq100;101; AVX512-LABEL: abd_ext_v16i16:102; AVX512: # %bb.0:103; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm2104; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0105; AVX512-NEXT: vpsubw %ymm2, %ymm0, %ymm0106; AVX512-NEXT: retq107 %aext = sext <16 x i16> %a to <16 x i64>108 %bext = sext <16 x i16> %b to <16 x i64>109 %sub = sub <16 x i64> %aext, %bext110 %abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 false)111 %trunc = trunc <16 x i64> %abs to <16 x i16>112 ret <16 x i16> %trunc113}114 115define <16 x i16> @abd_ext_v16i16_undef(<16 x i16> %a, <16 x i16> %b) nounwind {116; AVX1-LABEL: abd_ext_v16i16_undef:117; AVX1: # %bb.0:118; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2119; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3120; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm4121; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2122; AVX1-NEXT: vpsubw %xmm4, %xmm2, %xmm2123; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm3124; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0125; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0126; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0127; AVX1-NEXT: retq128;129; AVX2-LABEL: abd_ext_v16i16_undef:130; AVX2: # %bb.0:131; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm2132; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0133; AVX2-NEXT: vpsubw %ymm2, %ymm0, %ymm0134; AVX2-NEXT: retq135;136; AVX512-LABEL: abd_ext_v16i16_undef:137; AVX512: # %bb.0:138; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm2139; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0140; AVX512-NEXT: vpsubw %ymm2, %ymm0, %ymm0141; AVX512-NEXT: retq142 %aext = sext <16 x i16> %a to <16 x i64>143 %bext = sext <16 x i16> %b to <16 x i64>144 %sub = sub <16 x i64> %aext, %bext145 %abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 true)146 %trunc = trunc <16 x i64> %abs to <16 x i16>147 ret <16 x i16> %trunc148}149 150define <8 x i32> @abd_ext_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {151; AVX1-LABEL: abd_ext_v8i32:152; AVX1: # %bb.0:153; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2154; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3155; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm4156; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2157; AVX1-NEXT: vpsubd %xmm4, %xmm2, %xmm2158; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3159; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0160; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0161; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0162; AVX1-NEXT: retq163;164; AVX2-LABEL: abd_ext_v8i32:165; AVX2: # %bb.0:166; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm2167; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0168; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0169; AVX2-NEXT: retq170;171; AVX512-LABEL: abd_ext_v8i32:172; AVX512: # %bb.0:173; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm2174; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0175; AVX512-NEXT: vpsubd %ymm2, %ymm0, %ymm0176; AVX512-NEXT: retq177 %aext = sext <8 x i32> %a to <8 x i64>178 %bext = sext <8 x i32> %b to <8 x i64>179 %sub = sub <8 x i64> %aext, %bext180 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 false)181 %trunc = trunc <8 x i64> %abs to <8 x i32>182 ret <8 x i32> %trunc183}184 185define <8 x i32> @abd_ext_v8i32_undef(<8 x i32> %a, <8 x i32> %b) nounwind {186; AVX1-LABEL: abd_ext_v8i32_undef:187; AVX1: # %bb.0:188; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2189; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3190; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm4191; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2192; AVX1-NEXT: vpsubd %xmm4, %xmm2, %xmm2193; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3194; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0195; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0196; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0197; AVX1-NEXT: retq198;199; AVX2-LABEL: abd_ext_v8i32_undef:200; AVX2: # %bb.0:201; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm2202; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0203; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0204; AVX2-NEXT: retq205;206; AVX512-LABEL: abd_ext_v8i32_undef:207; AVX512: # %bb.0:208; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm2209; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0210; AVX512-NEXT: vpsubd %ymm2, %ymm0, %ymm0211; AVX512-NEXT: retq212 %aext = sext <8 x i32> %a to <8 x i64>213 %bext = sext <8 x i32> %b to <8 x i64>214 %sub = sub <8 x i64> %aext, %bext215 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 true)216 %trunc = trunc <8 x i64> %abs to <8 x i32>217 ret <8 x i32> %trunc218}219 220define <4 x i64> @abd_ext_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {221; AVX1-LABEL: abd_ext_v4i64:222; AVX1: # %bb.0:223; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2224; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3225; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4226; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2227; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2228; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2229; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3230; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0231; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0232; AVX1-NEXT: vpsubq %xmm0, %xmm3, %xmm0233; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0234; AVX1-NEXT: retq235;236; AVX2-LABEL: abd_ext_v4i64:237; AVX2: # %bb.0:238; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2239; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0240; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0241; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0242; AVX2-NEXT: retq243;244; AVX512-LABEL: abd_ext_v4i64:245; AVX512: # %bb.0:246; AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm2247; AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0248; AVX512-NEXT: vpsubq %ymm2, %ymm0, %ymm0249; AVX512-NEXT: retq250 %aext = sext <4 x i64> %a to <4 x i128>251 %bext = sext <4 x i64> %b to <4 x i128>252 %sub = sub <4 x i128> %aext, %bext253 %abs = call <4 x i128> @llvm.abs.v4i128(<4 x i128> %sub, i1 false)254 %trunc = trunc <4 x i128> %abs to <4 x i64>255 ret <4 x i64> %trunc256}257 258define <4 x i64> @abd_ext_v4i64_undef(<4 x i64> %a, <4 x i64> %b) nounwind {259; AVX1-LABEL: abd_ext_v4i64_undef:260; AVX1: # %bb.0:261; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2262; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3263; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4264; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2265; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2266; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2267; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3268; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0269; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0270; AVX1-NEXT: vpsubq %xmm0, %xmm3, %xmm0271; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0272; AVX1-NEXT: retq273;274; AVX2-LABEL: abd_ext_v4i64_undef:275; AVX2: # %bb.0:276; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2277; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0278; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0279; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0280; AVX2-NEXT: retq281;282; AVX512-LABEL: abd_ext_v4i64_undef:283; AVX512: # %bb.0:284; AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm2285; AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0286; AVX512-NEXT: vpsubq %ymm2, %ymm0, %ymm0287; AVX512-NEXT: retq288 %aext = sext <4 x i64> %a to <4 x i128>289 %bext = sext <4 x i64> %b to <4 x i128>290 %sub = sub <4 x i128> %aext, %bext291 %abs = call <4 x i128> @llvm.abs.v4i128(<4 x i128> %sub, i1 true)292 %trunc = trunc <4 x i128> %abs to <4 x i64>293 ret <4 x i64> %trunc294}295 296;297; sub(smax(a,b),smin(a,b)) -> abds(a,b)298;299 300define <32 x i8> @abd_minmax_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {301; AVX1-LABEL: abd_minmax_v32i8:302; AVX1: # %bb.0:303; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2304; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3305; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm4306; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2307; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2308; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm3309; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0310; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0311; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0312; AVX1-NEXT: retq313;314; AVX2-LABEL: abd_minmax_v32i8:315; AVX2: # %bb.0:316; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm2317; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0318; AVX2-NEXT: vpsubb %ymm2, %ymm0, %ymm0319; AVX2-NEXT: retq320;321; AVX512-LABEL: abd_minmax_v32i8:322; AVX512: # %bb.0:323; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm2324; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0325; AVX512-NEXT: vpsubb %ymm2, %ymm0, %ymm0326; AVX512-NEXT: retq327 %min = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %a, <32 x i8> %b)328 %max = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %a, <32 x i8> %b)329 %sub = sub <32 x i8> %max, %min330 ret <32 x i8> %sub331}332 333define <16 x i16> @abd_minmax_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {334; AVX1-LABEL: abd_minmax_v16i16:335; AVX1: # %bb.0:336; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2337; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3338; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm4339; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2340; AVX1-NEXT: vpsubw %xmm4, %xmm2, %xmm2341; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm3342; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0343; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0344; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0345; AVX1-NEXT: retq346;347; AVX2-LABEL: abd_minmax_v16i16:348; AVX2: # %bb.0:349; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm2350; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0351; AVX2-NEXT: vpsubw %ymm2, %ymm0, %ymm0352; AVX2-NEXT: retq353;354; AVX512-LABEL: abd_minmax_v16i16:355; AVX512: # %bb.0:356; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm2357; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0358; AVX512-NEXT: vpsubw %ymm2, %ymm0, %ymm0359; AVX512-NEXT: retq360 %min = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %a, <16 x i16> %b)361 %max = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %a, <16 x i16> %b)362 %sub = sub <16 x i16> %max, %min363 ret <16 x i16> %sub364}365 366define <8 x i32> @abd_minmax_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {367; AVX1-LABEL: abd_minmax_v8i32:368; AVX1: # %bb.0:369; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2370; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3371; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm4372; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2373; AVX1-NEXT: vpsubd %xmm4, %xmm2, %xmm2374; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3375; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0376; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0377; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0378; AVX1-NEXT: retq379;380; AVX2-LABEL: abd_minmax_v8i32:381; AVX2: # %bb.0:382; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm2383; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0384; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0385; AVX2-NEXT: retq386;387; AVX512-LABEL: abd_minmax_v8i32:388; AVX512: # %bb.0:389; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm2390; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0391; AVX512-NEXT: vpsubd %ymm2, %ymm0, %ymm0392; AVX512-NEXT: retq393 %min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %a, <8 x i32> %b)394 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %a, <8 x i32> %b)395 %sub = sub <8 x i32> %max, %min396 ret <8 x i32> %sub397}398 399define <4 x i64> @abd_minmax_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {400; AVX1-LABEL: abd_minmax_v4i64:401; AVX1: # %bb.0:402; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2403; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3404; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4405; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2406; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2407; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2408; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3409; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0410; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0411; AVX1-NEXT: vpsubq %xmm0, %xmm3, %xmm0412; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0413; AVX1-NEXT: retq414;415; AVX2-LABEL: abd_minmax_v4i64:416; AVX2: # %bb.0:417; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2418; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0419; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0420; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0421; AVX2-NEXT: retq422;423; AVX512-LABEL: abd_minmax_v4i64:424; AVX512: # %bb.0:425; AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm2426; AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0427; AVX512-NEXT: vpsubq %ymm2, %ymm0, %ymm0428; AVX512-NEXT: retq429 %min = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %a, <4 x i64> %b)430 %max = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %a, <4 x i64> %b)431 %sub = sub <4 x i64> %max, %min432 ret <4 x i64> %sub433}434 435;436; select(icmp(a,b),sub(a,b),sub(b,a)) -> abds(a,b)437;438 439define <32 x i8> @abd_cmp_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {440; AVX1-LABEL: abd_cmp_v32i8:441; AVX1: # %bb.0:442; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2443; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3444; AVX1-NEXT: vpminsb %xmm2, %xmm3, %xmm4445; AVX1-NEXT: vpmaxsb %xmm2, %xmm3, %xmm2446; AVX1-NEXT: vpsubb %xmm4, %xmm2, %xmm2447; AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm3448; AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0449; AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0450; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0451; AVX1-NEXT: retq452;453; AVX2-LABEL: abd_cmp_v32i8:454; AVX2: # %bb.0:455; AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm2456; AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0457; AVX2-NEXT: vpsubb %ymm2, %ymm0, %ymm0458; AVX2-NEXT: retq459;460; AVX512-LABEL: abd_cmp_v32i8:461; AVX512: # %bb.0:462; AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm2463; AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0464; AVX512-NEXT: vpsubb %ymm2, %ymm0, %ymm0465; AVX512-NEXT: retq466 %cmp = icmp sgt <32 x i8> %a, %b467 %ab = sub <32 x i8> %a, %b468 %ba = sub <32 x i8> %b, %a469 %sel = select <32 x i1> %cmp, <32 x i8> %ab, <32 x i8> %ba470 ret <32 x i8> %sel471}472 473define <16 x i16> @abd_cmp_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {474; AVX1-LABEL: abd_cmp_v16i16:475; AVX1: # %bb.0:476; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2477; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3478; AVX1-NEXT: vpminsw %xmm2, %xmm3, %xmm4479; AVX1-NEXT: vpmaxsw %xmm2, %xmm3, %xmm2480; AVX1-NEXT: vpsubw %xmm4, %xmm2, %xmm2481; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm3482; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0483; AVX1-NEXT: vpsubw %xmm3, %xmm0, %xmm0484; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0485; AVX1-NEXT: retq486;487; AVX2-LABEL: abd_cmp_v16i16:488; AVX2: # %bb.0:489; AVX2-NEXT: vpminsw %ymm1, %ymm0, %ymm2490; AVX2-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0491; AVX2-NEXT: vpsubw %ymm2, %ymm0, %ymm0492; AVX2-NEXT: retq493;494; AVX512-LABEL: abd_cmp_v16i16:495; AVX512: # %bb.0:496; AVX512-NEXT: vpminsw %ymm1, %ymm0, %ymm2497; AVX512-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0498; AVX512-NEXT: vpsubw %ymm2, %ymm0, %ymm0499; AVX512-NEXT: retq500 %cmp = icmp sge <16 x i16> %a, %b501 %ab = sub <16 x i16> %a, %b502 %ba = sub <16 x i16> %b, %a503 %sel = select <16 x i1> %cmp, <16 x i16> %ab, <16 x i16> %ba504 ret <16 x i16> %sel505}506 507define <8 x i32> @abd_cmp_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {508; AVX1-LABEL: abd_cmp_v8i32:509; AVX1: # %bb.0:510; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2511; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3512; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm4513; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2514; AVX1-NEXT: vpsubd %xmm4, %xmm2, %xmm2515; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm3516; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0517; AVX1-NEXT: vpsubd %xmm3, %xmm0, %xmm0518; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0519; AVX1-NEXT: retq520;521; AVX2-LABEL: abd_cmp_v8i32:522; AVX2: # %bb.0:523; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm2524; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0525; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0526; AVX2-NEXT: retq527;528; AVX512-LABEL: abd_cmp_v8i32:529; AVX512: # %bb.0:530; AVX512-NEXT: vpminsd %ymm1, %ymm0, %ymm2531; AVX512-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0532; AVX512-NEXT: vpsubd %ymm2, %ymm0, %ymm0533; AVX512-NEXT: retq534 %cmp = icmp slt <8 x i32> %a, %b535 %ab = sub <8 x i32> %a, %b536 %ba = sub <8 x i32> %b, %a537 %sel = select <8 x i1> %cmp, <8 x i32> %ba, <8 x i32> %ab538 ret <8 x i32> %sel539}540 541define <4 x i64> @abd_cmp_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {542; AVX1-LABEL: abd_cmp_v4i64:543; AVX1: # %bb.0:544; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2545; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3546; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4547; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2548; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2549; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2550; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm3551; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0552; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0553; AVX1-NEXT: vpsubq %xmm0, %xmm3, %xmm0554; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0555; AVX1-NEXT: retq556;557; AVX2-LABEL: abd_cmp_v4i64:558; AVX2: # %bb.0:559; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2560; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0561; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0562; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0563; AVX2-NEXT: retq564;565; AVX512-LABEL: abd_cmp_v4i64:566; AVX512: # %bb.0:567; AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm2568; AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0569; AVX512-NEXT: vpsubq %ymm2, %ymm0, %ymm0570; AVX512-NEXT: retq571 %cmp = icmp sge <4 x i64> %a, %b572 %ab = sub <4 x i64> %a, %b573 %ba = sub <4 x i64> %b, %a574 %sel = select <4 x i1> %cmp, <4 x i64> %ab, <4 x i64> %ba575 ret <4 x i64> %sel576}577 578;579; abs(sub_nsw(x, y)) -> abds(a,b)580;581 582define <32 x i8> @abd_subnsw_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {583; AVX1-LABEL: abd_subnsw_v32i8:584; AVX1: # %bb.0:585; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2586; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3587; AVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2588; AVX1-NEXT: vpsubb %xmm1, %xmm0, %xmm0589; AVX1-NEXT: vpabsb %xmm0, %xmm0590; AVX1-NEXT: vpabsb %xmm2, %xmm1591; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0592; AVX1-NEXT: retq593;594; AVX2-LABEL: abd_subnsw_v32i8:595; AVX2: # %bb.0:596; AVX2-NEXT: vpsubb %ymm1, %ymm0, %ymm0597; AVX2-NEXT: vpabsb %ymm0, %ymm0598; AVX2-NEXT: retq599;600; AVX512-LABEL: abd_subnsw_v32i8:601; AVX512: # %bb.0:602; AVX512-NEXT: vpsubb %ymm1, %ymm0, %ymm0603; AVX512-NEXT: vpabsb %ymm0, %ymm0604; AVX512-NEXT: retq605 %sub = sub nsw <32 x i8> %a, %b606 %abs = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %sub, i1 false)607 ret <32 x i8> %abs608}609 610define <16 x i16> @abd_subnsw_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {611; AVX1-LABEL: abd_subnsw_v16i16:612; AVX1: # %bb.0:613; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2614; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3615; AVX1-NEXT: vpsubw %xmm2, %xmm3, %xmm2616; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0617; AVX1-NEXT: vpabsw %xmm0, %xmm0618; AVX1-NEXT: vpabsw %xmm2, %xmm1619; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0620; AVX1-NEXT: retq621;622; AVX2-LABEL: abd_subnsw_v16i16:623; AVX2: # %bb.0:624; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0625; AVX2-NEXT: vpabsw %ymm0, %ymm0626; AVX2-NEXT: retq627;628; AVX512-LABEL: abd_subnsw_v16i16:629; AVX512: # %bb.0:630; AVX512-NEXT: vpsubw %ymm1, %ymm0, %ymm0631; AVX512-NEXT: vpabsw %ymm0, %ymm0632; AVX512-NEXT: retq633 %sub = sub nsw <16 x i16> %a, %b634 %abs = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %sub, i1 false)635 ret <16 x i16> %abs636}637 638define <8 x i32> @abd_subnsw_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {639; AVX1-LABEL: abd_subnsw_v8i32:640; AVX1: # %bb.0:641; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2642; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3643; AVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2644; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0645; AVX1-NEXT: vpabsd %xmm0, %xmm0646; AVX1-NEXT: vpabsd %xmm2, %xmm1647; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0648; AVX1-NEXT: retq649;650; AVX2-LABEL: abd_subnsw_v8i32:651; AVX2: # %bb.0:652; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0653; AVX2-NEXT: vpabsd %ymm0, %ymm0654; AVX2-NEXT: retq655;656; AVX512-LABEL: abd_subnsw_v8i32:657; AVX512: # %bb.0:658; AVX512-NEXT: vpsubd %ymm1, %ymm0, %ymm0659; AVX512-NEXT: vpabsd %ymm0, %ymm0660; AVX512-NEXT: retq661 %sub = sub nsw <8 x i32> %a, %b662 %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 false)663 ret <8 x i32> %abs664}665 666define <4 x i64> @abd_subnsw_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {667; AVX1-LABEL: abd_subnsw_v4i64:668; AVX1: # %bb.0:669; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2670; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3671; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2672; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0673; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm1674; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3675; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2676; AVX1-NEXT: vpsubq %xmm0, %xmm3, %xmm0677; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0678; AVX1-NEXT: vblendvpd %ymm1, %ymm0, %ymm1, %ymm0679; AVX1-NEXT: retq680;681; AVX2-LABEL: abd_subnsw_v4i64:682; AVX2: # %bb.0:683; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0684; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1685; AVX2-NEXT: vpsubq %ymm0, %ymm1, %ymm1686; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm0687; AVX2-NEXT: retq688;689; AVX512-LABEL: abd_subnsw_v4i64:690; AVX512: # %bb.0:691; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0692; AVX512-NEXT: vpabsq %ymm0, %ymm0693; AVX512-NEXT: retq694 %sub = sub nsw <4 x i64> %a, %b695 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 false)696 ret <4 x i64> %abs697}698 699declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)700declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)701declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)702declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)703declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)704declare <16 x i64> @llvm.abs.v16i64(<16 x i64>, i1)705declare <32 x i64> @llvm.abs.v32i64(<32 x i64>, i1)706declare <4 x i128> @llvm.abs.v4i128(<4 x i128>, i1)707 708declare <32 x i8> @llvm.smax.v32i8(<32 x i8>, <32 x i8>)709declare <16 x i16> @llvm.smax.v16i16(<16 x i16>, <16 x i16>)710declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)711declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)712 713declare <32 x i8> @llvm.smin.v32i8(<32 x i8>, <32 x i8>)714declare <16 x i16> @llvm.smin.v16i16(<16 x i16>, <16 x i16>)715declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)716declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)717