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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE424; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX15; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX26; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX5127 8;9; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)10;11 12define <16 x i8> @abd_ext_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {13; SSE-LABEL: abd_ext_v16i8:14; SSE: # %bb.0:15; SSE-NEXT: movdqa %xmm0, %xmm216; SSE-NEXT: pminub %xmm1, %xmm217; SSE-NEXT: pmaxub %xmm1, %xmm018; SSE-NEXT: psubb %xmm2, %xmm019; SSE-NEXT: retq20;21; AVX-LABEL: abd_ext_v16i8:22; AVX: # %bb.0:23; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm224; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm025; AVX-NEXT: vpsubb %xmm2, %xmm0, %xmm026; AVX-NEXT: retq27 %aext = zext <16 x i8> %a to <16 x i64>28 %bext = zext <16 x i8> %b to <16 x i64>29 %sub = sub <16 x i64> %aext, %bext30 %abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 false)31 %trunc = trunc <16 x i64> %abs to <16 x i8>32 ret <16 x i8> %trunc33}34 35define <16 x i8> @abd_ext_v16i8_undef(<16 x i8> %a, <16 x i8> %b) nounwind {36; SSE-LABEL: abd_ext_v16i8_undef:37; SSE: # %bb.0:38; SSE-NEXT: movdqa %xmm0, %xmm239; SSE-NEXT: pminub %xmm1, %xmm240; SSE-NEXT: pmaxub %xmm1, %xmm041; SSE-NEXT: psubb %xmm2, %xmm042; SSE-NEXT: retq43;44; AVX-LABEL: abd_ext_v16i8_undef:45; AVX: # %bb.0:46; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm247; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm048; AVX-NEXT: vpsubb %xmm2, %xmm0, %xmm049; AVX-NEXT: retq50 %aext = zext <16 x i8> %a to <16 x i64>51 %bext = zext <16 x i8> %b to <16 x i64>52 %sub = sub <16 x i64> %aext, %bext53 %abs = call <16 x i64> @llvm.abs.v16i64(<16 x i64> %sub, i1 true)54 %trunc = trunc <16 x i64> %abs to <16 x i8>55 ret <16 x i8> %trunc56}57 58define <8 x i16> @abd_ext_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {59; SSE2-LABEL: abd_ext_v8i16:60; SSE2: # %bb.0:61; SSE2-NEXT: movdqa %xmm1, %xmm262; SSE2-NEXT: psubusw %xmm0, %xmm263; SSE2-NEXT: psubusw %xmm1, %xmm064; SSE2-NEXT: por %xmm2, %xmm065; SSE2-NEXT: retq66;67; SSE42-LABEL: abd_ext_v8i16:68; SSE42: # %bb.0:69; SSE42-NEXT: movdqa %xmm0, %xmm270; SSE42-NEXT: pminuw %xmm1, %xmm271; SSE42-NEXT: pmaxuw %xmm1, %xmm072; SSE42-NEXT: psubw %xmm2, %xmm073; SSE42-NEXT: retq74;75; AVX-LABEL: abd_ext_v8i16:76; AVX: # %bb.0:77; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm278; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm079; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm080; AVX-NEXT: retq81 %aext = zext <8 x i16> %a to <8 x i64>82 %bext = zext <8 x i16> %b to <8 x i64>83 %sub = sub <8 x i64> %aext, %bext84 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 false)85 %trunc = trunc <8 x i64> %abs to <8 x i16>86 ret <8 x i16> %trunc87}88 89define <8 x i16> @abd_ext_v8i16_undef(<8 x i16> %a, <8 x i16> %b) nounwind {90; SSE2-LABEL: abd_ext_v8i16_undef:91; SSE2: # %bb.0:92; SSE2-NEXT: movdqa %xmm1, %xmm293; SSE2-NEXT: psubusw %xmm0, %xmm294; SSE2-NEXT: psubusw %xmm1, %xmm095; SSE2-NEXT: por %xmm2, %xmm096; SSE2-NEXT: retq97;98; SSE42-LABEL: abd_ext_v8i16_undef:99; SSE42: # %bb.0:100; SSE42-NEXT: movdqa %xmm0, %xmm2101; SSE42-NEXT: pminuw %xmm1, %xmm2102; SSE42-NEXT: pmaxuw %xmm1, %xmm0103; SSE42-NEXT: psubw %xmm2, %xmm0104; SSE42-NEXT: retq105;106; AVX-LABEL: abd_ext_v8i16_undef:107; AVX: # %bb.0:108; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm2109; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0110; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0111; AVX-NEXT: retq112 %aext = zext <8 x i16> %a to <8 x i64>113 %bext = zext <8 x i16> %b to <8 x i64>114 %sub = sub <8 x i64> %aext, %bext115 %abs = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %sub, i1 true)116 %trunc = trunc <8 x i64> %abs to <8 x i16>117 ret <8 x i16> %trunc118}119 120define <4 x i32> @abd_ext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {121; SSE2-LABEL: abd_ext_v4i32:122; SSE2: # %bb.0:123; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]124; SSE2-NEXT: movdqa %xmm1, %xmm3125; SSE2-NEXT: pxor %xmm2, %xmm3126; SSE2-NEXT: pxor %xmm0, %xmm2127; SSE2-NEXT: pcmpgtd %xmm3, %xmm2128; SSE2-NEXT: psubd %xmm1, %xmm0129; SSE2-NEXT: pxor %xmm2, %xmm0130; SSE2-NEXT: psubd %xmm0, %xmm2131; SSE2-NEXT: movdqa %xmm2, %xmm0132; SSE2-NEXT: retq133;134; SSE42-LABEL: abd_ext_v4i32:135; SSE42: # %bb.0:136; SSE42-NEXT: movdqa %xmm0, %xmm2137; SSE42-NEXT: pminud %xmm1, %xmm2138; SSE42-NEXT: pmaxud %xmm1, %xmm0139; SSE42-NEXT: psubd %xmm2, %xmm0140; SSE42-NEXT: retq141;142; AVX-LABEL: abd_ext_v4i32:143; AVX: # %bb.0:144; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm2145; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0146; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0147; AVX-NEXT: retq148 %aext = zext <4 x i32> %a to <4 x i64>149 %bext = zext <4 x i32> %b to <4 x i64>150 %sub = sub <4 x i64> %aext, %bext151 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 false)152 %trunc = trunc <4 x i64> %abs to <4 x i32>153 ret <4 x i32> %trunc154}155 156define <4 x i32> @abd_ext_v4i32_undef(<4 x i32> %a, <4 x i32> %b) nounwind {157; SSE2-LABEL: abd_ext_v4i32_undef:158; SSE2: # %bb.0:159; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]160; SSE2-NEXT: movdqa %xmm1, %xmm3161; SSE2-NEXT: pxor %xmm2, %xmm3162; SSE2-NEXT: pxor %xmm0, %xmm2163; SSE2-NEXT: pcmpgtd %xmm3, %xmm2164; SSE2-NEXT: psubd %xmm1, %xmm0165; SSE2-NEXT: pxor %xmm2, %xmm0166; SSE2-NEXT: psubd %xmm0, %xmm2167; SSE2-NEXT: movdqa %xmm2, %xmm0168; SSE2-NEXT: retq169;170; SSE42-LABEL: abd_ext_v4i32_undef:171; SSE42: # %bb.0:172; SSE42-NEXT: movdqa %xmm0, %xmm2173; SSE42-NEXT: pminud %xmm1, %xmm2174; SSE42-NEXT: pmaxud %xmm1, %xmm0175; SSE42-NEXT: psubd %xmm2, %xmm0176; SSE42-NEXT: retq177;178; AVX-LABEL: abd_ext_v4i32_undef:179; AVX: # %bb.0:180; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm2181; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0182; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0183; AVX-NEXT: retq184 %aext = zext <4 x i32> %a to <4 x i64>185 %bext = zext <4 x i32> %b to <4 x i64>186 %sub = sub <4 x i64> %aext, %bext187 %abs = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %sub, i1 true)188 %trunc = trunc <4 x i64> %abs to <4 x i32>189 ret <4 x i32> %trunc190}191 192define <2 x i64> @abd_ext_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {193; SSE2-LABEL: abd_ext_v2i64:194; SSE2: # %bb.0:195; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]196; SSE2-NEXT: movdqa %xmm1, %xmm3197; SSE2-NEXT: pxor %xmm2, %xmm3198; SSE2-NEXT: pxor %xmm0, %xmm2199; SSE2-NEXT: movdqa %xmm2, %xmm4200; SSE2-NEXT: pcmpgtd %xmm3, %xmm4201; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]202; SSE2-NEXT: pcmpeqd %xmm3, %xmm2203; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]204; SSE2-NEXT: pand %xmm5, %xmm3205; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]206; SSE2-NEXT: por %xmm3, %xmm2207; SSE2-NEXT: psubq %xmm1, %xmm0208; SSE2-NEXT: pxor %xmm2, %xmm0209; SSE2-NEXT: psubq %xmm0, %xmm2210; SSE2-NEXT: movdqa %xmm2, %xmm0211; SSE2-NEXT: retq212;213; SSE42-LABEL: abd_ext_v2i64:214; SSE42: # %bb.0:215; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]216; SSE42-NEXT: movdqa %xmm1, %xmm3217; SSE42-NEXT: pxor %xmm2, %xmm3218; SSE42-NEXT: pxor %xmm0, %xmm2219; SSE42-NEXT: pcmpgtq %xmm3, %xmm2220; SSE42-NEXT: psubq %xmm1, %xmm0221; SSE42-NEXT: pxor %xmm2, %xmm0222; SSE42-NEXT: psubq %xmm0, %xmm2223; SSE42-NEXT: movdqa %xmm2, %xmm0224; SSE42-NEXT: retq225;226; AVX1-LABEL: abd_ext_v2i64:227; AVX1: # %bb.0:228; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]229; AVX1-NEXT: # xmm2 = mem[0,0]230; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3231; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2232; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2233; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0234; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0235; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0236; AVX1-NEXT: retq237;238; AVX2-LABEL: abd_ext_v2i64:239; AVX2: # %bb.0:240; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]241; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3242; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2243; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2244; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm0245; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0246; AVX2-NEXT: vpsubq %xmm0, %xmm2, %xmm0247; AVX2-NEXT: retq248;249; AVX512-LABEL: abd_ext_v2i64:250; AVX512: # %bb.0:251; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm2252; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0253; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0254; AVX512-NEXT: retq255 %aext = zext <2 x i64> %a to <2 x i128>256 %bext = zext <2 x i64> %b to <2 x i128>257 %sub = sub <2 x i128> %aext, %bext258 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 false)259 %trunc = trunc <2 x i128> %abs to <2 x i64>260 ret <2 x i64> %trunc261}262 263define <2 x i64> @abd_ext_v2i64_undef(<2 x i64> %a, <2 x i64> %b) nounwind {264; SSE2-LABEL: abd_ext_v2i64_undef:265; SSE2: # %bb.0:266; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]267; SSE2-NEXT: movdqa %xmm1, %xmm3268; SSE2-NEXT: pxor %xmm2, %xmm3269; SSE2-NEXT: pxor %xmm0, %xmm2270; SSE2-NEXT: movdqa %xmm2, %xmm4271; SSE2-NEXT: pcmpgtd %xmm3, %xmm4272; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]273; SSE2-NEXT: pcmpeqd %xmm3, %xmm2274; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]275; SSE2-NEXT: pand %xmm5, %xmm3276; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]277; SSE2-NEXT: por %xmm3, %xmm2278; SSE2-NEXT: psubq %xmm1, %xmm0279; SSE2-NEXT: pxor %xmm2, %xmm0280; SSE2-NEXT: psubq %xmm0, %xmm2281; SSE2-NEXT: movdqa %xmm2, %xmm0282; SSE2-NEXT: retq283;284; SSE42-LABEL: abd_ext_v2i64_undef:285; SSE42: # %bb.0:286; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]287; SSE42-NEXT: movdqa %xmm1, %xmm3288; SSE42-NEXT: pxor %xmm2, %xmm3289; SSE42-NEXT: pxor %xmm0, %xmm2290; SSE42-NEXT: pcmpgtq %xmm3, %xmm2291; SSE42-NEXT: psubq %xmm1, %xmm0292; SSE42-NEXT: pxor %xmm2, %xmm0293; SSE42-NEXT: psubq %xmm0, %xmm2294; SSE42-NEXT: movdqa %xmm2, %xmm0295; SSE42-NEXT: retq296;297; AVX1-LABEL: abd_ext_v2i64_undef:298; AVX1: # %bb.0:299; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]300; AVX1-NEXT: # xmm2 = mem[0,0]301; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3302; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2303; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2304; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0305; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0306; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0307; AVX1-NEXT: retq308;309; AVX2-LABEL: abd_ext_v2i64_undef:310; AVX2: # %bb.0:311; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]312; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3313; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2314; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2315; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm0316; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0317; AVX2-NEXT: vpsubq %xmm0, %xmm2, %xmm0318; AVX2-NEXT: retq319;320; AVX512-LABEL: abd_ext_v2i64_undef:321; AVX512: # %bb.0:322; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm2323; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0324; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0325; AVX512-NEXT: retq326 %aext = zext <2 x i64> %a to <2 x i128>327 %bext = zext <2 x i64> %b to <2 x i128>328 %sub = sub <2 x i128> %aext, %bext329 %abs = call <2 x i128> @llvm.abs.v2i128(<2 x i128> %sub, i1 true)330 %trunc = trunc <2 x i128> %abs to <2 x i64>331 ret <2 x i64> %trunc332}333 334;335; sub(umax(a,b),umin(a,b)) -> abdu(a,b)336;337 338define <16 x i8> @abd_minmax_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {339; SSE-LABEL: abd_minmax_v16i8:340; SSE: # %bb.0:341; SSE-NEXT: movdqa %xmm0, %xmm2342; SSE-NEXT: pminub %xmm1, %xmm2343; SSE-NEXT: pmaxub %xmm1, %xmm0344; SSE-NEXT: psubb %xmm2, %xmm0345; SSE-NEXT: retq346;347; AVX-LABEL: abd_minmax_v16i8:348; AVX: # %bb.0:349; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm2350; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0351; AVX-NEXT: vpsubb %xmm2, %xmm0, %xmm0352; AVX-NEXT: retq353 %min = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %b)354 %max = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %b)355 %sub = sub <16 x i8> %max, %min356 ret <16 x i8> %sub357}358 359define <8 x i16> @abd_minmax_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {360; SSE2-LABEL: abd_minmax_v8i16:361; SSE2: # %bb.0:362; SSE2-NEXT: movdqa %xmm1, %xmm2363; SSE2-NEXT: psubusw %xmm0, %xmm2364; SSE2-NEXT: psubusw %xmm1, %xmm0365; SSE2-NEXT: por %xmm2, %xmm0366; SSE2-NEXT: retq367;368; SSE42-LABEL: abd_minmax_v8i16:369; SSE42: # %bb.0:370; SSE42-NEXT: movdqa %xmm0, %xmm2371; SSE42-NEXT: pminuw %xmm1, %xmm2372; SSE42-NEXT: pmaxuw %xmm1, %xmm0373; SSE42-NEXT: psubw %xmm2, %xmm0374; SSE42-NEXT: retq375;376; AVX-LABEL: abd_minmax_v8i16:377; AVX: # %bb.0:378; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm2379; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0380; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0381; AVX-NEXT: retq382 %min = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %b)383 %max = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %b)384 %sub = sub <8 x i16> %max, %min385 ret <8 x i16> %sub386}387 388define <4 x i32> @abd_minmax_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {389; SSE2-LABEL: abd_minmax_v4i32:390; SSE2: # %bb.0:391; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]392; SSE2-NEXT: movdqa %xmm1, %xmm3393; SSE2-NEXT: pxor %xmm2, %xmm3394; SSE2-NEXT: pxor %xmm0, %xmm2395; SSE2-NEXT: pcmpgtd %xmm3, %xmm2396; SSE2-NEXT: psubd %xmm1, %xmm0397; SSE2-NEXT: pxor %xmm2, %xmm0398; SSE2-NEXT: psubd %xmm0, %xmm2399; SSE2-NEXT: movdqa %xmm2, %xmm0400; SSE2-NEXT: retq401;402; SSE42-LABEL: abd_minmax_v4i32:403; SSE42: # %bb.0:404; SSE42-NEXT: movdqa %xmm0, %xmm2405; SSE42-NEXT: pminud %xmm1, %xmm2406; SSE42-NEXT: pmaxud %xmm1, %xmm0407; SSE42-NEXT: psubd %xmm2, %xmm0408; SSE42-NEXT: retq409;410; AVX-LABEL: abd_minmax_v4i32:411; AVX: # %bb.0:412; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm2413; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0414; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0415; AVX-NEXT: retq416 %min = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)417 %max = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)418 %sub = sub <4 x i32> %max, %min419 ret <4 x i32> %sub420}421 422define <2 x i64> @abd_minmax_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {423; SSE2-LABEL: abd_minmax_v2i64:424; SSE2: # %bb.0:425; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]426; SSE2-NEXT: movdqa %xmm1, %xmm3427; SSE2-NEXT: pxor %xmm2, %xmm3428; SSE2-NEXT: pxor %xmm0, %xmm2429; SSE2-NEXT: movdqa %xmm2, %xmm4430; SSE2-NEXT: pcmpgtd %xmm3, %xmm4431; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]432; SSE2-NEXT: pcmpeqd %xmm3, %xmm2433; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]434; SSE2-NEXT: pand %xmm5, %xmm3435; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]436; SSE2-NEXT: por %xmm3, %xmm2437; SSE2-NEXT: psubq %xmm1, %xmm0438; SSE2-NEXT: pxor %xmm2, %xmm0439; SSE2-NEXT: psubq %xmm0, %xmm2440; SSE2-NEXT: movdqa %xmm2, %xmm0441; SSE2-NEXT: retq442;443; SSE42-LABEL: abd_minmax_v2i64:444; SSE42: # %bb.0:445; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]446; SSE42-NEXT: movdqa %xmm1, %xmm3447; SSE42-NEXT: pxor %xmm2, %xmm3448; SSE42-NEXT: pxor %xmm0, %xmm2449; SSE42-NEXT: pcmpgtq %xmm3, %xmm2450; SSE42-NEXT: psubq %xmm1, %xmm0451; SSE42-NEXT: pxor %xmm2, %xmm0452; SSE42-NEXT: psubq %xmm0, %xmm2453; SSE42-NEXT: movdqa %xmm2, %xmm0454; SSE42-NEXT: retq455;456; AVX1-LABEL: abd_minmax_v2i64:457; AVX1: # %bb.0:458; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]459; AVX1-NEXT: # xmm2 = mem[0,0]460; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3461; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2462; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2463; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0464; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0465; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0466; AVX1-NEXT: retq467;468; AVX2-LABEL: abd_minmax_v2i64:469; AVX2: # %bb.0:470; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]471; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3472; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2473; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2474; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm0475; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0476; AVX2-NEXT: vpsubq %xmm0, %xmm2, %xmm0477; AVX2-NEXT: retq478;479; AVX512-LABEL: abd_minmax_v2i64:480; AVX512: # %bb.0:481; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm2482; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0483; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0484; AVX512-NEXT: retq485 %min = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %a, <2 x i64> %b)486 %max = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %a, <2 x i64> %b)487 %sub = sub <2 x i64> %max, %min488 ret <2 x i64> %sub489}490 491;492; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)493;494 495define <16 x i8> @abd_cmp_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {496; SSE-LABEL: abd_cmp_v16i8:497; SSE: # %bb.0:498; SSE-NEXT: movdqa %xmm0, %xmm2499; SSE-NEXT: pminub %xmm1, %xmm2500; SSE-NEXT: pmaxub %xmm1, %xmm0501; SSE-NEXT: psubb %xmm2, %xmm0502; SSE-NEXT: retq503;504; AVX-LABEL: abd_cmp_v16i8:505; AVX: # %bb.0:506; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm2507; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0508; AVX-NEXT: vpsubb %xmm2, %xmm0, %xmm0509; AVX-NEXT: retq510 %cmp = icmp ugt <16 x i8> %a, %b511 %ab = sub <16 x i8> %a, %b512 %ba = sub <16 x i8> %b, %a513 %sel = select <16 x i1> %cmp, <16 x i8> %ab, <16 x i8> %ba514 ret <16 x i8> %sel515}516 517define <8 x i16> @abd_cmp_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {518; SSE2-LABEL: abd_cmp_v8i16:519; SSE2: # %bb.0:520; SSE2-NEXT: movdqa %xmm1, %xmm2521; SSE2-NEXT: psubusw %xmm0, %xmm2522; SSE2-NEXT: psubusw %xmm1, %xmm0523; SSE2-NEXT: por %xmm2, %xmm0524; SSE2-NEXT: retq525;526; SSE42-LABEL: abd_cmp_v8i16:527; SSE42: # %bb.0:528; SSE42-NEXT: movdqa %xmm0, %xmm2529; SSE42-NEXT: pminuw %xmm1, %xmm2530; SSE42-NEXT: pmaxuw %xmm1, %xmm0531; SSE42-NEXT: psubw %xmm2, %xmm0532; SSE42-NEXT: retq533;534; AVX-LABEL: abd_cmp_v8i16:535; AVX: # %bb.0:536; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm2537; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0538; AVX-NEXT: vpsubw %xmm2, %xmm0, %xmm0539; AVX-NEXT: retq540 %cmp = icmp uge <8 x i16> %a, %b541 %ab = sub <8 x i16> %a, %b542 %ba = sub <8 x i16> %b, %a543 %sel = select <8 x i1> %cmp, <8 x i16> %ab, <8 x i16> %ba544 ret <8 x i16> %sel545}546 547define <4 x i32> @abd_cmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {548; SSE2-LABEL: abd_cmp_v4i32:549; SSE2: # %bb.0:550; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]551; SSE2-NEXT: movdqa %xmm1, %xmm3552; SSE2-NEXT: pxor %xmm2, %xmm3553; SSE2-NEXT: pxor %xmm0, %xmm2554; SSE2-NEXT: pcmpgtd %xmm3, %xmm2555; SSE2-NEXT: psubd %xmm1, %xmm0556; SSE2-NEXT: pxor %xmm2, %xmm0557; SSE2-NEXT: psubd %xmm0, %xmm2558; SSE2-NEXT: movdqa %xmm2, %xmm0559; SSE2-NEXT: retq560;561; SSE42-LABEL: abd_cmp_v4i32:562; SSE42: # %bb.0:563; SSE42-NEXT: movdqa %xmm0, %xmm2564; SSE42-NEXT: pminud %xmm1, %xmm2565; SSE42-NEXT: pmaxud %xmm1, %xmm0566; SSE42-NEXT: psubd %xmm2, %xmm0567; SSE42-NEXT: retq568;569; AVX-LABEL: abd_cmp_v4i32:570; AVX: # %bb.0:571; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm2572; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0573; AVX-NEXT: vpsubd %xmm2, %xmm0, %xmm0574; AVX-NEXT: retq575 %cmp = icmp ult <4 x i32> %a, %b576 %ab = sub <4 x i32> %a, %b577 %ba = sub <4 x i32> %b, %a578 %sel = select <4 x i1> %cmp, <4 x i32> %ba, <4 x i32> %ab579 ret <4 x i32> %sel580}581 582define <2 x i64> @abd_cmp_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {583; SSE2-LABEL: abd_cmp_v2i64:584; SSE2: # %bb.0:585; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]586; SSE2-NEXT: movdqa %xmm1, %xmm3587; SSE2-NEXT: pxor %xmm2, %xmm3588; SSE2-NEXT: pxor %xmm0, %xmm2589; SSE2-NEXT: movdqa %xmm2, %xmm4590; SSE2-NEXT: pcmpgtd %xmm3, %xmm4591; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]592; SSE2-NEXT: pcmpeqd %xmm3, %xmm2593; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]594; SSE2-NEXT: pand %xmm5, %xmm3595; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]596; SSE2-NEXT: por %xmm3, %xmm2597; SSE2-NEXT: psubq %xmm1, %xmm0598; SSE2-NEXT: pxor %xmm2, %xmm0599; SSE2-NEXT: psubq %xmm0, %xmm2600; SSE2-NEXT: movdqa %xmm2, %xmm0601; SSE2-NEXT: retq602;603; SSE42-LABEL: abd_cmp_v2i64:604; SSE42: # %bb.0:605; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]606; SSE42-NEXT: movdqa %xmm1, %xmm3607; SSE42-NEXT: pxor %xmm2, %xmm3608; SSE42-NEXT: pxor %xmm0, %xmm2609; SSE42-NEXT: pcmpgtq %xmm3, %xmm2610; SSE42-NEXT: psubq %xmm1, %xmm0611; SSE42-NEXT: pxor %xmm2, %xmm0612; SSE42-NEXT: psubq %xmm0, %xmm2613; SSE42-NEXT: movdqa %xmm2, %xmm0614; SSE42-NEXT: retq615;616; AVX1-LABEL: abd_cmp_v2i64:617; AVX1: # %bb.0:618; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]619; AVX1-NEXT: # xmm2 = mem[0,0]620; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3621; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2622; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2623; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0624; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0625; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0626; AVX1-NEXT: retq627;628; AVX2-LABEL: abd_cmp_v2i64:629; AVX2: # %bb.0:630; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]631; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3632; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2633; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2634; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm0635; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0636; AVX2-NEXT: vpsubq %xmm0, %xmm2, %xmm0637; AVX2-NEXT: retq638;639; AVX512-LABEL: abd_cmp_v2i64:640; AVX512: # %bb.0:641; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm2642; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0643; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0644; AVX512-NEXT: retq645 %cmp = icmp uge <2 x i64> %a, %b646 %ab = sub <2 x i64> %a, %b647 %ba = sub <2 x i64> %b, %a648 %sel = select <2 x i1> %cmp, <2 x i64> %ab, <2 x i64> %ba649 ret <2 x i64> %sel650}651 652;653; Special cases654;655 656define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwind {657; SSE2-LABEL: abd_cmp_v2i64_multiuse_cmp:658; SSE2: # %bb.0:659; SSE2-NEXT: movdqa %xmm0, %xmm2660; SSE2-NEXT: psubq %xmm1, %xmm2661; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456]662; SSE2-NEXT: pxor %xmm3, %xmm1663; SSE2-NEXT: pxor %xmm3, %xmm0664; SSE2-NEXT: movdqa %xmm0, %xmm3665; SSE2-NEXT: pcmpgtd %xmm1, %xmm3666; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]667; SSE2-NEXT: pcmpeqd %xmm1, %xmm0668; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]669; SSE2-NEXT: pand %xmm4, %xmm0670; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,3,3]671; SSE2-NEXT: por %xmm0, %xmm1672; SSE2-NEXT: pxor %xmm1, %xmm2673; SSE2-NEXT: movdqa %xmm1, %xmm0674; SSE2-NEXT: psubq %xmm2, %xmm0675; SSE2-NEXT: paddq %xmm1, %xmm0676; SSE2-NEXT: retq677;678; SSE42-LABEL: abd_cmp_v2i64_multiuse_cmp:679; SSE42: # %bb.0:680; SSE42-NEXT: movdqa %xmm0, %xmm2681; SSE42-NEXT: psubq %xmm1, %xmm2682; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]683; SSE42-NEXT: pxor %xmm3, %xmm1684; SSE42-NEXT: pxor %xmm3, %xmm0685; SSE42-NEXT: pcmpgtq %xmm1, %xmm0686; SSE42-NEXT: pxor %xmm0, %xmm2687; SSE42-NEXT: movdqa %xmm0, %xmm1688; SSE42-NEXT: psubq %xmm2, %xmm1689; SSE42-NEXT: paddq %xmm1, %xmm0690; SSE42-NEXT: retq691;692; AVX1-LABEL: abd_cmp_v2i64_multiuse_cmp:693; AVX1: # %bb.0:694; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm2695; AVX1-NEXT: vmovddup {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]696; AVX1-NEXT: # xmm3 = mem[0,0]697; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm1698; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0699; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0700; AVX1-NEXT: vpxor %xmm0, %xmm2, %xmm1701; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm1702; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0703; AVX1-NEXT: retq704;705; AVX2-LABEL: abd_cmp_v2i64_multiuse_cmp:706; AVX2: # %bb.0:707; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm2708; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]709; AVX2-NEXT: vpxor %xmm3, %xmm1, %xmm1710; AVX2-NEXT: vpxor %xmm3, %xmm0, %xmm0711; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0712; AVX2-NEXT: vpxor %xmm0, %xmm2, %xmm1713; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm1714; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0715; AVX2-NEXT: retq716;717; AVX512-LABEL: abd_cmp_v2i64_multiuse_cmp:718; AVX512: # %bb.0:719; AVX512-NEXT: vpcmpnleuq %xmm1, %xmm0, %k1720; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm2721; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0722; AVX512-NEXT: vpsubq %xmm2, %xmm0, %xmm0723; AVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1724; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 {%k1}725; AVX512-NEXT: retq726 %cmp = icmp ugt <2 x i64> %a, %b727 %ab = sub <2 x i64> %a, %b728 %ba = sub <2 x i64> %b, %a729 %sel = select <2 x i1> %cmp, <2 x i64> %ab, <2 x i64> %ba730 %ext = sext <2 x i1> %cmp to <2 x i64>731 %res = add <2 x i64> %ext, %sel732 ret <2 x i64> %res733}734 735define <8 x i16> @abd_cmp_v8i16_multiuse_sub(<8 x i16> %a, <8 x i16> %b) nounwind {736; SSE2-LABEL: abd_cmp_v8i16_multiuse_sub:737; SSE2: # %bb.0:738; SSE2-NEXT: movdqa %xmm0, %xmm2739; SSE2-NEXT: psubw %xmm1, %xmm2740; SSE2-NEXT: movdqa %xmm1, %xmm3741; SSE2-NEXT: psubusw %xmm0, %xmm3742; SSE2-NEXT: psubusw %xmm1, %xmm0743; SSE2-NEXT: por %xmm3, %xmm0744; SSE2-NEXT: paddw %xmm2, %xmm0745; SSE2-NEXT: retq746;747; SSE42-LABEL: abd_cmp_v8i16_multiuse_sub:748; SSE42: # %bb.0:749; SSE42-NEXT: movdqa %xmm0, %xmm2750; SSE42-NEXT: psubw %xmm1, %xmm2751; SSE42-NEXT: movdqa %xmm0, %xmm3752; SSE42-NEXT: pminuw %xmm1, %xmm3753; SSE42-NEXT: pmaxuw %xmm1, %xmm0754; SSE42-NEXT: psubw %xmm3, %xmm0755; SSE42-NEXT: paddw %xmm2, %xmm0756; SSE42-NEXT: retq757;758; AVX-LABEL: abd_cmp_v8i16_multiuse_sub:759; AVX: # %bb.0:760; AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm2761; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm3762; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0763; AVX-NEXT: vpsubw %xmm3, %xmm0, %xmm0764; AVX-NEXT: vpaddw %xmm0, %xmm2, %xmm0765; AVX-NEXT: retq766 %cmp = icmp uge <8 x i16> %a, %b767 %ab = sub <8 x i16> %a, %b768 %ba = sub <8 x i16> %b, %a769 %sel = select <8 x i1> %cmp, <8 x i16> %ab, <8 x i16> %ba770 %res = add <8 x i16> %ab, %sel771 ret <8 x i16> %res772}773 774declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)775declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)776declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)777declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)778declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)779declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)780declare <16 x i64> @llvm.abs.v16i64(<16 x i64>, i1)781declare <2 x i128> @llvm.abs.v2i128(<2 x i128>, i1)782 783declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)784declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)785declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)786declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>)787 788declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)789declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)790declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)791declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)792