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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s3 4; These tests use adc/sbb in place of set+add/sub. Should this transform5; be enabled by micro-architecture rather than as part of generic lowering/isel?6 7; <rdar://problem/8449754>8 9define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {10; CHECK-LABEL: test1:11; CHECK: # %bb.0:12; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax13; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax14; CHECK-NEXT: adcl $0, %eax15; CHECK-NEXT: retl16 %add4 = add i32 %x, %sum17 %cmp = icmp ult i32 %add4, %x18 %inc = zext i1 %cmp to i3219 %z.0 = add i32 %add4, %inc20 ret i32 %z.021}22 23; <rdar://problem/12579915>24 25define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {26; CHECK-LABEL: test2:27; CHECK: # %bb.0:28; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax29; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx30; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx31; CHECK-NEXT: sbbl $0, %eax32; CHECK-NEXT: retl33 %cmp = icmp ugt i32 %x, %y34 %dec = sext i1 %cmp to i3235 %dec.res = add nsw i32 %dec, %res36 ret i32 %dec.res37}38 39