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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s3 4; PR30841: https://llvm.org/bugs/show_bug.cgi?id=308415; Demanded bits analysis must disable nsw/nuw when it makes a6; simplification to add/sub such as in this case.7 8define i8 @PR30841(i64 %argc) {9; CHECK-LABEL: PR30841:10; CHECK: ## %bb.0: ## %entry11; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax12; CHECK-NEXT: negb %al13; CHECK-NEXT: ## kill: def $al killed $al killed $eax14; CHECK-NEXT: retl15entry:16 %or = or i64 %argc, -429496729617 br label %end18 19end:20 %neg = sub nuw nsw i64 -4294967296, %argc21 %trunc = trunc i64 %neg to i822 ret i8 %trunc23}24 25