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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-- -mcpu=generic < %s | FileCheck %s3 4; Verify that the DAGCombiner doesn't wrongly remove the 'and' from the dag.5 6define i8 @foo(ptr %V) {7; CHECK-LABEL: foo:8; CHECK: # %bb.0:9; CHECK-NEXT: movzbl 2(%rdi), %eax10; CHECK-NEXT: andb $95, %al11; CHECK-NEXT: retq12 %V3i8 = load <3 x i8>, ptr %V, align 413 %t0 = and <3 x i8> %V3i8, <i8 undef, i8 undef, i8 95>14 %t1 = extractelement <3 x i8> %t0, i64 215 ret i8 %t116}17 18