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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: not llc -mtriple=x86_64 < %s >%t1 2>%t23; RUN: FileCheck %s <%t14; RUN: FileCheck %s <%t2 --check-prefix=ERR5; RUN: not llc -mattr=+egpr -mtriple=x86_64 < %s >%t1 2>%t26; RUN: FileCheck %s <%t17; RUN: FileCheck %s <%t2 --check-prefix=ERR8; RUN: not llc -mattr=+egpr,+inline-asm-use-gpr32 -mtriple=x86_64 < %s >%t1 2>%t29; RUN: FileCheck %s <%t110; RUN: FileCheck %s <%t2 --check-prefix=ERR11 12; CHECK: addq %r8, %rax13define void @constraint_jr_test() nounwind {14entry:15 %reg = alloca i64, align 816 %0 = load i64, ptr %reg, align 817 call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{dirflag},~{fpsr},~{flags}"(i64 %0)18 ret void19}20 21; ERR: error: inline assembly requires more registers than available22define void @constraint_jr_test_err() nounwind {23entry:24 %reg = alloca i64, align 825 %0 = load i64, ptr %reg, align 826 call void asm sideeffect "add $0, %rax", "^jr,~{rax},~{rbx},~{rbp},~{rcx},~{rdx},~{rdi},~{rsi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"(i64 %0)27 ret void28}29