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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -verify-machineinstrs | FileCheck %s3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+cf -x86-cmov-converter=false -verify-machineinstrs | FileCheck %s4 5define i8 @cfcmov8rr(i8 %0) {6; CHECK-LABEL: cfcmov8rr:7; CHECK: # %bb.0:8; CHECK-NEXT: cmpb $1, %dil9; CHECK-NEXT: cfcmovel %edi, %eax10; CHECK-NEXT: # kill: def $al killed $al killed $eax11; CHECK-NEXT: retq12 %2 = icmp eq i8 %0, 113 %3 = select i1 %2, i8 %0, i8 014 ret i8 %315}16 17define i16 @cfcmov16rr(i16 %0) {18; CHECK-LABEL: cfcmov16rr:19; CHECK: # %bb.0:20; CHECK-NEXT: cmpw $1, %di21; CHECK-NEXT: cfcmovnel %edi, %eax22; CHECK-NEXT: # kill: def $ax killed $ax killed $eax23; CHECK-NEXT: retq24 %2 = icmp ne i16 %0, 125 %3 = select i1 %2, i16 %0, i16 026 ret i16 %327}28 29define i32 @cfcmov32rr(i32 %0) {30; CHECK-LABEL: cfcmov32rr:31; CHECK: # %bb.0:32; CHECK-NEXT: cmpl $2, %edi33; CHECK-NEXT: cfcmovael %edi, %eax34; CHECK-NEXT: retq35 %2 = icmp ugt i32 %0, 136 %3 = select i1 %2, i32 %0, i32 037 ret i32 %338}39 40define i64 @cfcmov64rr(i64 %0) {41; CHECK-LABEL: cfcmov64rr:42; CHECK: # %bb.0:43; CHECK-NEXT: testq %rdi, %rdi44; CHECK-NEXT: cfcmoveq %rdi, %rax45; CHECK-NEXT: retq46 %2 = icmp ult i64 %0, 147 %3 = select i1 %2, i64 %0, i64 048 ret i64 %349}50 51define i8 @cfcmov8rr_inv(i8 %0) {52; CHECK-LABEL: cfcmov8rr_inv:53; CHECK: # %bb.0:54; CHECK-NEXT: cmpb $1, %dil55; CHECK-NEXT: cfcmovnel %edi, %eax56; CHECK-NEXT: # kill: def $al killed $al killed $eax57; CHECK-NEXT: retq58 %2 = icmp eq i8 %0, 159 %3 = select i1 %2, i8 0, i8 %060 ret i8 %361}62 63define i16 @cfcmov16rr_inv(i16 %0) {64; CHECK-LABEL: cfcmov16rr_inv:65; CHECK: # %bb.0:66; CHECK-NEXT: cmpw $1, %di67; CHECK-NEXT: cfcmovel %edi, %eax68; CHECK-NEXT: # kill: def $ax killed $ax killed $eax69; CHECK-NEXT: retq70 %2 = icmp ne i16 %0, 171 %3 = select i1 %2, i16 0, i16 %072 ret i16 %373}74 75define i32 @cfcmov32rr_inv(i32 %0) {76; CHECK-LABEL: cfcmov32rr_inv:77; CHECK: # %bb.0:78; CHECK-NEXT: cmpl $2, %edi79; CHECK-NEXT: cfcmovbl %edi, %eax80; CHECK-NEXT: retq81 %2 = icmp ugt i32 %0, 182 %3 = select i1 %2, i32 0, i32 %083 ret i32 %384}85 86define i64 @cfcmov64rr_inv(i64 %0) {87; CHECK-LABEL: cfcmov64rr_inv:88; CHECK: # %bb.0:89; CHECK-NEXT: cmpq $2, %rdi90; CHECK-NEXT: cfcmovaeq %rdi, %rax91; CHECK-NEXT: retq92 %2 = icmp ule i64 %0, 193 %3 = select i1 %2, i64 0, i64 %094 ret i64 %395}96 97define void @cfcmov16mr(ptr %p, i16 %0) {98; CHECK-LABEL: cfcmov16mr:99; CHECK: # %bb.0:100; CHECK-NEXT: movzwl (%rdi), %eax101; CHECK-NEXT: cmpw %ax, %si102; CHECK-NEXT: cfcmovlew %si, (%rdi)103; CHECK-NEXT: retq104 %2 = load i16, ptr %p, align 2105 %3 = icmp sgt i16 %0, %2106 %4 = select i1 %3, i16 %2, i16 %0107 store i16 %4, ptr %p, align 2108 ret void109}110 111define void @cfcmov32mr(ptr %p, i32 %0) {112; CHECK-LABEL: cfcmov32mr:113; CHECK: # %bb.0:114; CHECK-NEXT: cmpl (%rdi), %esi115; CHECK-NEXT: cfcmovgl %esi, (%rdi)116; CHECK-NEXT: retq117 %2 = load i32, ptr %p, align 4118 %3 = call i32 @llvm.smax.i32(i32 %0, i32 %2)119 store i32 %3, ptr %p, align 4120 ret void121}122 123define void @cfcmov64mr(ptr %p, i64 %0) {124; CHECK-LABEL: cfcmov64mr:125; CHECK: # %bb.0:126; CHECK-NEXT: cmpq (%rdi), %rsi127; CHECK-NEXT: cfcmovgq %rsi, (%rdi)128; CHECK-NEXT: retq129 %2 = load i64, ptr %p, align 8130 %3 = icmp sgt i64 %0, %2131 %4 = select i1 %3, i64 %0, i64 %2132 store i64 %4, ptr %p, align 8133 ret void134}135 136define void @volatileload(ptr %p, i32 %0) {137; CHECK-LABEL: volatileload:138; CHECK: # %bb.0:139; CHECK-NEXT: movl (%rdi), %eax140; CHECK-NEXT: cmpl %eax, %esi141; CHECK-NEXT: cmovbl %esi, %eax142; CHECK-NEXT: movl %eax, (%rdi)143; CHECK-NEXT: retq144 %2 = load volatile i32, ptr %p, align 4145 %3 = call i32 @llvm.umin.i32(i32 %0, i32 %2)146 store i32 %3, ptr %p, align 4147 ret void148}149 150define void @atomicstore(ptr %p, i64 %0) {151; CHECK-LABEL: atomicstore:152; CHECK: # %bb.0:153; CHECK-NEXT: movq (%rdi), %rax154; CHECK-NEXT: cmpq %rax, %rsi155; CHECK-NEXT: cmovaq %rsi, %rax156; CHECK-NEXT: movq %rax, (%rdi)157; CHECK-NEXT: retq158 %2 = load i64, ptr %p, align 8159 %3 = icmp ugt i64 %0, %2160 %4 = select i1 %3, i64 %0, i64 %2161 store atomic i64 %4, ptr %p unordered, align 8162 ret void163}164 165define void @loadstorediffptr(ptr %p, i32 %0) {166; CHECK-LABEL: loadstorediffptr:167; CHECK: # %bb.0:168; CHECK-NEXT: movl (%rdi), %eax169; CHECK-NEXT: cmpl %eax, %esi170; CHECK-NEXT: cmovbel %eax, %esi171; CHECK-NEXT: movl %esi, 4(%rdi)172; CHECK-NEXT: retq173 %2 = getelementptr [2 x i32], ptr %p, i32 0, i32 0174 %3 = load i32, ptr %2, align 4175 %4 = icmp ule i32 %0, %3176 %5 = select i1 %4, i32 %3, i32 %0177 %6 = getelementptr [2 x i32], ptr %p, i32 0, i32 1178 store i32 %5, ptr %6, align 4179 ret void180}181 182declare i32 @llvm.smax.i32(i32, i32)183declare i32 @llvm.umin.i32(i32, i32)184