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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=x86_64 -mattr=+nf -verify-machineinstrs | FileCheck %s3 4; This is to check no assertion raised in X86 Suppress APX for Relocation pass5; if there is a NF instruction6 7define fastcc void @foo(i32 %0, i1 %or.cond) nounwind {8; CHECK-LABEL: foo:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: pushq %rbp11; CHECK-NEXT: pushq %r1512; CHECK-NEXT: pushq %r1413; CHECK-NEXT: pushq %r1314; CHECK-NEXT: pushq %r1215; CHECK-NEXT: pushq %rbx16; CHECK-NEXT: pushq %rax17; CHECK-NEXT: movl %esi, %ebx18; CHECK-NEXT: movslq %edi, %r1519; CHECK-NEXT: leaq (,%r15,4), %rax20; CHECK-NEXT: leaq (%rax,%rax,4), %r1421; CHECK-NEXT: movl %r15d, %r12d22; CHECK-NEXT: xorl %r13d, %r13d23; CHECK-NEXT: xorl %ebp, %ebp24; CHECK-NEXT: jmp .LBB0_125; CHECK-NEXT: .p2align 426; CHECK-NEXT: .LBB0_3: # %if.end4127; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=128; CHECK-NEXT: leaq (%r12,%rbp), %rdi29; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi30; CHECK-NEXT: xorl %esi, %esi31; CHECK-NEXT: movq %r14, %rdx32; CHECK-NEXT: callq *%r1333; CHECK-NEXT: incq %rbp34; CHECK-NEXT: addq $20, %r1435; CHECK-NEXT: .LBB0_1: # %for.body3036; CHECK-NEXT: # =>This Inner Loop Header: Depth=137; CHECK-NEXT: testb $1, %bl38; CHECK-NEXT: je .LBB0_339; CHECK-NEXT: # %bb.2: # %if.then3740; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=141; CHECK-NEXT: movq %r15, %rax42; CHECK-NEXT: addq %rbp, %rax43; CHECK-NEXT: movq 0, %rax44; CHECK-NEXT: {nf} addq %r15, %rax45; CHECK-NEXT: movb $0, (%rbp,%rax)46; CHECK-NEXT: jmp .LBB0_347entry:48 %1 = sext i32 %0 to i6449 br label %for.body3050 51for.body30: ; preds = %if.end41, %entry52 %indvars.iv = phi i64 [ %1, %entry ], [ %indvars.iv.next, %if.end41 ]53 %.pre88 = trunc i64 %indvars.iv to i3254 br label %if.end16.i55 56if.then9.i: ; No predecessors!57 call fastcc void null(ptr null, i32 %.pre88)58 br label %if.end16.i59 60if.end16.i: ; preds = %if.then9.i, %for.body3061 br i1 %or.cond, label %if.then37, label %if.end4162 63if.then37: ; preds = %if.end16.i64 %2 = load ptr, ptr null, align 865 %arrayidx.i = getelementptr i8, ptr %2, i64 %indvars.iv66 store i8 0, ptr %arrayidx.i, align 167 %3 = icmp eq i64 %indvars.iv, 068 br i1 %3, label %if.end41, label %if.then.i6569 70if.then.i65: ; preds = %if.then3771 %arraydecay.i = getelementptr [5 x float], ptr null, i64 %indvars.iv, i64 -572 %4 = call <5 x float> @llvm.masked.load.v5f32.p0(ptr %arraydecay.i, i32 1, <5 x i1> zeroinitializer, <5 x float> zeroinitializer)73 br label %if.end4174 75if.end41: ; preds = %if.then.i65, %if.then37, %if.end16.i76 %arraydecay44 = getelementptr [5 x float], ptr null, i64 %indvars.iv, i64 077 call fastcc void null(i32 %.pre88, i32 0, ptr %arraydecay44)78 %indvars.iv.next = add i64 %indvars.iv, 179 %cmp29 = icmp slt i64 %indvars.iv, 080 br label %for.body3081}82 83declare <5 x float> @llvm.masked.load.v5f32.p0(ptr captures(none), i32 immarg, <5 x i1>, <5 x float>)84