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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52# RUN: llc %s -mtriple=x86_64-unknown -mattr=+ndd,+egpr -start-before=break-false-deps -show-mc-encoding -verify-machineinstrs -o - | FileCheck --check-prefixes=CHECK,RCDEFAULT %s3# RUN: llc %s -mtriple=x86_64-unknown -mattr=+ndd,+egpr -start-before=break-false-deps -partial-reg-update-clearance=1 -verify-machineinstrs -show-mc-encoding -o - | FileCheck --check-prefixes=CHECK,RC1 %s4#5# Check that BreakFalseDeps detects cases where an ND instruction would cause a partial register write6# if compressed to a legacy op. MIR has been modified to force different register assignments.7#8# For partial_write, the ADD16rr_ND is compressible, but will become a partial write after compression.9# Compression is inhibited if the eax definition is within the partial-reg-update-clearance threshold.10#11# For no_partial_write, the ADD16rr_ND is incompressible hence it cannot become a partial write.12# This case checks that an implicit-def of eax is not added by breakPartialRegDependency.13#14--- |15 define signext i16 @partial_write(ptr %p, i32 %a, i32 %b, i16 signext %x, i16 signext %y) #0 {16 ; RCDEFAULT-LABEL: partial_write:17 ; RCDEFAULT: # %bb.0: # %entry18 ; RCDEFAULT-NEXT: leal (%rdx,%rsi), %eax # encoding: [0x8d,0x04,0x32]19 ; RCDEFAULT-NEXT: movl %eax, (%rdi) # encoding: [0x89,0x07]20 ; RCDEFAULT-NEXT: addw %cx, %ax, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x01,0xc8]21 ; RCDEFAULT-NEXT: retq # encoding: [0xc3]22 ;23 ; RC1-LABEL: partial_write:24 ; RC1: # %bb.0: # %entry25 ; RC1-NEXT: leal (%rdx,%rsi), %eax # encoding: [0x8d,0x04,0x32]26 ; RC1-NEXT: movl %eax, (%rdi) # encoding: [0x89,0x07]27 ; RC1-NEXT: addw %cx, %ax # EVEX TO LEGACY Compression encoding: [0x66,0x01,0xc8]28 ; RC1-NEXT: retq # encoding: [0xc3]29 entry:30 %add = add nsw i32 %b, %a31 store i32 %add, ptr %p, align 432 %add1 = trunc i32 %add to i1633 %add2 = add i16 %add1, %x34 ret i16 %add235 }36 37 define signext i16 @no_partial_write(ptr %p, i32 %a, i32 %b, i16 signext %x, i16 signext %y) #0 {38 ; CHECK-LABEL: no_partial_write:39 ; CHECK: # %bb.0: # %entry40 ; CHECK-NEXT: addl %esi, %edx # EVEX TO LEGACY Compression encoding: [0x01,0xf2]41 ; CHECK-NEXT: movl %edx, (%rdi) # encoding: [0x89,0x17]42 ; CHECK-NEXT: addw %cx, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x01,0xca]43 ; CHECK-NEXT: retq # encoding: [0xc3]44 entry:45 %add = add nsw i32 %b, %a46 store i32 %add, ptr %p, align 447 %add1 = trunc i32 %add to i1648 %add2 = add i16 %add1, %x49 ret i16 %add250 }51 attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx16,+cx8,+egpr,+fxsr,+mmx,+ndd,+sse,+sse2,+x87" "tune-cpu"="generic" }52...53---54name: partial_write55tracksRegLiveness: true56noVRegs: true57noPhis: true58isSSA: false59body: |60 bb.0.entry:61 liveins: $ecx, $edx, $esi, $rdi62 renamable $eax = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags63 MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $eax :: (store (s32) into %ir.p)64 renamable $ax = ADD16rr_ND renamable $ax, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit $eax65 RET64 $ax66...67---68name: no_partial_write69tracksRegLiveness: true70noVRegs: true71noPhis: true72isSSA: false73body: |74 bb.0.entry:75 liveins: $ecx, $edx, $esi, $rdi76 77 renamable $edx = nsw ADD32rr_ND killed renamable $edx, killed renamable $esi, implicit-def dead $eflags78 MOV32mr killed renamable $rdi, 1, $noreg, 0, $noreg, renamable $edx :: (store (s32) into %ir.p)79 renamable $ax = ADD16rr_ND renamable $dx, renamable $cx, implicit-def dead $eflags, implicit killed $ecx, implicit killed $edx80 RET64 $ax81...82