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1; RUN: llc -mcpu=diamondrapids %s -mtriple=x86_64 -filetype=obj -o %t.o2; RUN: llvm-objdump --no-print-imm-hex -dr %t.o | FileCheck %s --check-prefixes=NOAPXREL,CHECK3 4; RUN: llc -mcpu=diamondrapids %s -mtriple=x86_64 -filetype=obj -o %t.o -x86-enable-apx-for-relocation=true5; RUN: llvm-objdump --no-print-imm-hex -dr %t.o | FileCheck %s --check-prefixes=APXREL,CHECK6 7 8; All tests are used to check no R_X86_64_CODE_4_GOTPCRELX relocation type9; emitted if APX features is disabled for relocation.10; The first 2 tests are used to check if the register class is not11; updated/recomputed by register allocator. It's originally updated to non-rex212; register class by "Suppress APX for relocation" pass.13 14 15; CHECK-LABEL: test_regclass_not_updated_by_regalloc_116; CHECK-NOT: R_X86_64_CODE_4_GOTPCRELX gvar-0x417; CHECK: movq (%rip), %rdi18; CHECK-NEXT: R_X86_64_REX_GOTPCRELX gvar-0x419 20@gvar = external global [20000 x i8]21 22define void @test_regclass_not_updated_by_regalloc_1(ptr %ptr1, ptr %0, i32 %int1, i64 %int_sext, i64 %mul.447, i64 %int_sext3, i32 %fetch.2508, i32 %fetch.2513, i32 %mul.442, i64 %int_sext6, i64 %int_sext7, i64 %int_sext8, i1 %cond1, i1 %cond2) {23alloca_38:24 %int_sext4 = sext i32 %int1 to i6425 tail call void @llvm.memset.p0.i64(ptr @gvar, i8 0, i64 20000, i1 false)26 %div.161 = sdiv i64 %int_sext3, %int_sext27 %cmp.2 = icmp sgt i64 %div.161, 028 %1 = sub i64 %int_sext7, %mul.44729 br label %loop.4130 31loop.41: ; preds = %ifmerge.2, %alloca_3832 br i1 %cmp.2, label %L.53, label %ifmerge.233 34L.53: ; preds = %loop.4135 %2 = getelementptr i8, ptr %ptr1, i64 %int_sext836 br label %loop.8337 38loop.83: ; preds = %loop.83, %L.5339 %i2.i64.1 = phi i64 [ 0, %L.53 ], [ %nextloop.83, %loop.83 ]40 %3 = mul i64 %i2.i64.1, %int_sext441 %.r275 = add i64 %3, %142 %4 = getelementptr float, ptr getelementptr ([20000 x i8], ptr @gvar, i64 0, i64 8000), i64 %.r27543 %gepload = load float, ptr %2, align 144 store float %gepload, ptr %4, align 445 %nextloop.83 = add i64 %i2.i64.1, 146 br i1 %cond1, label %ifmerge.2, label %loop.8347 48ifmerge.2: ; preds = %loop.83, %loop.4149 br i1 %cond2, label %afterloop.41, label %loop.4150 51afterloop.41: ; preds = %ifmerge.252 %mul.469 = mul i32 %mul.442, %fetch.250853 %div.172 = mul i32 %fetch.2513, %mul.46954 %mul.471 = mul i32 %int1, %div.17255 %int_sext39 = sext i32 %mul.471 to i6456 %5 = mul i64 %int_sext6, %int_sext3957 %6 = getelementptr i8, ptr %ptr1, i64 %558 %7 = load float, ptr %6, align 159 store float %7, ptr null, align 460 ret void61}62 63declare void @llvm.memset.p0.i64(ptr writeonly captures(none), i8, i64, i1 immarg)64 65; TODO: update after R_X86_64_CODE_6_GOTPCRELX is supported.66; CHECK-LABEL: test_regclass_not_updated_by_regalloc_267; APXREL: {nf} addq (%rip), %r16, %rcx68; APXREL-NEXT: R_X86_64_GOTPCREL gvar2-0x469; NOAPXREL-NOT: R_X86_64_CODE_4_GOTPCRELX gvar2-0x470; NOAPXREL: addq (%rip), %rbx71; NOAPXREL-NEXT: R_X86_64_REX_GOTPCRELX gvar2-0x472 73@gvar2 = external constant [8 x [8 x i32]]74 75define void @test_regclass_not_updated_by_regalloc_2(ptr %pSrc1, i32 %srcStep1, ptr %pSrc2, i32 %srcStep2, i32 %width, i32 %0, i1 %cmp71.not783, i1 %cmp11.i, ptr %pSrc2.addr.0535.i) {76entry:77 %1 = ashr i32 %srcStep2, 178 %conv.i = sext i32 %width to i6479 %conv6.i = and i32 %srcStep1, 180 %cmp.i = icmp sgt i32 %srcStep1, 081 %idx.ext.i = zext i32 %conv6.i to i6482 %2 = getelementptr <4 x i64>, ptr @gvar2, i64 %idx.ext.i83 %idx.ext183.i = sext i32 %1 to i6484 br i1 %cmp71.not783, label %for.end, label %for.body73.lr.ph85 86for.body73.lr.ph: ; preds = %entry87 %3 = load <4 x i64>, ptr %2, align 3288 %..i = select i1 %cmp11.i, <4 x i64> zeroinitializer, <4 x i64> splat (i64 1)89 %4 = bitcast <4 x i64> %..i to <8 x i32>90 %5 = bitcast <4 x i64> %3 to <8 x i32>91 %. = select i1 %cmp.i, <8 x i32> splat (i32 1), <8 x i32> %492 %.833 = select i1 %cmp.i, <8 x i32> %5, <8 x i32> zeroinitializer93 br i1 %cmp11.i, label %for.end.i, label %for.end94 95for.end.i: ; preds = %if.end153.i, %for.body73.lr.ph96 %pSrc2.addr.0535.i5 = phi ptr [ %add.ptr184.i, %if.end153.i ], [ %pSrc2, %for.body73.lr.ph ]97 %eSum0.0531.i = phi <4 x i64> [ %add.i452.i, %if.end153.i ], [ zeroinitializer, %for.body73.lr.ph ]98 br i1 %cmp71.not783, label %if.end153.i, label %if.then90.i99 100if.then90.i: ; preds = %for.end.i101 %6 = tail call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr null, <8 x i32> %.)102 %add.i464.i = or <4 x i64> %eSum0.0531.i, zeroinitializer103 %7 = bitcast <8 x i32> %.833 to <4 x i64>104 %add.ptr152.i = getelementptr i16, ptr %pSrc2.addr.0535.i5, i64 %conv.i105 br label %if.end153.i106 107if.end153.i: ; preds = %if.then90.i, %for.end.i108 %eSum0.2.i = phi <4 x i64> [ %7, %if.then90.i ], [ %eSum0.0531.i, %for.end.i ]109 %pLocSrc2.1.i = phi ptr [ %add.ptr152.i, %if.then90.i ], [ %pSrc1, %for.end.i ]110 %8 = load i16, ptr %pLocSrc2.1.i, align 2111 %conv165.i = zext i16 %8 to i32112 %vecinit3.i.i = insertelement <4 x i32> zeroinitializer, i32 %conv165.i, i64 0113 %9 = bitcast <4 x i32> %vecinit3.i.i to <2 x i64>114 %shuffle.i503.i = shufflevector <2 x i64> %9, <2 x i64> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>115 %add.i452.i = or <4 x i64> %eSum0.2.i, %shuffle.i503.i116 %add.ptr184.i = getelementptr i16, ptr %pSrc2.addr.0535.i, i64 %idx.ext183.i117 br label %for.end.i118 119for.end: ; preds = %for.body73.lr.ph, %entry120 br label %for.cond29.preheader.i227121 122for.cond29.preheader.i227: ; preds = %for.end123 br label %for.body32.i328124 125for.body32.i328: ; preds = %for.body32.i328, %for.cond29.preheader.i227126 %w.0524.i329 = phi i32 [ %sub.i381, %for.body32.i328 ], [ 0, %for.cond29.preheader.i227 ]127 %sub.i381 = or i32 %w.0524.i329, 0128 %cmp30.i384 = icmp sgt i32 %w.0524.i329, 0129 br label %for.body32.i328130}131 132declare <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr, <8 x i32>)133 134 135; The test is used to check MOV64rm instruction with relocation and ADD64rr_ND136; instruction are not folded to ADD64rm_ND with relocation. The later will emit137; APX relocation which is not recognized by the builtin linker on released OS.138 139; CHECK-LABEL: test_mem_fold140; NOAPXREL-NOT: R_X86_64_CODE_4_GOTPCRELX gvar3-0x4141; NOAPXREL: movq (%rip), %rbx142; NOAPXREL-NEXT: R_X86_64_REX_GOTPCRELX gvar3-0x4143 144@gvar3 = external global [40000 x i8]145 146define void @test_mem_fold(i32 %fetch.1644, i32 %sub.1142, i32 %mul.455, ptr %dval1, ptr %j1, ptr %j2, <4 x i1> %0, i1 %condloop.41.not, i32 %fetch.1646, i32 %fetch.1647, i32 %sub.1108, i64 %int_sext16, i64 %sub.1114, i1 %condloop.45.not.not, <4 x i1> %1) {147alloca_28:148 br label %ifmerge.52149 150do.body903: ; preds = %ifmerge.2151 %mul.453 = mul i32 %sub.1108, %fetch.1647152 %sub.1144.neg = or i32 %mul.455, %fetch.1646153 %mul.454.neg = mul i32 %sub.1144.neg, %fetch.1644154 %sub.1147 = sub i32 0, %sub.1142155 %int_sext36 = sext i32 %mul.453 to i64156 %int_sext38 = sext i32 %mul.454.neg to i64157 %add.974 = or i64 %int_sext36, %int_sext38158 %div.98 = sdiv i64 %add.974, %int_sext16159 br label %do.body907160 161do.body907: ; preds = %do.body907, %do.body903162 %do.count41.0 = phi i64 [ %sub.1173, %do.body907 ], [ %div.98, %do.body903 ]163 %gvar3.load = load double, ptr @gvar3, align 8164 store double %gvar3.load, ptr null, align 8165 call void (...) null(ptr null, ptr null, ptr null, ptr null, ptr %dval1, ptr null, ptr %j1, ptr %j2, ptr null, ptr null, ptr null, ptr null, ptr null, i64 0)166 store i32 %sub.1147, ptr null, align 4167 %sub.1173 = or i64 %do.count41.0, 1168 %rel.314 = icmp sgt i64 %do.count41.0, 0169 br label %do.body907170 171ifmerge.52: ; preds = %ifmerge.2, %alloca_28172 %i1.i64.012 = phi i64 [ 0, %alloca_28 ], [ %sub.1114, %ifmerge.2 ]173 %2 = getelementptr double, ptr @gvar3, i64 %i1.i64.012174 br label %loop.45175 176loop.45: ; preds = %loop.45, %ifmerge.52177 %3 = getelementptr double, ptr %2, <4 x i64> zeroinitializer178 %4 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %3, i32 0, <4 x i1> %0, <4 x double> zeroinitializer)179 call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %4, <4 x ptr> zeroinitializer, i32 0, <4 x i1> %0)180 br i1 %condloop.45.not.not, label %loop.45, label %ifmerge.2181 182ifmerge.2: ; preds = %loop.45183 br i1 %condloop.41.not, label %do.body903, label %ifmerge.52184}185 186declare <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, <4 x double>)187declare void @llvm.masked.scatter.v4f64.v4p0(<4 x double>, <4 x ptr>, i32 immarg, <4 x i1>)188 189 190; The test is to check no R_X86_64_CODE_4_GOTPCRELX relocation emitted when the191; register in operand 0 of instruction with relocation is used in the PHI192; instruction. In PHI elimination pass, PHI instruction is eliminated by193; inserting COPY instruction. And in the late pass (Machine Copy Propagation194; pass), the COPY instruction may be optimized and the register in operand 0 of195; instruction with relocation may be replaced with EGPR.196 197 198; CHECK-LABEL: test_phi_uses199; APXREL: addq (%rip), %r16200; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar4-0x4201; APXREL: movq (%rip), %r17202; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar5-0x4203; APXREL: movq (%rip), %r18204; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar6-0x4205; APXREL: movq (%rip), %r19206; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar7-0x4207; APXREL: movq (%rip), %r22208; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar8-0x4209; APXREL: movq (%rip), %r23210; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar9-0x4211; APXREL: movq (%rip), %r24212; APXREL-NEXT: R_X86_64_CODE_4_GOTPCRELX gvar10-0x4213; NOAPXREL-NOT: R_X86_64_CODE_4_GOTPCRELX gvar5-0x4214; NOAPXREL: movq (%rip), %r15215; NOAPXREL-NEXT: R_X86_64_REX_GOTPCRELX gvar5-0x4216 217 218@gvar4 = external global [33 x [33 x double]]219@gvar5 = external global [33 x [33 x float]]220@gvar6 = external global [33 x [33 x float]]221@gvar7 = external global [33 x [33 x float]]222@gvar8 = external global [33 x [33 x float]]223@gvar9 = external global [33 x [33 x float]]224@gvar10 = external global [33 x [33 x float]]225 226define void @test_phi_uses(i64 %i1.i64.0, ptr %0, ptr %1, ptr %2, ptr %3, ptr %in0, ptr %4, ptr %5, i1 %cmp.144) #0 {227alloca_15:228 br label %loop.253229 230loop.253: ; preds = %loop.1500, %alloca_15231 %i1.i64.01 = phi i64 [ 0, %alloca_15 ], [ %6, %loop.1500 ]232 %6 = add i64 %i1.i64.01, 1233 br label %loop.254234 235loop.254: ; preds = %loop.254, %loop.253236 %i2.i64.02 = phi i64 [ %13, %loop.254 ], [ 0, %loop.253 ]237 %7 = getelementptr [33 x [33 x float]], ptr @gvar10, i64 0, i64 %i2.i64.02, i64 %i1.i64.01238 %gepload368 = load float, ptr %7, align 4239 store double 0.000000e+00, ptr %0, align 8240 %8 = getelementptr [33 x [33 x float]], ptr @gvar9, i64 0, i64 %i2.i64.02, i64 %i1.i64.01241 %gepload369 = load float, ptr %8, align 4242 store double 0.000000e+00, ptr %1, align 8243 %9 = getelementptr [33 x [33 x float]], ptr @gvar8, i64 0, i64 %i2.i64.02, i64 %i1.i64.01244 %gepload371 = load float, ptr %9, align 4245 store double 0.000000e+00, ptr %2, align 8246 %10 = getelementptr [33 x [33 x float]], ptr @gvar7, i64 0, i64 %i2.i64.02, i64 %i1.i64.01247 %gepload373 = load float, ptr %10, align 4248 %11 = getelementptr [33 x [33 x double]], ptr @gvar4, i64 0, i64 %i2.i64.02, i64 %i1.i64.0249 store double 0.000000e+00, ptr %11, align 8250 %12 = getelementptr [33 x [33 x float]], ptr @gvar6, i64 0, i64 %i2.i64.02, i64 %i1.i64.01251 %gepload375 = load float, ptr %12, align 4252 store double 0.000000e+00, ptr %3, align 8253 store double 0.000000e+00, ptr %5, align 8254 %13 = add i64 %i2.i64.02, 1255 store double 0.000000e+00, ptr %in0, align 8256 store double 0.000000e+00, ptr %4, align 8257 %14 = getelementptr [33 x [33 x float]], ptr @gvar5, i64 0, i64 %i2.i64.02, i64 %i1.i64.01258 %gepload392 = load float, ptr %14, align 4259 br i1 %cmp.144, label %loop.1500, label %loop.254260 261loop.1500: ; preds = %loop.254262 %15 = getelementptr [33 x [33 x float]], ptr @gvar5, i64 0, i64 0, i64 %i1.i64.0263 %gepload444 = load float, ptr %15, align 4264 %16 = fpext float %gepload444 to double265 store double %16, ptr null, align 8266 br label %loop.253267}