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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,CHECK-O3,CHECK-SSE-O33; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,CHECK-O3,CHECK-SSE-O34; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,CHECK-O3,CHECK-AVX-O3,CHECK-AVX2-O35; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-O3,CHECK-AVX-O3,CHECK-AVX512-O36; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -O0 -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,CHECK-O0,CHECK-SSE-O07; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -O0 -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,CHECK-O0,CHECK-SSE-O08; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -O0 -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,CHECK-O0,CHECK-AVX-O0,CHECK-AVX2-O09; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs -O0 -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-O0,CHECK-AVX-O0,CHECK-AVX512-O010 11define void @test1(ptr %ptr, i32 %val1) {12; CHECK-LABEL: test1:13; CHECK: # %bb.0:14; CHECK-NEXT: xchgl %esi, (%rdi)15; CHECK-NEXT: retq16 store atomic i32 %val1, ptr %ptr seq_cst, align 417 ret void18}19 20define void @test2(ptr %ptr, i32 %val1) {21; CHECK-LABEL: test2:22; CHECK: # %bb.0:23; CHECK-NEXT: movl %esi, (%rdi)24; CHECK-NEXT: retq25 store atomic i32 %val1, ptr %ptr release, align 426 ret void27}28 29define i32 @test3(ptr %ptr) {30; CHECK-LABEL: test3:31; CHECK: # %bb.0:32; CHECK-NEXT: movl (%rdi), %eax33; CHECK-NEXT: retq34 %val = load atomic i32, ptr %ptr seq_cst, align 435 ret i32 %val36}37 38define <1 x i32> @atomic_vec1_i32(ptr %x) {39; CHECK-LABEL: atomic_vec1_i32:40; CHECK: # %bb.0:41; CHECK-NEXT: movl (%rdi), %eax42; CHECK-NEXT: retq43 %ret = load atomic <1 x i32>, ptr %x acquire, align 444 ret <1 x i32> %ret45}46 47define <1 x i8> @atomic_vec1_i8(ptr %x) {48; CHECK-O3-LABEL: atomic_vec1_i8:49; CHECK-O3: # %bb.0:50; CHECK-O3-NEXT: movzbl (%rdi), %eax51; CHECK-O3-NEXT: retq52;53; CHECK-O0-LABEL: atomic_vec1_i8:54; CHECK-O0: # %bb.0:55; CHECK-O0-NEXT: movb (%rdi), %al56; CHECK-O0-NEXT: retq57 %ret = load atomic <1 x i8>, ptr %x acquire, align 158 ret <1 x i8> %ret59}60 61define <1 x i16> @atomic_vec1_i16(ptr %x) {62; CHECK-O3-LABEL: atomic_vec1_i16:63; CHECK-O3: # %bb.0:64; CHECK-O3-NEXT: movzwl (%rdi), %eax65; CHECK-O3-NEXT: retq66;67; CHECK-O0-LABEL: atomic_vec1_i16:68; CHECK-O0: # %bb.0:69; CHECK-O0-NEXT: movw (%rdi), %ax70; CHECK-O0-NEXT: retq71 %ret = load atomic <1 x i16>, ptr %x acquire, align 272 ret <1 x i16> %ret73}74 75define <1 x i32> @atomic_vec1_i8_zext(ptr %x) {76; CHECK-O3-LABEL: atomic_vec1_i8_zext:77; CHECK-O3: # %bb.0:78; CHECK-O3-NEXT: movzbl (%rdi), %eax79; CHECK-O3-NEXT: movzbl %al, %eax80; CHECK-O3-NEXT: retq81;82; CHECK-O0-LABEL: atomic_vec1_i8_zext:83; CHECK-O0: # %bb.0:84; CHECK-O0-NEXT: movb (%rdi), %al85; CHECK-O0-NEXT: movzbl %al, %eax86; CHECK-O0-NEXT: retq87 %ret = load atomic <1 x i8>, ptr %x acquire, align 188 %zret = zext <1 x i8> %ret to <1 x i32>89 ret <1 x i32> %zret90}91 92define <1 x i64> @atomic_vec1_i16_sext(ptr %x) {93; CHECK-O3-LABEL: atomic_vec1_i16_sext:94; CHECK-O3: # %bb.0:95; CHECK-O3-NEXT: movzwl (%rdi), %eax96; CHECK-O3-NEXT: movswq %ax, %rax97; CHECK-O3-NEXT: retq98;99; CHECK-O0-LABEL: atomic_vec1_i16_sext:100; CHECK-O0: # %bb.0:101; CHECK-O0-NEXT: movw (%rdi), %ax102; CHECK-O0-NEXT: movswq %ax, %rax103; CHECK-O0-NEXT: retq104 %ret = load atomic <1 x i16>, ptr %x acquire, align 2105 %sret = sext <1 x i16> %ret to <1 x i64>106 ret <1 x i64> %sret107}108 109define <1 x ptr addrspace(270)> @atomic_vec1_ptr270(ptr %x) {110; CHECK-LABEL: atomic_vec1_ptr270:111; CHECK: # %bb.0:112; CHECK-NEXT: movl (%rdi), %eax113; CHECK-NEXT: retq114 %ret = load atomic <1 x ptr addrspace(270)>, ptr %x acquire, align 4115 ret <1 x ptr addrspace(270)> %ret116}117 118define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {119; CHECK-SSE-O3-LABEL: atomic_vec1_bfloat:120; CHECK-SSE-O3: # %bb.0:121; CHECK-SSE-O3-NEXT: movzwl (%rdi), %eax122; CHECK-SSE-O3-NEXT: pinsrw $0, %eax, %xmm0123; CHECK-SSE-O3-NEXT: retq124;125; CHECK-AVX-O3-LABEL: atomic_vec1_bfloat:126; CHECK-AVX-O3: # %bb.0:127; CHECK-AVX-O3-NEXT: movzwl (%rdi), %eax128; CHECK-AVX-O3-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0129; CHECK-AVX-O3-NEXT: retq130;131; CHECK-SSE-O0-LABEL: atomic_vec1_bfloat:132; CHECK-SSE-O0: # %bb.0:133; CHECK-SSE-O0-NEXT: movw (%rdi), %cx134; CHECK-SSE-O0-NEXT: # implicit-def: $eax135; CHECK-SSE-O0-NEXT: movw %cx, %ax136; CHECK-SSE-O0-NEXT: # implicit-def: $xmm0137; CHECK-SSE-O0-NEXT: pinsrw $0, %eax, %xmm0138; CHECK-SSE-O0-NEXT: retq139;140; CHECK-AVX-O0-LABEL: atomic_vec1_bfloat:141; CHECK-AVX-O0: # %bb.0:142; CHECK-AVX-O0-NEXT: movw (%rdi), %cx143; CHECK-AVX-O0-NEXT: # implicit-def: $eax144; CHECK-AVX-O0-NEXT: movw %cx, %ax145; CHECK-AVX-O0-NEXT: # implicit-def: $xmm0146; CHECK-AVX-O0-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0147; CHECK-AVX-O0-NEXT: retq148 %ret = load atomic <1 x bfloat>, ptr %x acquire, align 2149 ret <1 x bfloat> %ret150}151 152define <1 x ptr> @atomic_vec1_ptr_align(ptr %x) nounwind {153; CHECK-LABEL: atomic_vec1_ptr_align:154; CHECK: # %bb.0:155; CHECK-NEXT: movq (%rdi), %rax156; CHECK-NEXT: retq157 %ret = load atomic <1 x ptr>, ptr %x acquire, align 8158 ret <1 x ptr> %ret159}160 161define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {162; CHECK-LABEL: atomic_vec1_i64_align:163; CHECK: # %bb.0:164; CHECK-NEXT: movq (%rdi), %rax165; CHECK-NEXT: retq166 %ret = load atomic <1 x i64>, ptr %x acquire, align 8167 ret <1 x i64> %ret168}169 170define <1 x ptr> @atomic_vec1_ptr(ptr %x) nounwind {171; CHECK-O3-LABEL: atomic_vec1_ptr:172; CHECK-O3: # %bb.0:173; CHECK-O3-NEXT: pushq %rax174; CHECK-O3-NEXT: movq %rdi, %rsi175; CHECK-O3-NEXT: movq %rsp, %rdx176; CHECK-O3-NEXT: movl $8, %edi177; CHECK-O3-NEXT: movl $2, %ecx178; CHECK-O3-NEXT: callq __atomic_load@PLT179; CHECK-O3-NEXT: movq (%rsp), %rax180; CHECK-O3-NEXT: popq %rcx181; CHECK-O3-NEXT: retq182;183; CHECK-O0-LABEL: atomic_vec1_ptr:184; CHECK-O0: # %bb.0:185; CHECK-O0-NEXT: pushq %rax186; CHECK-O0-NEXT: movq %rdi, %rsi187; CHECK-O0-NEXT: movl $8, %edi188; CHECK-O0-NEXT: movq %rsp, %rdx189; CHECK-O0-NEXT: movl $2, %ecx190; CHECK-O0-NEXT: callq __atomic_load@PLT191; CHECK-O0-NEXT: movq (%rsp), %rax192; CHECK-O0-NEXT: popq %rcx193; CHECK-O0-NEXT: retq194 %ret = load atomic <1 x ptr>, ptr %x acquire, align 4195 ret <1 x ptr> %ret196}197 198define <1 x half> @atomic_vec1_half(ptr %x) {199; CHECK-SSE-O3-LABEL: atomic_vec1_half:200; CHECK-SSE-O3: # %bb.0:201; CHECK-SSE-O3-NEXT: movzwl (%rdi), %eax202; CHECK-SSE-O3-NEXT: pinsrw $0, %eax, %xmm0203; CHECK-SSE-O3-NEXT: retq204;205; CHECK-AVX-O3-LABEL: atomic_vec1_half:206; CHECK-AVX-O3: # %bb.0:207; CHECK-AVX-O3-NEXT: movzwl (%rdi), %eax208; CHECK-AVX-O3-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0209; CHECK-AVX-O3-NEXT: retq210;211; CHECK-SSE-O0-LABEL: atomic_vec1_half:212; CHECK-SSE-O0: # %bb.0:213; CHECK-SSE-O0-NEXT: movw (%rdi), %cx214; CHECK-SSE-O0-NEXT: # implicit-def: $eax215; CHECK-SSE-O0-NEXT: movw %cx, %ax216; CHECK-SSE-O0-NEXT: # implicit-def: $xmm0217; CHECK-SSE-O0-NEXT: pinsrw $0, %eax, %xmm0218; CHECK-SSE-O0-NEXT: retq219;220; CHECK-AVX-O0-LABEL: atomic_vec1_half:221; CHECK-AVX-O0: # %bb.0:222; CHECK-AVX-O0-NEXT: movw (%rdi), %cx223; CHECK-AVX-O0-NEXT: # implicit-def: $eax224; CHECK-AVX-O0-NEXT: movw %cx, %ax225; CHECK-AVX-O0-NEXT: # implicit-def: $xmm0226; CHECK-AVX-O0-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0227; CHECK-AVX-O0-NEXT: retq228 %ret = load atomic <1 x half>, ptr %x acquire, align 2229 ret <1 x half> %ret230}231 232define <1 x float> @atomic_vec1_float(ptr %x) {233; CHECK-SSE-O3-LABEL: atomic_vec1_float:234; CHECK-SSE-O3: # %bb.0:235; CHECK-SSE-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero236; CHECK-SSE-O3-NEXT: retq237;238; CHECK-AVX-O3-LABEL: atomic_vec1_float:239; CHECK-AVX-O3: # %bb.0:240; CHECK-AVX-O3-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero241; CHECK-AVX-O3-NEXT: retq242;243; CHECK-SSE-O0-LABEL: atomic_vec1_float:244; CHECK-SSE-O0: # %bb.0:245; CHECK-SSE-O0-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero246; CHECK-SSE-O0-NEXT: retq247;248; CHECK-AVX-O0-LABEL: atomic_vec1_float:249; CHECK-AVX-O0: # %bb.0:250; CHECK-AVX-O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero251; CHECK-AVX-O0-NEXT: retq252 %ret = load atomic <1 x float>, ptr %x acquire, align 4253 ret <1 x float> %ret254}255 256define <1 x double> @atomic_vec1_double_align(ptr %x) nounwind {257; CHECK-SSE-O3-LABEL: atomic_vec1_double_align:258; CHECK-SSE-O3: # %bb.0:259; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero260; CHECK-SSE-O3-NEXT: retq261;262; CHECK-AVX-O3-LABEL: atomic_vec1_double_align:263; CHECK-AVX-O3: # %bb.0:264; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero265; CHECK-AVX-O3-NEXT: retq266;267; CHECK-SSE-O0-LABEL: atomic_vec1_double_align:268; CHECK-SSE-O0: # %bb.0:269; CHECK-SSE-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero270; CHECK-SSE-O0-NEXT: retq271;272; CHECK-AVX-O0-LABEL: atomic_vec1_double_align:273; CHECK-AVX-O0: # %bb.0:274; CHECK-AVX-O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero275; CHECK-AVX-O0-NEXT: retq276 %ret = load atomic <1 x double>, ptr %x acquire, align 8277 ret <1 x double> %ret278}279 280define <1 x i64> @atomic_vec1_i64(ptr %x) nounwind {281; CHECK-O3-LABEL: atomic_vec1_i64:282; CHECK-O3: # %bb.0:283; CHECK-O3-NEXT: pushq %rax284; CHECK-O3-NEXT: movq %rdi, %rsi285; CHECK-O3-NEXT: movq %rsp, %rdx286; CHECK-O3-NEXT: movl $8, %edi287; CHECK-O3-NEXT: movl $2, %ecx288; CHECK-O3-NEXT: callq __atomic_load@PLT289; CHECK-O3-NEXT: movq (%rsp), %rax290; CHECK-O3-NEXT: popq %rcx291; CHECK-O3-NEXT: retq292;293; CHECK-O0-LABEL: atomic_vec1_i64:294; CHECK-O0: # %bb.0:295; CHECK-O0-NEXT: pushq %rax296; CHECK-O0-NEXT: movq %rdi, %rsi297; CHECK-O0-NEXT: movl $8, %edi298; CHECK-O0-NEXT: movq %rsp, %rdx299; CHECK-O0-NEXT: movl $2, %ecx300; CHECK-O0-NEXT: callq __atomic_load@PLT301; CHECK-O0-NEXT: movq (%rsp), %rax302; CHECK-O0-NEXT: popq %rcx303; CHECK-O0-NEXT: retq304 %ret = load atomic <1 x i64>, ptr %x acquire, align 4305 ret <1 x i64> %ret306}307 308define <1 x double> @atomic_vec1_double(ptr %x) nounwind {309; CHECK-SSE-O3-LABEL: atomic_vec1_double:310; CHECK-SSE-O3: # %bb.0:311; CHECK-SSE-O3-NEXT: pushq %rax312; CHECK-SSE-O3-NEXT: movq %rdi, %rsi313; CHECK-SSE-O3-NEXT: movq %rsp, %rdx314; CHECK-SSE-O3-NEXT: movl $8, %edi315; CHECK-SSE-O3-NEXT: movl $2, %ecx316; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT317; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero318; CHECK-SSE-O3-NEXT: popq %rax319; CHECK-SSE-O3-NEXT: retq320;321; CHECK-AVX-O3-LABEL: atomic_vec1_double:322; CHECK-AVX-O3: # %bb.0:323; CHECK-AVX-O3-NEXT: pushq %rax324; CHECK-AVX-O3-NEXT: movq %rdi, %rsi325; CHECK-AVX-O3-NEXT: movq %rsp, %rdx326; CHECK-AVX-O3-NEXT: movl $8, %edi327; CHECK-AVX-O3-NEXT: movl $2, %ecx328; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT329; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero330; CHECK-AVX-O3-NEXT: popq %rax331; CHECK-AVX-O3-NEXT: retq332;333; CHECK-SSE-O0-LABEL: atomic_vec1_double:334; CHECK-SSE-O0: # %bb.0:335; CHECK-SSE-O0-NEXT: pushq %rax336; CHECK-SSE-O0-NEXT: movq %rdi, %rsi337; CHECK-SSE-O0-NEXT: movl $8, %edi338; CHECK-SSE-O0-NEXT: movq %rsp, %rdx339; CHECK-SSE-O0-NEXT: movl $2, %ecx340; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT341; CHECK-SSE-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero342; CHECK-SSE-O0-NEXT: popq %rax343; CHECK-SSE-O0-NEXT: retq344;345; CHECK-AVX-O0-LABEL: atomic_vec1_double:346; CHECK-AVX-O0: # %bb.0:347; CHECK-AVX-O0-NEXT: pushq %rax348; CHECK-AVX-O0-NEXT: movq %rdi, %rsi349; CHECK-AVX-O0-NEXT: movl $8, %edi350; CHECK-AVX-O0-NEXT: movq %rsp, %rdx351; CHECK-AVX-O0-NEXT: movl $2, %ecx352; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT353; CHECK-AVX-O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero354; CHECK-AVX-O0-NEXT: popq %rax355; CHECK-AVX-O0-NEXT: retq356 %ret = load atomic <1 x double>, ptr %x acquire, align 4357 ret <1 x double> %ret358}359 360define <2 x i32> @atomic_vec2_i32(ptr %x) nounwind {361; CHECK-SSE-O3-LABEL: atomic_vec2_i32:362; CHECK-SSE-O3: # %bb.0:363; CHECK-SSE-O3-NEXT: pushq %rax364; CHECK-SSE-O3-NEXT: movq %rdi, %rsi365; CHECK-SSE-O3-NEXT: movq %rsp, %rdx366; CHECK-SSE-O3-NEXT: movl $8, %edi367; CHECK-SSE-O3-NEXT: movl $2, %ecx368; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT369; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero370; CHECK-SSE-O3-NEXT: popq %rax371; CHECK-SSE-O3-NEXT: retq372;373; CHECK-AVX-O3-LABEL: atomic_vec2_i32:374; CHECK-AVX-O3: # %bb.0:375; CHECK-AVX-O3-NEXT: pushq %rax376; CHECK-AVX-O3-NEXT: movq %rdi, %rsi377; CHECK-AVX-O3-NEXT: movq %rsp, %rdx378; CHECK-AVX-O3-NEXT: movl $8, %edi379; CHECK-AVX-O3-NEXT: movl $2, %ecx380; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT381; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero382; CHECK-AVX-O3-NEXT: popq %rax383; CHECK-AVX-O3-NEXT: retq384;385; CHECK-SSE-O0-LABEL: atomic_vec2_i32:386; CHECK-SSE-O0: # %bb.0:387; CHECK-SSE-O0-NEXT: pushq %rax388; CHECK-SSE-O0-NEXT: movq %rdi, %rsi389; CHECK-SSE-O0-NEXT: movl $8, %edi390; CHECK-SSE-O0-NEXT: movq %rsp, %rdx391; CHECK-SSE-O0-NEXT: movl $2, %ecx392; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT393; CHECK-SSE-O0-NEXT: movq {{.*#+}} xmm0 = mem[0],zero394; CHECK-SSE-O0-NEXT: popq %rax395; CHECK-SSE-O0-NEXT: retq396;397; CHECK-AVX-O0-LABEL: atomic_vec2_i32:398; CHECK-AVX-O0: # %bb.0:399; CHECK-AVX-O0-NEXT: pushq %rax400; CHECK-AVX-O0-NEXT: movq %rdi, %rsi401; CHECK-AVX-O0-NEXT: movl $8, %edi402; CHECK-AVX-O0-NEXT: movq %rsp, %rdx403; CHECK-AVX-O0-NEXT: movl $2, %ecx404; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT405; CHECK-AVX-O0-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero406; CHECK-AVX-O0-NEXT: popq %rax407; CHECK-AVX-O0-NEXT: retq408 %ret = load atomic <2 x i32>, ptr %x acquire, align 4409 ret <2 x i32> %ret410}411 412define <4 x float> @atomic_vec4_float(ptr %x) nounwind {413; CHECK-SSE-O3-LABEL: atomic_vec4_float:414; CHECK-SSE-O3: # %bb.0:415; CHECK-SSE-O3-NEXT: subq $24, %rsp416; CHECK-SSE-O3-NEXT: movq %rdi, %rsi417; CHECK-SSE-O3-NEXT: movq %rsp, %rdx418; CHECK-SSE-O3-NEXT: movl $16, %edi419; CHECK-SSE-O3-NEXT: movl $2, %ecx420; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT421; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0422; CHECK-SSE-O3-NEXT: addq $24, %rsp423; CHECK-SSE-O3-NEXT: retq424;425; CHECK-AVX-O3-LABEL: atomic_vec4_float:426; CHECK-AVX-O3: # %bb.0:427; CHECK-AVX-O3-NEXT: subq $24, %rsp428; CHECK-AVX-O3-NEXT: movq %rdi, %rsi429; CHECK-AVX-O3-NEXT: movq %rsp, %rdx430; CHECK-AVX-O3-NEXT: movl $16, %edi431; CHECK-AVX-O3-NEXT: movl $2, %ecx432; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT433; CHECK-AVX-O3-NEXT: vmovaps (%rsp), %xmm0434; CHECK-AVX-O3-NEXT: addq $24, %rsp435; CHECK-AVX-O3-NEXT: retq436;437; CHECK-SSE-O0-LABEL: atomic_vec4_float:438; CHECK-SSE-O0: # %bb.0:439; CHECK-SSE-O0-NEXT: subq $24, %rsp440; CHECK-SSE-O0-NEXT: movq %rdi, %rsi441; CHECK-SSE-O0-NEXT: movl $16, %edi442; CHECK-SSE-O0-NEXT: movq %rsp, %rdx443; CHECK-SSE-O0-NEXT: movl $2, %ecx444; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT445; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0446; CHECK-SSE-O0-NEXT: addq $24, %rsp447; CHECK-SSE-O0-NEXT: retq448;449; CHECK-AVX-O0-LABEL: atomic_vec4_float:450; CHECK-AVX-O0: # %bb.0:451; CHECK-AVX-O0-NEXT: subq $24, %rsp452; CHECK-AVX-O0-NEXT: movq %rdi, %rsi453; CHECK-AVX-O0-NEXT: movl $16, %edi454; CHECK-AVX-O0-NEXT: movq %rsp, %rdx455; CHECK-AVX-O0-NEXT: movl $2, %ecx456; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT457; CHECK-AVX-O0-NEXT: vmovaps (%rsp), %xmm0458; CHECK-AVX-O0-NEXT: addq $24, %rsp459; CHECK-AVX-O0-NEXT: retq460 %ret = load atomic <4 x float>, ptr %x acquire, align 4461 ret <4 x float> %ret462}463 464define <8 x double> @atomic_vec8_double(ptr %x) nounwind {465; CHECK-SSE-O3-LABEL: atomic_vec8_double:466; CHECK-SSE-O3: # %bb.0:467; CHECK-SSE-O3-NEXT: subq $72, %rsp468; CHECK-SSE-O3-NEXT: movq %rdi, %rsi469; CHECK-SSE-O3-NEXT: movq %rsp, %rdx470; CHECK-SSE-O3-NEXT: movl $64, %edi471; CHECK-SSE-O3-NEXT: movl $2, %ecx472; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT473; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0474; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1475; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2476; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3477; CHECK-SSE-O3-NEXT: addq $72, %rsp478; CHECK-SSE-O3-NEXT: retq479;480; CHECK-AVX2-O3-LABEL: atomic_vec8_double:481; CHECK-AVX2-O3: # %bb.0:482; CHECK-AVX2-O3-NEXT: subq $72, %rsp483; CHECK-AVX2-O3-NEXT: movq %rdi, %rsi484; CHECK-AVX2-O3-NEXT: movq %rsp, %rdx485; CHECK-AVX2-O3-NEXT: movl $64, %edi486; CHECK-AVX2-O3-NEXT: movl $2, %ecx487; CHECK-AVX2-O3-NEXT: callq __atomic_load@PLT488; CHECK-AVX2-O3-NEXT: vmovups (%rsp), %ymm0489; CHECK-AVX2-O3-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1490; CHECK-AVX2-O3-NEXT: addq $72, %rsp491; CHECK-AVX2-O3-NEXT: retq492;493; CHECK-AVX512-O3-LABEL: atomic_vec8_double:494; CHECK-AVX512-O3: # %bb.0:495; CHECK-AVX512-O3-NEXT: subq $72, %rsp496; CHECK-AVX512-O3-NEXT: movq %rdi, %rsi497; CHECK-AVX512-O3-NEXT: movq %rsp, %rdx498; CHECK-AVX512-O3-NEXT: movl $64, %edi499; CHECK-AVX512-O3-NEXT: movl $2, %ecx500; CHECK-AVX512-O3-NEXT: callq __atomic_load@PLT501; CHECK-AVX512-O3-NEXT: vmovups (%rsp), %zmm0502; CHECK-AVX512-O3-NEXT: addq $72, %rsp503; CHECK-AVX512-O3-NEXT: retq504;505; CHECK-SSE-O0-LABEL: atomic_vec8_double:506; CHECK-SSE-O0: # %bb.0:507; CHECK-SSE-O0-NEXT: subq $72, %rsp508; CHECK-SSE-O0-NEXT: movq %rdi, %rsi509; CHECK-SSE-O0-NEXT: movl $64, %edi510; CHECK-SSE-O0-NEXT: movq %rsp, %rdx511; CHECK-SSE-O0-NEXT: movl $2, %ecx512; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT513; CHECK-SSE-O0-NEXT: movapd (%rsp), %xmm0514; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm1515; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm2516; CHECK-SSE-O0-NEXT: movapd {{[0-9]+}}(%rsp), %xmm3517; CHECK-SSE-O0-NEXT: addq $72, %rsp518; CHECK-SSE-O0-NEXT: retq519;520; CHECK-AVX2-O0-LABEL: atomic_vec8_double:521; CHECK-AVX2-O0: # %bb.0:522; CHECK-AVX2-O0-NEXT: subq $72, %rsp523; CHECK-AVX2-O0-NEXT: movq %rdi, %rsi524; CHECK-AVX2-O0-NEXT: movl $64, %edi525; CHECK-AVX2-O0-NEXT: movq %rsp, %rdx526; CHECK-AVX2-O0-NEXT: movl $2, %ecx527; CHECK-AVX2-O0-NEXT: callq __atomic_load@PLT528; CHECK-AVX2-O0-NEXT: vmovupd (%rsp), %ymm0529; CHECK-AVX2-O0-NEXT: vmovupd {{[0-9]+}}(%rsp), %ymm1530; CHECK-AVX2-O0-NEXT: addq $72, %rsp531; CHECK-AVX2-O0-NEXT: retq532;533; CHECK-AVX512-O0-LABEL: atomic_vec8_double:534; CHECK-AVX512-O0: # %bb.0:535; CHECK-AVX512-O0-NEXT: subq $72, %rsp536; CHECK-AVX512-O0-NEXT: movq %rdi, %rsi537; CHECK-AVX512-O0-NEXT: movl $64, %edi538; CHECK-AVX512-O0-NEXT: movq %rsp, %rdx539; CHECK-AVX512-O0-NEXT: movl $2, %ecx540; CHECK-AVX512-O0-NEXT: callq __atomic_load@PLT541; CHECK-AVX512-O0-NEXT: vmovupd (%rsp), %zmm0542; CHECK-AVX512-O0-NEXT: addq $72, %rsp543; CHECK-AVX512-O0-NEXT: retq544 %ret = load atomic <8 x double>, ptr %x acquire, align 4545 ret <8 x double> %ret546}547 548define <16 x bfloat> @atomic_vec16_bfloat(ptr %x) nounwind {549; CHECK-SSE-O3-LABEL: atomic_vec16_bfloat:550; CHECK-SSE-O3: # %bb.0:551; CHECK-SSE-O3-NEXT: subq $40, %rsp552; CHECK-SSE-O3-NEXT: movq %rdi, %rsi553; CHECK-SSE-O3-NEXT: movq %rsp, %rdx554; CHECK-SSE-O3-NEXT: movl $32, %edi555; CHECK-SSE-O3-NEXT: movl $2, %ecx556; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT557; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0558; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1559; CHECK-SSE-O3-NEXT: addq $40, %rsp560; CHECK-SSE-O3-NEXT: retq561;562; CHECK-AVX-O3-LABEL: atomic_vec16_bfloat:563; CHECK-AVX-O3: # %bb.0:564; CHECK-AVX-O3-NEXT: subq $40, %rsp565; CHECK-AVX-O3-NEXT: movq %rdi, %rsi566; CHECK-AVX-O3-NEXT: movq %rsp, %rdx567; CHECK-AVX-O3-NEXT: movl $32, %edi568; CHECK-AVX-O3-NEXT: movl $2, %ecx569; CHECK-AVX-O3-NEXT: callq __atomic_load@PLT570; CHECK-AVX-O3-NEXT: vmovups (%rsp), %ymm0571; CHECK-AVX-O3-NEXT: addq $40, %rsp572; CHECK-AVX-O3-NEXT: retq573;574; CHECK-SSE-O0-LABEL: atomic_vec16_bfloat:575; CHECK-SSE-O0: # %bb.0:576; CHECK-SSE-O0-NEXT: subq $40, %rsp577; CHECK-SSE-O0-NEXT: movq %rdi, %rsi578; CHECK-SSE-O0-NEXT: movl $32, %edi579; CHECK-SSE-O0-NEXT: movq %rsp, %rdx580; CHECK-SSE-O0-NEXT: movl $2, %ecx581; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT582; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0583; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1584; CHECK-SSE-O0-NEXT: addq $40, %rsp585; CHECK-SSE-O0-NEXT: retq586;587; CHECK-AVX-O0-LABEL: atomic_vec16_bfloat:588; CHECK-AVX-O0: # %bb.0:589; CHECK-AVX-O0-NEXT: subq $40, %rsp590; CHECK-AVX-O0-NEXT: movq %rdi, %rsi591; CHECK-AVX-O0-NEXT: movl $32, %edi592; CHECK-AVX-O0-NEXT: movq %rsp, %rdx593; CHECK-AVX-O0-NEXT: movl $2, %ecx594; CHECK-AVX-O0-NEXT: callq __atomic_load@PLT595; CHECK-AVX-O0-NEXT: vmovups (%rsp), %ymm0596; CHECK-AVX-O0-NEXT: addq $40, %rsp597; CHECK-AVX-O0-NEXT: retq598 %ret = load atomic <16 x bfloat>, ptr %x acquire, align 4599 ret <16 x bfloat> %ret600}601 602define <32 x half> @atomic_vec32_half(ptr %x) nounwind {603; CHECK-SSE-O3-LABEL: atomic_vec32_half:604; CHECK-SSE-O3: # %bb.0:605; CHECK-SSE-O3-NEXT: subq $72, %rsp606; CHECK-SSE-O3-NEXT: movq %rdi, %rsi607; CHECK-SSE-O3-NEXT: movq %rsp, %rdx608; CHECK-SSE-O3-NEXT: movl $64, %edi609; CHECK-SSE-O3-NEXT: movl $2, %ecx610; CHECK-SSE-O3-NEXT: callq __atomic_load@PLT611; CHECK-SSE-O3-NEXT: movaps (%rsp), %xmm0612; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1613; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2614; CHECK-SSE-O3-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3615; CHECK-SSE-O3-NEXT: addq $72, %rsp616; CHECK-SSE-O3-NEXT: retq617;618; CHECK-AVX2-O3-LABEL: atomic_vec32_half:619; CHECK-AVX2-O3: # %bb.0:620; CHECK-AVX2-O3-NEXT: subq $72, %rsp621; CHECK-AVX2-O3-NEXT: movq %rdi, %rsi622; CHECK-AVX2-O3-NEXT: movq %rsp, %rdx623; CHECK-AVX2-O3-NEXT: movl $64, %edi624; CHECK-AVX2-O3-NEXT: movl $2, %ecx625; CHECK-AVX2-O3-NEXT: callq __atomic_load@PLT626; CHECK-AVX2-O3-NEXT: vmovups (%rsp), %ymm0627; CHECK-AVX2-O3-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1628; CHECK-AVX2-O3-NEXT: addq $72, %rsp629; CHECK-AVX2-O3-NEXT: retq630;631; CHECK-AVX512-O3-LABEL: atomic_vec32_half:632; CHECK-AVX512-O3: # %bb.0:633; CHECK-AVX512-O3-NEXT: subq $72, %rsp634; CHECK-AVX512-O3-NEXT: movq %rdi, %rsi635; CHECK-AVX512-O3-NEXT: movq %rsp, %rdx636; CHECK-AVX512-O3-NEXT: movl $64, %edi637; CHECK-AVX512-O3-NEXT: movl $2, %ecx638; CHECK-AVX512-O3-NEXT: callq __atomic_load@PLT639; CHECK-AVX512-O3-NEXT: vmovups (%rsp), %zmm0640; CHECK-AVX512-O3-NEXT: addq $72, %rsp641; CHECK-AVX512-O3-NEXT: retq642;643; CHECK-SSE-O0-LABEL: atomic_vec32_half:644; CHECK-SSE-O0: # %bb.0:645; CHECK-SSE-O0-NEXT: subq $72, %rsp646; CHECK-SSE-O0-NEXT: movq %rdi, %rsi647; CHECK-SSE-O0-NEXT: movl $64, %edi648; CHECK-SSE-O0-NEXT: movq %rsp, %rdx649; CHECK-SSE-O0-NEXT: movl $2, %ecx650; CHECK-SSE-O0-NEXT: callq __atomic_load@PLT651; CHECK-SSE-O0-NEXT: movaps (%rsp), %xmm0652; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1653; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2654; CHECK-SSE-O0-NEXT: movaps {{[0-9]+}}(%rsp), %xmm3655; CHECK-SSE-O0-NEXT: addq $72, %rsp656; CHECK-SSE-O0-NEXT: retq657;658; CHECK-AVX2-O0-LABEL: atomic_vec32_half:659; CHECK-AVX2-O0: # %bb.0:660; CHECK-AVX2-O0-NEXT: subq $72, %rsp661; CHECK-AVX2-O0-NEXT: movq %rdi, %rsi662; CHECK-AVX2-O0-NEXT: movl $64, %edi663; CHECK-AVX2-O0-NEXT: movq %rsp, %rdx664; CHECK-AVX2-O0-NEXT: movl $2, %ecx665; CHECK-AVX2-O0-NEXT: callq __atomic_load@PLT666; CHECK-AVX2-O0-NEXT: vmovups (%rsp), %ymm0667; CHECK-AVX2-O0-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm1668; CHECK-AVX2-O0-NEXT: addq $72, %rsp669; CHECK-AVX2-O0-NEXT: retq670;671; CHECK-AVX512-O0-LABEL: atomic_vec32_half:672; CHECK-AVX512-O0: # %bb.0:673; CHECK-AVX512-O0-NEXT: subq $72, %rsp674; CHECK-AVX512-O0-NEXT: movq %rdi, %rsi675; CHECK-AVX512-O0-NEXT: movl $64, %edi676; CHECK-AVX512-O0-NEXT: movq %rsp, %rdx677; CHECK-AVX512-O0-NEXT: movl $2, %ecx678; CHECK-AVX512-O0-NEXT: callq __atomic_load@PLT679; CHECK-AVX512-O0-NEXT: vmovups (%rsp), %zmm0680; CHECK-AVX512-O0-NEXT: addq $72, %rsp681; CHECK-AVX512-O0-NEXT: retq682 %ret = load atomic <32 x half>, ptr %x acquire, align 4683 ret <32 x half> %ret684}685