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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX14; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512F6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512BW7 8define void @avg_v4i8(ptr %a, ptr %b) nounwind {9; SSE2-LABEL: avg_v4i8:10; SSE2:       # %bb.0:11; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero12; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero13; SSE2-NEXT:    pavgb %xmm0, %xmm114; SSE2-NEXT:    movd %xmm1, (%rax)15; SSE2-NEXT:    retq16;17; AVX-LABEL: avg_v4i8:18; AVX:       # %bb.0:19; AVX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero20; AVX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero21; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm022; AVX-NEXT:    vmovd %xmm0, (%rax)23; AVX-NEXT:    retq24  %1 = load <4 x i8>, ptr %a25  %2 = load <4 x i8>, ptr %b26  %3 = zext <4 x i8> %1 to <4 x i32>27  %4 = zext <4 x i8> %2 to <4 x i32>28  %5 = add nuw nsw <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>29  %6 = add nuw nsw <4 x i32> %5, %430  %7 = lshr <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>31  %8 = trunc <4 x i32> %7 to <4 x i8>32  store <4 x i8> %8, ptr undef, align 433  ret void34}35 36define void @avg_v8i8(ptr %a, ptr %b) nounwind {37; SSE2-LABEL: avg_v8i8:38; SSE2:       # %bb.0:39; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero40; SSE2-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero41; SSE2-NEXT:    pavgb %xmm0, %xmm142; SSE2-NEXT:    movq %xmm1, (%rax)43; SSE2-NEXT:    retq44;45; AVX-LABEL: avg_v8i8:46; AVX:       # %bb.0:47; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero48; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero49; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm050; AVX-NEXT:    vmovq %xmm0, (%rax)51; AVX-NEXT:    retq52  %1 = load <8 x i8>, ptr %a53  %2 = load <8 x i8>, ptr %b54  %3 = zext <8 x i8> %1 to <8 x i32>55  %4 = zext <8 x i8> %2 to <8 x i32>56  %5 = add nuw nsw <8 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>57  %6 = add nuw nsw <8 x i32> %5, %458  %7 = lshr <8 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>59  %8 = trunc <8 x i32> %7 to <8 x i8>60  store <8 x i8> %8, ptr undef, align 461  ret void62}63 64define void @avg_v16i8(ptr %a, ptr %b) nounwind {65; SSE2-LABEL: avg_v16i8:66; SSE2:       # %bb.0:67; SSE2-NEXT:    movdqa (%rdi), %xmm068; SSE2-NEXT:    pavgb (%rsi), %xmm069; SSE2-NEXT:    movdqu %xmm0, (%rax)70; SSE2-NEXT:    retq71;72; AVX-LABEL: avg_v16i8:73; AVX:       # %bb.0:74; AVX-NEXT:    vmovdqa (%rdi), %xmm075; AVX-NEXT:    vpavgb (%rsi), %xmm0, %xmm076; AVX-NEXT:    vmovdqu %xmm0, (%rax)77; AVX-NEXT:    retq78  %1 = load <16 x i8>, ptr %a79  %2 = load <16 x i8>, ptr %b80  %3 = zext <16 x i8> %1 to <16 x i32>81  %4 = zext <16 x i8> %2 to <16 x i32>82  %5 = add nuw nsw <16 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>83  %6 = add nuw nsw <16 x i32> %5, %484  %7 = lshr <16 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>85  %8 = trunc <16 x i32> %7 to <16 x i8>86  store <16 x i8> %8, ptr undef, align 487  ret void88}89 90define void @avg_v24i8(ptr %a, ptr %b) nounwind {91; SSE2-LABEL: avg_v24i8:92; SSE2:       # %bb.0:93; SSE2-NEXT:    movdqa (%rdi), %xmm094; SSE2-NEXT:    movdqa 16(%rdi), %xmm195; SSE2-NEXT:    pavgb (%rsi), %xmm096; SSE2-NEXT:    pavgb 16(%rsi), %xmm197; SSE2-NEXT:    movq %xmm1, (%rax)98; SSE2-NEXT:    movdqu %xmm0, (%rax)99; SSE2-NEXT:    retq100;101; AVX1-LABEL: avg_v24i8:102; AVX1:       # %bb.0:103; AVX1-NEXT:    vmovdqa (%rdi), %xmm0104; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1105; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0106; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1107; AVX1-NEXT:    vmovq %xmm1, (%rax)108; AVX1-NEXT:    vmovdqu %xmm0, (%rax)109; AVX1-NEXT:    retq110;111; AVX2-LABEL: avg_v24i8:112; AVX2:       # %bb.0:113; AVX2-NEXT:    vmovdqa (%rdi), %ymm0114; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0115; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1116; AVX2-NEXT:    vmovq %xmm1, (%rax)117; AVX2-NEXT:    vmovdqu %xmm0, (%rax)118; AVX2-NEXT:    vzeroupper119; AVX2-NEXT:    retq120;121; AVX512-LABEL: avg_v24i8:122; AVX512:       # %bb.0:123; AVX512-NEXT:    vmovdqa (%rdi), %ymm0124; AVX512-NEXT:    vpavgb (%rsi), %ymm0, %ymm0125; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm1126; AVX512-NEXT:    vmovq %xmm1, (%rax)127; AVX512-NEXT:    vmovdqu %xmm0, (%rax)128; AVX512-NEXT:    vzeroupper129; AVX512-NEXT:    retq130  %1 = load <24 x i8>, ptr %a131  %2 = load <24 x i8>, ptr %b132  %3 = zext <24 x i8> %1 to <24 x i32>133  %4 = zext <24 x i8> %2 to <24 x i32>134  %5 = add nuw nsw <24 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>135  %6 = add nuw nsw <24 x i32> %5, %4136  %7 = lshr <24 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>137  %8 = trunc <24 x i32> %7 to <24 x i8>138  store <24 x i8> %8, ptr undef, align 4139  ret void140}141 142define void @avg_v32i8(ptr %a, ptr %b) nounwind {143; SSE2-LABEL: avg_v32i8:144; SSE2:       # %bb.0:145; SSE2-NEXT:    movdqa (%rdi), %xmm0146; SSE2-NEXT:    movdqa 16(%rdi), %xmm1147; SSE2-NEXT:    pavgb (%rsi), %xmm0148; SSE2-NEXT:    pavgb 16(%rsi), %xmm1149; SSE2-NEXT:    movdqu %xmm1, (%rax)150; SSE2-NEXT:    movdqu %xmm0, (%rax)151; SSE2-NEXT:    retq152;153; AVX1-LABEL: avg_v32i8:154; AVX1:       # %bb.0:155; AVX1-NEXT:    vmovdqa (%rdi), %xmm0156; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1157; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0158; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1159; AVX1-NEXT:    vmovdqu %xmm1, (%rax)160; AVX1-NEXT:    vmovdqu %xmm0, (%rax)161; AVX1-NEXT:    retq162;163; AVX2-LABEL: avg_v32i8:164; AVX2:       # %bb.0:165; AVX2-NEXT:    vmovdqa (%rdi), %ymm0166; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0167; AVX2-NEXT:    vmovdqu %ymm0, (%rax)168; AVX2-NEXT:    vzeroupper169; AVX2-NEXT:    retq170;171; AVX512-LABEL: avg_v32i8:172; AVX512:       # %bb.0:173; AVX512-NEXT:    vmovdqa (%rdi), %ymm0174; AVX512-NEXT:    vpavgb (%rsi), %ymm0, %ymm0175; AVX512-NEXT:    vmovdqu %ymm0, (%rax)176; AVX512-NEXT:    vzeroupper177; AVX512-NEXT:    retq178  %1 = load <32 x i8>, ptr %a179  %2 = load <32 x i8>, ptr %b180  %3 = zext <32 x i8> %1 to <32 x i32>181  %4 = zext <32 x i8> %2 to <32 x i32>182  %5 = add nuw nsw <32 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>183  %6 = add nuw nsw <32 x i32> %5, %4184  %7 = lshr <32 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>185  %8 = trunc <32 x i32> %7 to <32 x i8>186  store <32 x i8> %8, ptr undef, align 4187  ret void188}189 190define void @avg_v48i8(ptr %a, ptr %b) nounwind {191; SSE2-LABEL: avg_v48i8:192; SSE2:       # %bb.0:193; SSE2-NEXT:    movdqa (%rdi), %xmm0194; SSE2-NEXT:    movdqa 16(%rdi), %xmm1195; SSE2-NEXT:    movdqa 32(%rdi), %xmm2196; SSE2-NEXT:    pavgb (%rsi), %xmm0197; SSE2-NEXT:    pavgb 16(%rsi), %xmm1198; SSE2-NEXT:    pavgb 32(%rsi), %xmm2199; SSE2-NEXT:    movdqu %xmm2, (%rax)200; SSE2-NEXT:    movdqu %xmm1, (%rax)201; SSE2-NEXT:    movdqu %xmm0, (%rax)202; SSE2-NEXT:    retq203;204; AVX1-LABEL: avg_v48i8:205; AVX1:       # %bb.0:206; AVX1-NEXT:    vmovdqa (%rdi), %xmm0207; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1208; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2209; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0210; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1211; AVX1-NEXT:    vpavgb 32(%rsi), %xmm2, %xmm2212; AVX1-NEXT:    vmovdqu %xmm1, (%rax)213; AVX1-NEXT:    vmovdqu %xmm0, (%rax)214; AVX1-NEXT:    vmovdqu %xmm2, (%rax)215; AVX1-NEXT:    retq216;217; AVX2-LABEL: avg_v48i8:218; AVX2:       # %bb.0:219; AVX2-NEXT:    vmovdqa (%rdi), %ymm0220; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0221; AVX2-NEXT:    vmovdqa 32(%rdi), %xmm1222; AVX2-NEXT:    vpavgb 32(%rsi), %xmm1, %xmm1223; AVX2-NEXT:    vmovdqu %xmm1, (%rax)224; AVX2-NEXT:    vmovdqu %ymm0, (%rax)225; AVX2-NEXT:    vzeroupper226; AVX2-NEXT:    retq227;228; AVX512F-LABEL: avg_v48i8:229; AVX512F:       # %bb.0:230; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0231; AVX512F-NEXT:    vpavgb (%rsi), %ymm0, %ymm0232; AVX512F-NEXT:    vmovdqa 32(%rdi), %xmm1233; AVX512F-NEXT:    vpavgb 32(%rsi), %xmm1, %xmm1234; AVX512F-NEXT:    vmovdqu %xmm1, (%rax)235; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)236; AVX512F-NEXT:    vzeroupper237; AVX512F-NEXT:    retq238;239; AVX512BW-LABEL: avg_v48i8:240; AVX512BW:       # %bb.0:241; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0242; AVX512BW-NEXT:    vpavgb (%rsi), %zmm0, %zmm0243; AVX512BW-NEXT:    vextracti32x4 $2, %zmm0, (%rax)244; AVX512BW-NEXT:    vmovdqu %ymm0, (%rax)245; AVX512BW-NEXT:    vzeroupper246; AVX512BW-NEXT:    retq247  %1 = load <48 x i8>, ptr %a248  %2 = load <48 x i8>, ptr %b249  %3 = zext <48 x i8> %1 to <48 x i32>250  %4 = zext <48 x i8> %2 to <48 x i32>251  %5 = add nuw nsw <48 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>252  %6 = add nuw nsw <48 x i32> %5, %4253  %7 = lshr <48 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>254  %8 = trunc <48 x i32> %7 to <48 x i8>255  store <48 x i8> %8, ptr undef, align 4256  ret void257}258 259define void @avg_v64i8(ptr %a, ptr %b) nounwind {260; SSE2-LABEL: avg_v64i8:261; SSE2:       # %bb.0:262; SSE2-NEXT:    movdqa (%rdi), %xmm0263; SSE2-NEXT:    movdqa 16(%rdi), %xmm1264; SSE2-NEXT:    movdqa 32(%rdi), %xmm2265; SSE2-NEXT:    movdqa 48(%rdi), %xmm3266; SSE2-NEXT:    pavgb (%rsi), %xmm0267; SSE2-NEXT:    pavgb 16(%rsi), %xmm1268; SSE2-NEXT:    pavgb 32(%rsi), %xmm2269; SSE2-NEXT:    pavgb 48(%rsi), %xmm3270; SSE2-NEXT:    movdqu %xmm3, (%rax)271; SSE2-NEXT:    movdqu %xmm2, (%rax)272; SSE2-NEXT:    movdqu %xmm1, (%rax)273; SSE2-NEXT:    movdqu %xmm0, (%rax)274; SSE2-NEXT:    retq275;276; AVX1-LABEL: avg_v64i8:277; AVX1:       # %bb.0:278; AVX1-NEXT:    vmovdqa (%rdi), %xmm0279; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1280; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2281; AVX1-NEXT:    vmovdqa 48(%rdi), %xmm3282; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0283; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1284; AVX1-NEXT:    vpavgb 32(%rsi), %xmm2, %xmm2285; AVX1-NEXT:    vpavgb 48(%rsi), %xmm3, %xmm3286; AVX1-NEXT:    vmovdqu %xmm3, (%rax)287; AVX1-NEXT:    vmovdqu %xmm2, (%rax)288; AVX1-NEXT:    vmovdqu %xmm1, (%rax)289; AVX1-NEXT:    vmovdqu %xmm0, (%rax)290; AVX1-NEXT:    retq291;292; AVX2-LABEL: avg_v64i8:293; AVX2:       # %bb.0:294; AVX2-NEXT:    vmovdqa (%rdi), %ymm0295; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm1296; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0297; AVX2-NEXT:    vpavgb 32(%rsi), %ymm1, %ymm1298; AVX2-NEXT:    vmovdqu %ymm1, (%rax)299; AVX2-NEXT:    vmovdqu %ymm0, (%rax)300; AVX2-NEXT:    vzeroupper301; AVX2-NEXT:    retq302;303; AVX512F-LABEL: avg_v64i8:304; AVX512F:       # %bb.0:305; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0306; AVX512F-NEXT:    vmovdqa 32(%rdi), %ymm1307; AVX512F-NEXT:    vpavgb (%rsi), %ymm0, %ymm0308; AVX512F-NEXT:    vpavgb 32(%rsi), %ymm1, %ymm1309; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)310; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)311; AVX512F-NEXT:    vzeroupper312; AVX512F-NEXT:    retq313;314; AVX512BW-LABEL: avg_v64i8:315; AVX512BW:       # %bb.0:316; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0317; AVX512BW-NEXT:    vpavgb (%rsi), %zmm0, %zmm0318; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)319; AVX512BW-NEXT:    vzeroupper320; AVX512BW-NEXT:    retq321  %1 = load <64 x i8>, ptr %a322  %2 = load <64 x i8>, ptr %b323  %3 = zext <64 x i8> %1 to <64 x i32>324  %4 = zext <64 x i8> %2 to <64 x i32>325  %5 = add nuw nsw <64 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>326  %6 = add nuw nsw <64 x i32> %5, %4327  %7 = lshr <64 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>328  %8 = trunc <64 x i32> %7 to <64 x i8>329  store <64 x i8> %8, ptr undef, align 4330  ret void331}332 333define void @avg_v4i16(ptr %a, ptr %b) nounwind {334; SSE2-LABEL: avg_v4i16:335; SSE2:       # %bb.0:336; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero337; SSE2-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero338; SSE2-NEXT:    pavgw %xmm0, %xmm1339; SSE2-NEXT:    movq %xmm1, (%rax)340; SSE2-NEXT:    retq341;342; AVX-LABEL: avg_v4i16:343; AVX:       # %bb.0:344; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero345; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero346; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm0347; AVX-NEXT:    vmovq %xmm0, (%rax)348; AVX-NEXT:    retq349  %1 = load <4 x i16>, ptr %a350  %2 = load <4 x i16>, ptr %b351  %3 = zext <4 x i16> %1 to <4 x i32>352  %4 = zext <4 x i16> %2 to <4 x i32>353  %5 = add nuw nsw <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>354  %6 = add nuw nsw <4 x i32> %5, %4355  %7 = lshr <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>356  %8 = trunc <4 x i32> %7 to <4 x i16>357  store <4 x i16> %8, ptr undef, align 4358  ret void359}360 361define void @avg_v8i16(ptr %a, ptr %b) nounwind {362; SSE2-LABEL: avg_v8i16:363; SSE2:       # %bb.0:364; SSE2-NEXT:    movdqa (%rdi), %xmm0365; SSE2-NEXT:    pavgw (%rsi), %xmm0366; SSE2-NEXT:    movdqu %xmm0, (%rax)367; SSE2-NEXT:    retq368;369; AVX-LABEL: avg_v8i16:370; AVX:       # %bb.0:371; AVX-NEXT:    vmovdqa (%rdi), %xmm0372; AVX-NEXT:    vpavgw (%rsi), %xmm0, %xmm0373; AVX-NEXT:    vmovdqu %xmm0, (%rax)374; AVX-NEXT:    retq375  %1 = load <8 x i16>, ptr %a376  %2 = load <8 x i16>, ptr %b377  %3 = zext <8 x i16> %1 to <8 x i32>378  %4 = zext <8 x i16> %2 to <8 x i32>379  %5 = add nuw nsw <8 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>380  %6 = add nuw nsw <8 x i32> %5, %4381  %7 = lshr <8 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>382  %8 = trunc <8 x i32> %7 to <8 x i16>383  store <8 x i16> %8, ptr undef, align 4384  ret void385}386 387define void @avg_v16i16(ptr %a, ptr %b) nounwind {388; SSE2-LABEL: avg_v16i16:389; SSE2:       # %bb.0:390; SSE2-NEXT:    movdqa (%rdi), %xmm0391; SSE2-NEXT:    movdqa 16(%rdi), %xmm1392; SSE2-NEXT:    pavgw (%rsi), %xmm0393; SSE2-NEXT:    pavgw 16(%rsi), %xmm1394; SSE2-NEXT:    movdqu %xmm1, (%rax)395; SSE2-NEXT:    movdqu %xmm0, (%rax)396; SSE2-NEXT:    retq397;398; AVX1-LABEL: avg_v16i16:399; AVX1:       # %bb.0:400; AVX1-NEXT:    vmovdqa (%rdi), %xmm0401; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1402; AVX1-NEXT:    vpavgw (%rsi), %xmm0, %xmm0403; AVX1-NEXT:    vpavgw 16(%rsi), %xmm1, %xmm1404; AVX1-NEXT:    vmovdqu %xmm1, (%rax)405; AVX1-NEXT:    vmovdqu %xmm0, (%rax)406; AVX1-NEXT:    retq407;408; AVX2-LABEL: avg_v16i16:409; AVX2:       # %bb.0:410; AVX2-NEXT:    vmovdqa (%rdi), %ymm0411; AVX2-NEXT:    vpavgw (%rsi), %ymm0, %ymm0412; AVX2-NEXT:    vmovdqu %ymm0, (%rax)413; AVX2-NEXT:    vzeroupper414; AVX2-NEXT:    retq415;416; AVX512-LABEL: avg_v16i16:417; AVX512:       # %bb.0:418; AVX512-NEXT:    vmovdqa (%rdi), %ymm0419; AVX512-NEXT:    vpavgw (%rsi), %ymm0, %ymm0420; AVX512-NEXT:    vmovdqu %ymm0, (%rax)421; AVX512-NEXT:    vzeroupper422; AVX512-NEXT:    retq423  %1 = load <16 x i16>, ptr %a424  %2 = load <16 x i16>, ptr %b425  %3 = zext <16 x i16> %1 to <16 x i32>426  %4 = zext <16 x i16> %2 to <16 x i32>427  %5 = add nuw nsw <16 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>428  %6 = add nuw nsw <16 x i32> %5, %4429  %7 = lshr <16 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>430  %8 = trunc <16 x i32> %7 to <16 x i16>431  store <16 x i16> %8, ptr undef, align 4432  ret void433}434 435define void @avg_v32i16(ptr %a, ptr %b) nounwind {436; SSE2-LABEL: avg_v32i16:437; SSE2:       # %bb.0:438; SSE2-NEXT:    movdqa (%rdi), %xmm0439; SSE2-NEXT:    movdqa 16(%rdi), %xmm1440; SSE2-NEXT:    movdqa 32(%rdi), %xmm2441; SSE2-NEXT:    movdqa 48(%rdi), %xmm3442; SSE2-NEXT:    pavgw (%rsi), %xmm0443; SSE2-NEXT:    pavgw 16(%rsi), %xmm1444; SSE2-NEXT:    pavgw 32(%rsi), %xmm2445; SSE2-NEXT:    pavgw 48(%rsi), %xmm3446; SSE2-NEXT:    movdqu %xmm3, (%rax)447; SSE2-NEXT:    movdqu %xmm2, (%rax)448; SSE2-NEXT:    movdqu %xmm1, (%rax)449; SSE2-NEXT:    movdqu %xmm0, (%rax)450; SSE2-NEXT:    retq451;452; AVX1-LABEL: avg_v32i16:453; AVX1:       # %bb.0:454; AVX1-NEXT:    vmovdqa (%rdi), %xmm0455; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1456; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2457; AVX1-NEXT:    vmovdqa 48(%rdi), %xmm3458; AVX1-NEXT:    vpavgw (%rsi), %xmm0, %xmm0459; AVX1-NEXT:    vpavgw 16(%rsi), %xmm1, %xmm1460; AVX1-NEXT:    vpavgw 32(%rsi), %xmm2, %xmm2461; AVX1-NEXT:    vpavgw 48(%rsi), %xmm3, %xmm3462; AVX1-NEXT:    vmovdqu %xmm3, (%rax)463; AVX1-NEXT:    vmovdqu %xmm2, (%rax)464; AVX1-NEXT:    vmovdqu %xmm1, (%rax)465; AVX1-NEXT:    vmovdqu %xmm0, (%rax)466; AVX1-NEXT:    retq467;468; AVX2-LABEL: avg_v32i16:469; AVX2:       # %bb.0:470; AVX2-NEXT:    vmovdqa (%rdi), %ymm0471; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm1472; AVX2-NEXT:    vpavgw (%rsi), %ymm0, %ymm0473; AVX2-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1474; AVX2-NEXT:    vmovdqu %ymm1, (%rax)475; AVX2-NEXT:    vmovdqu %ymm0, (%rax)476; AVX2-NEXT:    vzeroupper477; AVX2-NEXT:    retq478;479; AVX512F-LABEL: avg_v32i16:480; AVX512F:       # %bb.0:481; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0482; AVX512F-NEXT:    vmovdqa 32(%rdi), %ymm1483; AVX512F-NEXT:    vpavgw (%rsi), %ymm0, %ymm0484; AVX512F-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1485; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)486; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)487; AVX512F-NEXT:    vzeroupper488; AVX512F-NEXT:    retq489;490; AVX512BW-LABEL: avg_v32i16:491; AVX512BW:       # %bb.0:492; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0493; AVX512BW-NEXT:    vpavgw (%rsi), %zmm0, %zmm0494; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)495; AVX512BW-NEXT:    vzeroupper496; AVX512BW-NEXT:    retq497  %1 = load <32 x i16>, ptr %a498  %2 = load <32 x i16>, ptr %b499  %3 = zext <32 x i16> %1 to <32 x i32>500  %4 = zext <32 x i16> %2 to <32 x i32>501  %5 = add nuw nsw <32 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>502  %6 = add nuw nsw <32 x i32> %5, %4503  %7 = lshr <32 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>504  %8 = trunc <32 x i32> %7 to <32 x i16>505  store <32 x i16> %8, ptr undef, align 4506  ret void507}508 509define void @avg_v40i16(ptr %a, ptr %b) nounwind {510; SSE2-LABEL: avg_v40i16:511; SSE2:       # %bb.0:512; SSE2-NEXT:    movdqa 64(%rdi), %xmm0513; SSE2-NEXT:    movdqa (%rdi), %xmm1514; SSE2-NEXT:    movdqa 16(%rdi), %xmm2515; SSE2-NEXT:    movdqa 32(%rdi), %xmm3516; SSE2-NEXT:    movdqa 48(%rdi), %xmm4517; SSE2-NEXT:    pavgw (%rsi), %xmm1518; SSE2-NEXT:    pavgw 16(%rsi), %xmm2519; SSE2-NEXT:    pavgw 32(%rsi), %xmm3520; SSE2-NEXT:    pavgw 48(%rsi), %xmm4521; SSE2-NEXT:    pavgw 64(%rsi), %xmm0522; SSE2-NEXT:    movdqu %xmm0, (%rax)523; SSE2-NEXT:    movdqu %xmm4, (%rax)524; SSE2-NEXT:    movdqu %xmm3, (%rax)525; SSE2-NEXT:    movdqu %xmm2, (%rax)526; SSE2-NEXT:    movdqu %xmm1, (%rax)527; SSE2-NEXT:    retq528;529; AVX1-LABEL: avg_v40i16:530; AVX1:       # %bb.0:531; AVX1-NEXT:    vmovdqa (%rdi), %xmm0532; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1533; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2534; AVX1-NEXT:    vmovdqa 48(%rdi), %xmm3535; AVX1-NEXT:    vpavgw (%rsi), %xmm0, %xmm0536; AVX1-NEXT:    vpavgw 16(%rsi), %xmm1, %xmm1537; AVX1-NEXT:    vpavgw 32(%rsi), %xmm2, %xmm2538; AVX1-NEXT:    vpavgw 48(%rsi), %xmm3, %xmm3539; AVX1-NEXT:    vmovdqa 64(%rdi), %xmm4540; AVX1-NEXT:    vpavgw 64(%rsi), %xmm4, %xmm4541; AVX1-NEXT:    vmovdqu %xmm3, (%rax)542; AVX1-NEXT:    vmovdqu %xmm2, (%rax)543; AVX1-NEXT:    vmovdqu %xmm1, (%rax)544; AVX1-NEXT:    vmovdqu %xmm0, (%rax)545; AVX1-NEXT:    vmovdqu %xmm4, (%rax)546; AVX1-NEXT:    retq547;548; AVX2-LABEL: avg_v40i16:549; AVX2:       # %bb.0:550; AVX2-NEXT:    vmovdqa (%rdi), %ymm0551; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm1552; AVX2-NEXT:    vpavgw (%rsi), %ymm0, %ymm0553; AVX2-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1554; AVX2-NEXT:    vmovdqa 64(%rdi), %xmm2555; AVX2-NEXT:    vpavgw 64(%rsi), %xmm2, %xmm2556; AVX2-NEXT:    vmovdqu %xmm2, (%rax)557; AVX2-NEXT:    vmovdqu %ymm1, (%rax)558; AVX2-NEXT:    vmovdqu %ymm0, (%rax)559; AVX2-NEXT:    vzeroupper560; AVX2-NEXT:    retq561;562; AVX512F-LABEL: avg_v40i16:563; AVX512F:       # %bb.0:564; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0565; AVX512F-NEXT:    vmovdqa 32(%rdi), %ymm1566; AVX512F-NEXT:    vpavgw (%rsi), %ymm0, %ymm0567; AVX512F-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1568; AVX512F-NEXT:    vmovdqa 64(%rdi), %xmm2569; AVX512F-NEXT:    vpavgw 64(%rsi), %xmm2, %xmm2570; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)571; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)572; AVX512F-NEXT:    vmovdqu %xmm2, (%rax)573; AVX512F-NEXT:    vzeroupper574; AVX512F-NEXT:    retq575;576; AVX512BW-LABEL: avg_v40i16:577; AVX512BW:       # %bb.0:578; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0579; AVX512BW-NEXT:    vpavgw (%rsi), %zmm0, %zmm0580; AVX512BW-NEXT:    vmovdqa 64(%rdi), %xmm1581; AVX512BW-NEXT:    vpavgw 64(%rsi), %xmm1, %xmm1582; AVX512BW-NEXT:    vmovdqu %xmm1, (%rax)583; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)584; AVX512BW-NEXT:    vzeroupper585; AVX512BW-NEXT:    retq586  %1 = load <40 x i16>, ptr %a587  %2 = load <40 x i16>, ptr %b588  %3 = zext <40 x i16> %1 to <40 x i32>589  %4 = zext <40 x i16> %2 to <40 x i32>590  %5 = add nuw nsw <40 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>591  %6 = add nuw nsw <40 x i32> %5, %4592  %7 = lshr <40 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>593  %8 = trunc <40 x i32> %7 to <40 x i16>594  store <40 x i16> %8, ptr undef, align 4595  ret void596}597 598define void @avg_v4i8_2(ptr %a, ptr %b) nounwind {599; SSE2-LABEL: avg_v4i8_2:600; SSE2:       # %bb.0:601; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero602; SSE2-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero603; SSE2-NEXT:    pavgb %xmm0, %xmm1604; SSE2-NEXT:    movd %xmm1, (%rax)605; SSE2-NEXT:    retq606;607; AVX-LABEL: avg_v4i8_2:608; AVX:       # %bb.0:609; AVX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero610; AVX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero611; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm0612; AVX-NEXT:    vmovd %xmm0, (%rax)613; AVX-NEXT:    retq614  %1 = load <4 x i8>, ptr %a615  %2 = load <4 x i8>, ptr %b616  %3 = zext <4 x i8> %1 to <4 x i32>617  %4 = zext <4 x i8> %2 to <4 x i32>618  %5 = add nuw nsw <4 x i32> %3, %4619  %6 = add nuw nsw <4 x i32> %5, <i32 1, i32 1, i32 1, i32 1>620  %7 = lshr <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>621  %8 = trunc <4 x i32> %7 to <4 x i8>622  store <4 x i8> %8, ptr undef, align 4623  ret void624}625 626define void @avg_v8i8_2(ptr %a, ptr %b) nounwind {627; SSE2-LABEL: avg_v8i8_2:628; SSE2:       # %bb.0:629; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero630; SSE2-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero631; SSE2-NEXT:    pavgb %xmm0, %xmm1632; SSE2-NEXT:    movq %xmm1, (%rax)633; SSE2-NEXT:    retq634;635; AVX-LABEL: avg_v8i8_2:636; AVX:       # %bb.0:637; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero638; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero639; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm0640; AVX-NEXT:    vmovq %xmm0, (%rax)641; AVX-NEXT:    retq642  %1 = load <8 x i8>, ptr %a643  %2 = load <8 x i8>, ptr %b644  %3 = zext <8 x i8> %1 to <8 x i32>645  %4 = zext <8 x i8> %2 to <8 x i32>646  %5 = add nuw nsw <8 x i32> %3, %4647  %6 = add nuw nsw <8 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>648  %7 = lshr <8 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>649  %8 = trunc <8 x i32> %7 to <8 x i8>650  store <8 x i8> %8, ptr undef, align 4651  ret void652}653 654define void @avg_v16i8_2(ptr %a, ptr %b) nounwind {655; SSE2-LABEL: avg_v16i8_2:656; SSE2:       # %bb.0:657; SSE2-NEXT:    movdqa (%rdi), %xmm0658; SSE2-NEXT:    pavgb (%rsi), %xmm0659; SSE2-NEXT:    movdqu %xmm0, (%rax)660; SSE2-NEXT:    retq661;662; AVX-LABEL: avg_v16i8_2:663; AVX:       # %bb.0:664; AVX-NEXT:    vmovdqa (%rdi), %xmm0665; AVX-NEXT:    vpavgb (%rsi), %xmm0, %xmm0666; AVX-NEXT:    vmovdqu %xmm0, (%rax)667; AVX-NEXT:    retq668  %1 = load <16 x i8>, ptr %a669  %2 = load <16 x i8>, ptr %b670  %3 = zext <16 x i8> %1 to <16 x i32>671  %4 = zext <16 x i8> %2 to <16 x i32>672  %5 = add nuw nsw <16 x i32> %3, %4673  %6 = add nuw nsw <16 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>674  %7 = lshr <16 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>675  %8 = trunc <16 x i32> %7 to <16 x i8>676  store <16 x i8> %8, ptr undef, align 4677  ret void678}679 680define void @avg_v32i8_2(ptr %a, ptr %b) nounwind {681; SSE2-LABEL: avg_v32i8_2:682; SSE2:       # %bb.0:683; SSE2-NEXT:    movdqa (%rdi), %xmm0684; SSE2-NEXT:    movdqa 16(%rdi), %xmm1685; SSE2-NEXT:    pavgb (%rsi), %xmm0686; SSE2-NEXT:    pavgb 16(%rsi), %xmm1687; SSE2-NEXT:    movdqu %xmm1, (%rax)688; SSE2-NEXT:    movdqu %xmm0, (%rax)689; SSE2-NEXT:    retq690;691; AVX1-LABEL: avg_v32i8_2:692; AVX1:       # %bb.0:693; AVX1-NEXT:    vmovdqa (%rdi), %xmm0694; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1695; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0696; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1697; AVX1-NEXT:    vmovdqu %xmm1, (%rax)698; AVX1-NEXT:    vmovdqu %xmm0, (%rax)699; AVX1-NEXT:    retq700;701; AVX2-LABEL: avg_v32i8_2:702; AVX2:       # %bb.0:703; AVX2-NEXT:    vmovdqa (%rdi), %ymm0704; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0705; AVX2-NEXT:    vmovdqu %ymm0, (%rax)706; AVX2-NEXT:    vzeroupper707; AVX2-NEXT:    retq708;709; AVX512-LABEL: avg_v32i8_2:710; AVX512:       # %bb.0:711; AVX512-NEXT:    vmovdqa (%rdi), %ymm0712; AVX512-NEXT:    vpavgb (%rsi), %ymm0, %ymm0713; AVX512-NEXT:    vmovdqu %ymm0, (%rax)714; AVX512-NEXT:    vzeroupper715; AVX512-NEXT:    retq716  %1 = load <32 x i8>, ptr %a717  %2 = load <32 x i8>, ptr %b718  %3 = zext <32 x i8> %1 to <32 x i32>719  %4 = zext <32 x i8> %2 to <32 x i32>720  %5 = add nuw nsw <32 x i32> %3, %4721  %6 = add nuw nsw <32 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>722  %7 = lshr <32 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>723  %8 = trunc <32 x i32> %7 to <32 x i8>724  store <32 x i8> %8, ptr undef, align 4725  ret void726}727 728define void @avg_v64i8_2(ptr %a, ptr %b) nounwind {729; SSE2-LABEL: avg_v64i8_2:730; SSE2:       # %bb.0:731; SSE2-NEXT:    movdqa (%rdi), %xmm0732; SSE2-NEXT:    movdqa 16(%rdi), %xmm1733; SSE2-NEXT:    movdqa 32(%rdi), %xmm2734; SSE2-NEXT:    movdqa 48(%rdi), %xmm3735; SSE2-NEXT:    pavgb (%rsi), %xmm0736; SSE2-NEXT:    pavgb 16(%rsi), %xmm1737; SSE2-NEXT:    pavgb 32(%rsi), %xmm2738; SSE2-NEXT:    pavgb 48(%rsi), %xmm3739; SSE2-NEXT:    movdqu %xmm3, (%rax)740; SSE2-NEXT:    movdqu %xmm2, (%rax)741; SSE2-NEXT:    movdqu %xmm1, (%rax)742; SSE2-NEXT:    movdqu %xmm0, (%rax)743; SSE2-NEXT:    retq744;745; AVX1-LABEL: avg_v64i8_2:746; AVX1:       # %bb.0:747; AVX1-NEXT:    vmovdqa (%rdi), %xmm0748; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1749; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2750; AVX1-NEXT:    vmovdqa 48(%rdi), %xmm3751; AVX1-NEXT:    vpavgb (%rsi), %xmm0, %xmm0752; AVX1-NEXT:    vpavgb 16(%rsi), %xmm1, %xmm1753; AVX1-NEXT:    vpavgb 32(%rsi), %xmm2, %xmm2754; AVX1-NEXT:    vpavgb 48(%rsi), %xmm3, %xmm3755; AVX1-NEXT:    vmovdqu %xmm3, (%rax)756; AVX1-NEXT:    vmovdqu %xmm2, (%rax)757; AVX1-NEXT:    vmovdqu %xmm1, (%rax)758; AVX1-NEXT:    vmovdqu %xmm0, (%rax)759; AVX1-NEXT:    retq760;761; AVX2-LABEL: avg_v64i8_2:762; AVX2:       # %bb.0:763; AVX2-NEXT:    vmovdqa (%rdi), %ymm0764; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm1765; AVX2-NEXT:    vpavgb (%rsi), %ymm0, %ymm0766; AVX2-NEXT:    vpavgb 32(%rsi), %ymm1, %ymm1767; AVX2-NEXT:    vmovdqu %ymm1, (%rax)768; AVX2-NEXT:    vmovdqu %ymm0, (%rax)769; AVX2-NEXT:    vzeroupper770; AVX2-NEXT:    retq771;772; AVX512F-LABEL: avg_v64i8_2:773; AVX512F:       # %bb.0:774; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0775; AVX512F-NEXT:    vmovdqa 32(%rdi), %ymm1776; AVX512F-NEXT:    vpavgb (%rsi), %ymm0, %ymm0777; AVX512F-NEXT:    vpavgb 32(%rsi), %ymm1, %ymm1778; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)779; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)780; AVX512F-NEXT:    vzeroupper781; AVX512F-NEXT:    retq782;783; AVX512BW-LABEL: avg_v64i8_2:784; AVX512BW:       # %bb.0:785; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0786; AVX512BW-NEXT:    vpavgb (%rsi), %zmm0, %zmm0787; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)788; AVX512BW-NEXT:    vzeroupper789; AVX512BW-NEXT:    retq790  %1 = load <64 x i8>, ptr %a791  %2 = load <64 x i8>, ptr %b792  %3 = zext <64 x i8> %1 to <64 x i32>793  %4 = zext <64 x i8> %2 to <64 x i32>794  %5 = add nuw nsw <64 x i32> %3, %4795  %6 = add nuw nsw <64 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>796  %7 = lshr <64 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>797  %8 = trunc <64 x i32> %7 to <64 x i8>798  store <64 x i8> %8, ptr undef, align 4799  ret void800}801 802define void @avg_v4i16_2(ptr %a, ptr %b) nounwind {803; SSE2-LABEL: avg_v4i16_2:804; SSE2:       # %bb.0:805; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero806; SSE2-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero807; SSE2-NEXT:    pavgw %xmm0, %xmm1808; SSE2-NEXT:    movq %xmm1, (%rax)809; SSE2-NEXT:    retq810;811; AVX-LABEL: avg_v4i16_2:812; AVX:       # %bb.0:813; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero814; AVX-NEXT:    vmovq {{.*#+}} xmm1 = mem[0],zero815; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm0816; AVX-NEXT:    vmovq %xmm0, (%rax)817; AVX-NEXT:    retq818  %1 = load <4 x i16>, ptr %a819  %2 = load <4 x i16>, ptr %b820  %3 = zext <4 x i16> %1 to <4 x i32>821  %4 = zext <4 x i16> %2 to <4 x i32>822  %5 = add nuw nsw <4 x i32> %3, %4823  %6 = add nuw nsw <4 x i32> %5, <i32 1, i32 1, i32 1, i32 1>824  %7 = lshr <4 x i32> %6, <i32 1, i32 1, i32 1, i32 1>825  %8 = trunc <4 x i32> %7 to <4 x i16>826  store <4 x i16> %8, ptr undef, align 4827  ret void828}829 830define void @avg_v8i16_2(ptr %a, ptr %b) nounwind {831; SSE2-LABEL: avg_v8i16_2:832; SSE2:       # %bb.0:833; SSE2-NEXT:    movdqa (%rdi), %xmm0834; SSE2-NEXT:    pavgw (%rsi), %xmm0835; SSE2-NEXT:    movdqu %xmm0, (%rax)836; SSE2-NEXT:    retq837;838; AVX-LABEL: avg_v8i16_2:839; AVX:       # %bb.0:840; AVX-NEXT:    vmovdqa (%rdi), %xmm0841; AVX-NEXT:    vpavgw (%rsi), %xmm0, %xmm0842; AVX-NEXT:    vmovdqu %xmm0, (%rax)843; AVX-NEXT:    retq844  %1 = load <8 x i16>, ptr %a845  %2 = load <8 x i16>, ptr %b846  %3 = zext <8 x i16> %1 to <8 x i32>847  %4 = zext <8 x i16> %2 to <8 x i32>848  %5 = add nuw nsw <8 x i32> %3, %4849  %6 = add nuw nsw <8 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>850  %7 = lshr <8 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>851  %8 = trunc <8 x i32> %7 to <8 x i16>852  store <8 x i16> %8, ptr undef, align 4853  ret void854}855 856define void @avg_v16i16_2(ptr %a, ptr %b) nounwind {857; SSE2-LABEL: avg_v16i16_2:858; SSE2:       # %bb.0:859; SSE2-NEXT:    movdqa (%rdi), %xmm0860; SSE2-NEXT:    movdqa 16(%rdi), %xmm1861; SSE2-NEXT:    pavgw (%rsi), %xmm0862; SSE2-NEXT:    pavgw 16(%rsi), %xmm1863; SSE2-NEXT:    movdqu %xmm1, (%rax)864; SSE2-NEXT:    movdqu %xmm0, (%rax)865; SSE2-NEXT:    retq866;867; AVX1-LABEL: avg_v16i16_2:868; AVX1:       # %bb.0:869; AVX1-NEXT:    vmovdqa (%rdi), %xmm0870; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1871; AVX1-NEXT:    vpavgw (%rsi), %xmm0, %xmm0872; AVX1-NEXT:    vpavgw 16(%rsi), %xmm1, %xmm1873; AVX1-NEXT:    vmovdqu %xmm1, (%rax)874; AVX1-NEXT:    vmovdqu %xmm0, (%rax)875; AVX1-NEXT:    retq876;877; AVX2-LABEL: avg_v16i16_2:878; AVX2:       # %bb.0:879; AVX2-NEXT:    vmovdqa (%rdi), %ymm0880; AVX2-NEXT:    vpavgw (%rsi), %ymm0, %ymm0881; AVX2-NEXT:    vmovdqu %ymm0, (%rax)882; AVX2-NEXT:    vzeroupper883; AVX2-NEXT:    retq884;885; AVX512-LABEL: avg_v16i16_2:886; AVX512:       # %bb.0:887; AVX512-NEXT:    vmovdqa (%rdi), %ymm0888; AVX512-NEXT:    vpavgw (%rsi), %ymm0, %ymm0889; AVX512-NEXT:    vmovdqu %ymm0, (%rax)890; AVX512-NEXT:    vzeroupper891; AVX512-NEXT:    retq892  %1 = load <16 x i16>, ptr %a893  %2 = load <16 x i16>, ptr %b894  %3 = zext <16 x i16> %1 to <16 x i32>895  %4 = zext <16 x i16> %2 to <16 x i32>896  %5 = add nuw nsw <16 x i32> %3, %4897  %6 = add nuw nsw <16 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>898  %7 = lshr <16 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>899  %8 = trunc <16 x i32> %7 to <16 x i16>900  store <16 x i16> %8, ptr undef, align 4901  ret void902}903 904define void @avg_v32i16_2(ptr %a, ptr %b) nounwind {905; SSE2-LABEL: avg_v32i16_2:906; SSE2:       # %bb.0:907; SSE2-NEXT:    movdqa (%rdi), %xmm0908; SSE2-NEXT:    movdqa 16(%rdi), %xmm1909; SSE2-NEXT:    movdqa 32(%rdi), %xmm2910; SSE2-NEXT:    movdqa 48(%rdi), %xmm3911; SSE2-NEXT:    pavgw (%rsi), %xmm0912; SSE2-NEXT:    pavgw 16(%rsi), %xmm1913; SSE2-NEXT:    pavgw 32(%rsi), %xmm2914; SSE2-NEXT:    pavgw 48(%rsi), %xmm3915; SSE2-NEXT:    movdqu %xmm3, (%rax)916; SSE2-NEXT:    movdqu %xmm2, (%rax)917; SSE2-NEXT:    movdqu %xmm1, (%rax)918; SSE2-NEXT:    movdqu %xmm0, (%rax)919; SSE2-NEXT:    retq920;921; AVX1-LABEL: avg_v32i16_2:922; AVX1:       # %bb.0:923; AVX1-NEXT:    vmovdqa (%rdi), %xmm0924; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1925; AVX1-NEXT:    vmovdqa 32(%rdi), %xmm2926; AVX1-NEXT:    vmovdqa 48(%rdi), %xmm3927; AVX1-NEXT:    vpavgw (%rsi), %xmm0, %xmm0928; AVX1-NEXT:    vpavgw 16(%rsi), %xmm1, %xmm1929; AVX1-NEXT:    vpavgw 32(%rsi), %xmm2, %xmm2930; AVX1-NEXT:    vpavgw 48(%rsi), %xmm3, %xmm3931; AVX1-NEXT:    vmovdqu %xmm3, (%rax)932; AVX1-NEXT:    vmovdqu %xmm2, (%rax)933; AVX1-NEXT:    vmovdqu %xmm1, (%rax)934; AVX1-NEXT:    vmovdqu %xmm0, (%rax)935; AVX1-NEXT:    retq936;937; AVX2-LABEL: avg_v32i16_2:938; AVX2:       # %bb.0:939; AVX2-NEXT:    vmovdqa (%rdi), %ymm0940; AVX2-NEXT:    vmovdqa 32(%rdi), %ymm1941; AVX2-NEXT:    vpavgw (%rsi), %ymm0, %ymm0942; AVX2-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1943; AVX2-NEXT:    vmovdqu %ymm1, (%rax)944; AVX2-NEXT:    vmovdqu %ymm0, (%rax)945; AVX2-NEXT:    vzeroupper946; AVX2-NEXT:    retq947;948; AVX512F-LABEL: avg_v32i16_2:949; AVX512F:       # %bb.0:950; AVX512F-NEXT:    vmovdqa (%rdi), %ymm0951; AVX512F-NEXT:    vmovdqa 32(%rdi), %ymm1952; AVX512F-NEXT:    vpavgw (%rsi), %ymm0, %ymm0953; AVX512F-NEXT:    vpavgw 32(%rsi), %ymm1, %ymm1954; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)955; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)956; AVX512F-NEXT:    vzeroupper957; AVX512F-NEXT:    retq958;959; AVX512BW-LABEL: avg_v32i16_2:960; AVX512BW:       # %bb.0:961; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm0962; AVX512BW-NEXT:    vpavgw (%rsi), %zmm0, %zmm0963; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)964; AVX512BW-NEXT:    vzeroupper965; AVX512BW-NEXT:    retq966  %1 = load <32 x i16>, ptr %a967  %2 = load <32 x i16>, ptr %b968  %3 = zext <32 x i16> %1 to <32 x i32>969  %4 = zext <32 x i16> %2 to <32 x i32>970  %5 = add nuw nsw <32 x i32> %3, %4971  %6 = add nuw nsw <32 x i32> %5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>972  %7 = lshr <32 x i32> %6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>973  %8 = trunc <32 x i32> %7 to <32 x i16>974  store <32 x i16> %8, ptr undef, align 4975  ret void976}977 978define void @avg_v4i8_const(ptr %a) nounwind {979; SSE2-LABEL: avg_v4i8_const:980; SSE2:       # %bb.0:981; SSE2-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero982; SSE2-NEXT:    pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0983; SSE2-NEXT:    movd %xmm0, (%rax)984; SSE2-NEXT:    retq985;986; AVX-LABEL: avg_v4i8_const:987; AVX:       # %bb.0:988; AVX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero989; AVX-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0990; AVX-NEXT:    vmovd %xmm0, (%rax)991; AVX-NEXT:    retq992  %1 = load <4 x i8>, ptr %a993  %2 = zext <4 x i8> %1 to <4 x i32>994  %3 = add nuw nsw <4 x i32> %2, <i32 1, i32 2, i32 3, i32 4>995  %4 = lshr <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>996  %5 = trunc <4 x i32> %4 to <4 x i8>997  store <4 x i8> %5, ptr undef, align 4998  ret void999}1000 1001define void @avg_v8i8_const(ptr %a) nounwind {1002; SSE2-LABEL: avg_v8i8_const:1003; SSE2:       # %bb.0:1004; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero1005; SSE2-NEXT:    pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm01006; SSE2-NEXT:    movq %xmm0, (%rax)1007; SSE2-NEXT:    retq1008;1009; AVX-LABEL: avg_v8i8_const:1010; AVX:       # %bb.0:1011; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero1012; AVX-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm01013; AVX-NEXT:    vmovq %xmm0, (%rax)1014; AVX-NEXT:    retq1015  %1 = load <8 x i8>, ptr %a1016  %2 = zext <8 x i8> %1 to <8 x i32>1017  %3 = add nuw nsw <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1018  %4 = lshr <8 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1019  %5 = trunc <8 x i32> %4 to <8 x i8>1020  store <8 x i8> %5, ptr undef, align 41021  ret void1022}1023 1024define void @avg_v16i8_const(ptr %a) nounwind {1025; SSE2-LABEL: avg_v16i8_const:1026; SSE2:       # %bb.0:1027; SSE2-NEXT:    movdqa (%rdi), %xmm01028; SSE2-NEXT:    pavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm01029; SSE2-NEXT:    movdqu %xmm0, (%rax)1030; SSE2-NEXT:    retq1031;1032; AVX-LABEL: avg_v16i8_const:1033; AVX:       # %bb.0:1034; AVX-NEXT:    vmovdqa (%rdi), %xmm01035; AVX-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm01036; AVX-NEXT:    vmovdqu %xmm0, (%rax)1037; AVX-NEXT:    retq1038  %1 = load <16 x i8>, ptr %a1039  %2 = zext <16 x i8> %1 to <16 x i32>1040  %3 = add nuw nsw <16 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1041  %4 = lshr <16 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1042  %5 = trunc <16 x i32> %4 to <16 x i8>1043  store <16 x i8> %5, ptr undef, align 41044  ret void1045}1046 1047define void @avg_v32i8_const(ptr %a) nounwind {1048; SSE2-LABEL: avg_v32i8_const:1049; SSE2:       # %bb.0:1050; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1051; SSE2-NEXT:    movdqa (%rdi), %xmm11052; SSE2-NEXT:    pavgb %xmm0, %xmm11053; SSE2-NEXT:    pavgb 16(%rdi), %xmm01054; SSE2-NEXT:    movdqu %xmm0, (%rax)1055; SSE2-NEXT:    movdqu %xmm1, (%rax)1056; SSE2-NEXT:    retq1057;1058; AVX1-LABEL: avg_v32i8_const:1059; AVX1:       # %bb.0:1060; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1061; AVX1-NEXT:    # xmm0 = mem[0,0]1062; AVX1-NEXT:    vpavgb (%rdi), %xmm0, %xmm11063; AVX1-NEXT:    vpavgb 16(%rdi), %xmm0, %xmm01064; AVX1-NEXT:    vmovdqu %xmm0, (%rax)1065; AVX1-NEXT:    vmovdqu %xmm1, (%rax)1066; AVX1-NEXT:    retq1067;1068; AVX2-LABEL: avg_v32i8_const:1069; AVX2:       # %bb.0:1070; AVX2-NEXT:    vmovdqa (%rdi), %ymm01071; AVX2-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm01072; AVX2-NEXT:    vmovdqu %ymm0, (%rax)1073; AVX2-NEXT:    vzeroupper1074; AVX2-NEXT:    retq1075;1076; AVX512-LABEL: avg_v32i8_const:1077; AVX512:       # %bb.0:1078; AVX512-NEXT:    vmovdqa (%rdi), %ymm01079; AVX512-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm01080; AVX512-NEXT:    vmovdqu %ymm0, (%rax)1081; AVX512-NEXT:    vzeroupper1082; AVX512-NEXT:    retq1083  %1 = load <32 x i8>, ptr %a1084  %2 = zext <32 x i8> %1 to <32 x i32>1085  %3 = add nuw nsw <32 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1086  %4 = lshr <32 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1087  %5 = trunc <32 x i32> %4 to <32 x i8>1088  store <32 x i8> %5, ptr undef, align 41089  ret void1090}1091 1092define void @avg_v64i8_const(ptr %a) nounwind {1093; SSE2-LABEL: avg_v64i8_const:1094; SSE2:       # %bb.0:1095; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1096; SSE2-NEXT:    movdqa (%rdi), %xmm11097; SSE2-NEXT:    pavgb %xmm0, %xmm11098; SSE2-NEXT:    movdqa 16(%rdi), %xmm21099; SSE2-NEXT:    pavgb %xmm0, %xmm21100; SSE2-NEXT:    movdqa 32(%rdi), %xmm31101; SSE2-NEXT:    pavgb %xmm0, %xmm31102; SSE2-NEXT:    pavgb 48(%rdi), %xmm01103; SSE2-NEXT:    movdqu %xmm0, (%rax)1104; SSE2-NEXT:    movdqu %xmm3, (%rax)1105; SSE2-NEXT:    movdqu %xmm2, (%rax)1106; SSE2-NEXT:    movdqu %xmm1, (%rax)1107; SSE2-NEXT:    retq1108;1109; AVX1-LABEL: avg_v64i8_const:1110; AVX1:       # %bb.0:1111; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1112; AVX1-NEXT:    # xmm0 = mem[0,0]1113; AVX1-NEXT:    vpavgb (%rdi), %xmm0, %xmm11114; AVX1-NEXT:    vpavgb 16(%rdi), %xmm0, %xmm21115; AVX1-NEXT:    vpavgb 32(%rdi), %xmm0, %xmm31116; AVX1-NEXT:    vpavgb 48(%rdi), %xmm0, %xmm01117; AVX1-NEXT:    vmovdqu %xmm0, (%rax)1118; AVX1-NEXT:    vmovdqu %xmm3, (%rax)1119; AVX1-NEXT:    vmovdqu %xmm2, (%rax)1120; AVX1-NEXT:    vmovdqu %xmm1, (%rax)1121; AVX1-NEXT:    retq1122;1123; AVX2-LABEL: avg_v64i8_const:1124; AVX2:       # %bb.0:1125; AVX2-NEXT:    vpbroadcastq {{.*#+}} ymm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1126; AVX2-NEXT:    vpavgb (%rdi), %ymm0, %ymm11127; AVX2-NEXT:    vpavgb 32(%rdi), %ymm0, %ymm01128; AVX2-NEXT:    vmovdqu %ymm0, (%rax)1129; AVX2-NEXT:    vmovdqu %ymm1, (%rax)1130; AVX2-NEXT:    vzeroupper1131; AVX2-NEXT:    retq1132;1133; AVX512F-LABEL: avg_v64i8_const:1134; AVX512F:       # %bb.0:1135; AVX512F-NEXT:    vpbroadcastq {{.*#+}} ymm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1136; AVX512F-NEXT:    vpavgb (%rdi), %ymm0, %ymm11137; AVX512F-NEXT:    vpavgb 32(%rdi), %ymm0, %ymm01138; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)1139; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)1140; AVX512F-NEXT:    vzeroupper1141; AVX512F-NEXT:    retq1142;1143; AVX512BW-LABEL: avg_v64i8_const:1144; AVX512BW:       # %bb.0:1145; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm01146; AVX512BW-NEXT:    vpavgb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm01147; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)1148; AVX512BW-NEXT:    vzeroupper1149; AVX512BW-NEXT:    retq1150  %1 = load <64 x i8>, ptr %a1151  %2 = zext <64 x i8> %1 to <64 x i32>1152  %3 = add nuw nsw <64 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1153  %4 = lshr <64 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1154  %5 = trunc <64 x i32> %4 to <64 x i8>1155  store <64 x i8> %5, ptr undef, align 41156  ret void1157}1158 1159define void @avg_v4i16_const(ptr %a) nounwind {1160; SSE2-LABEL: avg_v4i16_const:1161; SSE2:       # %bb.0:1162; SSE2-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero1163; SSE2-NEXT:    pavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm01164; SSE2-NEXT:    movq %xmm0, (%rax)1165; SSE2-NEXT:    retq1166;1167; AVX-LABEL: avg_v4i16_const:1168; AVX:       # %bb.0:1169; AVX-NEXT:    vmovq {{.*#+}} xmm0 = mem[0],zero1170; AVX-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm01171; AVX-NEXT:    vmovq %xmm0, (%rax)1172; AVX-NEXT:    retq1173  %1 = load <4 x i16>, ptr %a1174  %2 = zext <4 x i16> %1 to <4 x i32>1175  %3 = add nuw nsw <4 x i32> %2, <i32 1, i32 2, i32 3, i32 4>1176  %4 = lshr <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>1177  %5 = trunc <4 x i32> %4 to <4 x i16>1178  store <4 x i16> %5, ptr undef, align 41179  ret void1180}1181 1182define void @avg_v8i16_const(ptr %a) nounwind {1183; SSE2-LABEL: avg_v8i16_const:1184; SSE2:       # %bb.0:1185; SSE2-NEXT:    movdqa (%rdi), %xmm01186; SSE2-NEXT:    pavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm01187; SSE2-NEXT:    movdqu %xmm0, (%rax)1188; SSE2-NEXT:    retq1189;1190; AVX-LABEL: avg_v8i16_const:1191; AVX:       # %bb.0:1192; AVX-NEXT:    vmovdqa (%rdi), %xmm01193; AVX-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm01194; AVX-NEXT:    vmovdqu %xmm0, (%rax)1195; AVX-NEXT:    retq1196  %1 = load <8 x i16>, ptr %a1197  %2 = zext <8 x i16> %1 to <8 x i32>1198  %3 = add nuw nsw <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1199  %4 = lshr <8 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1200  %5 = trunc <8 x i32> %4 to <8 x i16>1201  store <8 x i16> %5, ptr undef, align 41202  ret void1203}1204 1205define void @avg_v16i16_const(ptr %a) nounwind {1206; SSE2-LABEL: avg_v16i16_const:1207; SSE2:       # %bb.0:1208; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7]1209; SSE2-NEXT:    movdqa (%rdi), %xmm11210; SSE2-NEXT:    pavgw %xmm0, %xmm11211; SSE2-NEXT:    pavgw 16(%rdi), %xmm01212; SSE2-NEXT:    movdqu %xmm0, (%rax)1213; SSE2-NEXT:    movdqu %xmm1, (%rax)1214; SSE2-NEXT:    retq1215;1216; AVX1-LABEL: avg_v16i16_const:1217; AVX1:       # %bb.0:1218; AVX1-NEXT:    vpmovsxbw {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7]1219; AVX1-NEXT:    vpavgw (%rdi), %xmm0, %xmm11220; AVX1-NEXT:    vpavgw 16(%rdi), %xmm0, %xmm01221; AVX1-NEXT:    vmovdqu %xmm0, (%rax)1222; AVX1-NEXT:    vmovdqu %xmm1, (%rax)1223; AVX1-NEXT:    retq1224;1225; AVX2-LABEL: avg_v16i16_const:1226; AVX2:       # %bb.0:1227; AVX2-NEXT:    vmovdqa (%rdi), %ymm01228; AVX2-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm01229; AVX2-NEXT:    vmovdqu %ymm0, (%rax)1230; AVX2-NEXT:    vzeroupper1231; AVX2-NEXT:    retq1232;1233; AVX512-LABEL: avg_v16i16_const:1234; AVX512:       # %bb.0:1235; AVX512-NEXT:    vmovdqa (%rdi), %ymm01236; AVX512-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm01237; AVX512-NEXT:    vmovdqu %ymm0, (%rax)1238; AVX512-NEXT:    vzeroupper1239; AVX512-NEXT:    retq1240  %1 = load <16 x i16>, ptr %a1241  %2 = zext <16 x i16> %1 to <16 x i32>1242  %3 = add nuw nsw <16 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1243  %4 = lshr <16 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1244  %5 = trunc <16 x i32> %4 to <16 x i16>1245  store <16 x i16> %5, ptr undef, align 41246  ret void1247}1248 1249define void @avg_v32i16_const(ptr %a) nounwind {1250; SSE2-LABEL: avg_v32i16_const:1251; SSE2:       # %bb.0:1252; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7]1253; SSE2-NEXT:    movdqa (%rdi), %xmm11254; SSE2-NEXT:    pavgw %xmm0, %xmm11255; SSE2-NEXT:    movdqa 16(%rdi), %xmm21256; SSE2-NEXT:    pavgw %xmm0, %xmm21257; SSE2-NEXT:    movdqa 32(%rdi), %xmm31258; SSE2-NEXT:    pavgw %xmm0, %xmm31259; SSE2-NEXT:    pavgw 48(%rdi), %xmm01260; SSE2-NEXT:    movdqu %xmm0, (%rax)1261; SSE2-NEXT:    movdqu %xmm3, (%rax)1262; SSE2-NEXT:    movdqu %xmm2, (%rax)1263; SSE2-NEXT:    movdqu %xmm1, (%rax)1264; SSE2-NEXT:    retq1265;1266; AVX1-LABEL: avg_v32i16_const:1267; AVX1:       # %bb.0:1268; AVX1-NEXT:    vpmovsxbw {{.*#+}} xmm0 = [0,1,2,3,4,5,6,7]1269; AVX1-NEXT:    vpavgw (%rdi), %xmm0, %xmm11270; AVX1-NEXT:    vpavgw 16(%rdi), %xmm0, %xmm21271; AVX1-NEXT:    vpavgw 32(%rdi), %xmm0, %xmm31272; AVX1-NEXT:    vpavgw 48(%rdi), %xmm0, %xmm01273; AVX1-NEXT:    vmovdqu %xmm0, (%rax)1274; AVX1-NEXT:    vmovdqu %xmm3, (%rax)1275; AVX1-NEXT:    vmovdqu %xmm2, (%rax)1276; AVX1-NEXT:    vmovdqu %xmm1, (%rax)1277; AVX1-NEXT:    retq1278;1279; AVX2-LABEL: avg_v32i16_const:1280; AVX2:       # %bb.0:1281; AVX2-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1282; AVX2-NEXT:    # ymm0 = mem[0,1,0,1]1283; AVX2-NEXT:    vpavgw (%rdi), %ymm0, %ymm11284; AVX2-NEXT:    vpavgw 32(%rdi), %ymm0, %ymm01285; AVX2-NEXT:    vmovdqu %ymm0, (%rax)1286; AVX2-NEXT:    vmovdqu %ymm1, (%rax)1287; AVX2-NEXT:    vzeroupper1288; AVX2-NEXT:    retq1289;1290; AVX512F-LABEL: avg_v32i16_const:1291; AVX512F:       # %bb.0:1292; AVX512F-NEXT:    vbroadcasti128 {{.*#+}} ymm0 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]1293; AVX512F-NEXT:    # ymm0 = mem[0,1,0,1]1294; AVX512F-NEXT:    vpavgw (%rdi), %ymm0, %ymm11295; AVX512F-NEXT:    vpavgw 32(%rdi), %ymm0, %ymm01296; AVX512F-NEXT:    vmovdqu %ymm0, (%rax)1297; AVX512F-NEXT:    vmovdqu %ymm1, (%rax)1298; AVX512F-NEXT:    vzeroupper1299; AVX512F-NEXT:    retq1300;1301; AVX512BW-LABEL: avg_v32i16_const:1302; AVX512BW:       # %bb.0:1303; AVX512BW-NEXT:    vmovdqa64 (%rdi), %zmm01304; AVX512BW-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm01305; AVX512BW-NEXT:    vmovdqu64 %zmm0, (%rax)1306; AVX512BW-NEXT:    vzeroupper1307; AVX512BW-NEXT:    retq1308  %1 = load <32 x i16>, ptr %a1309  %2 = zext <32 x i16> %1 to <32 x i32>1310  %3 = add nuw nsw <32 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>1311  %4 = lshr <32 x i32> %3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1312  %5 = trunc <32 x i32> %4 to <32 x i16>1313  store <32 x i16> %5, ptr undef, align 41314  ret void1315}1316 1317define <16 x i8> @avg_v16i8_3(<16 x i8> %a, <16 x i8> %b) nounwind {1318; SSE2-LABEL: avg_v16i8_3:1319; SSE2:       # %bb.0:1320; SSE2-NEXT:    pavgb %xmm1, %xmm01321; SSE2-NEXT:    retq1322;1323; AVX-LABEL: avg_v16i8_3:1324; AVX:       # %bb.0:1325; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm01326; AVX-NEXT:    retq1327  %za = zext <16 x i8> %a to <16 x i16>1328  %zb = zext <16 x i8> %b to <16 x i16>1329  %add = add nuw nsw <16 x i16> %za, %zb1330  %add1 = add nuw nsw <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1331  %lshr = lshr <16 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1332  %res = trunc <16 x i16> %lshr to <16 x i8>1333  ret <16 x i8> %res1334}1335 1336define <32 x i8> @avg_v32i8_3(<32 x i8> %a, <32 x i8> %b) nounwind {1337; SSE2-LABEL: avg_v32i8_3:1338; SSE2:       # %bb.0:1339; SSE2-NEXT:    pavgb %xmm2, %xmm01340; SSE2-NEXT:    pavgb %xmm3, %xmm11341; SSE2-NEXT:    retq1342;1343; AVX1-LABEL: avg_v32i8_3:1344; AVX1:       # %bb.0:1345; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm21346; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm31347; AVX1-NEXT:    vpavgb %xmm2, %xmm3, %xmm21348; AVX1-NEXT:    vpavgb %xmm1, %xmm0, %xmm01349; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm01350; AVX1-NEXT:    retq1351;1352; AVX2-LABEL: avg_v32i8_3:1353; AVX2:       # %bb.0:1354; AVX2-NEXT:    vpavgb %ymm1, %ymm0, %ymm01355; AVX2-NEXT:    retq1356;1357; AVX512-LABEL: avg_v32i8_3:1358; AVX512:       # %bb.0:1359; AVX512-NEXT:    vpavgb %ymm1, %ymm0, %ymm01360; AVX512-NEXT:    retq1361  %za = zext <32 x i8> %a to <32 x i16>1362  %zb = zext <32 x i8> %b to <32 x i16>1363  %add = add nuw nsw <32 x i16> %za, %zb1364  %add1 = add nuw nsw <32 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1365  %lshr = lshr <32 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1366  %res = trunc <32 x i16> %lshr to <32 x i8>1367  ret <32 x i8> %res1368}1369 1370define <64 x i8> @avg_v64i8_3(<64 x i8> %a, <64 x i8> %b) nounwind {1371; SSE2-LABEL: avg_v64i8_3:1372; SSE2:       # %bb.0:1373; SSE2-NEXT:    pavgb %xmm4, %xmm01374; SSE2-NEXT:    pavgb %xmm5, %xmm11375; SSE2-NEXT:    pavgb %xmm6, %xmm21376; SSE2-NEXT:    pavgb %xmm7, %xmm31377; SSE2-NEXT:    retq1378;1379; AVX1-LABEL: avg_v64i8_3:1380; AVX1:       # %bb.0:1381; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm41382; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm51383; AVX1-NEXT:    vpavgb %xmm4, %xmm5, %xmm41384; AVX1-NEXT:    vpavgb %xmm2, %xmm0, %xmm01385; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm0, %ymm01386; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm21387; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm41388; AVX1-NEXT:    vpavgb %xmm2, %xmm4, %xmm21389; AVX1-NEXT:    vpavgb %xmm3, %xmm1, %xmm11390; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm1, %ymm11391; AVX1-NEXT:    retq1392;1393; AVX2-LABEL: avg_v64i8_3:1394; AVX2:       # %bb.0:1395; AVX2-NEXT:    vpavgb %ymm2, %ymm0, %ymm01396; AVX2-NEXT:    vpavgb %ymm3, %ymm1, %ymm11397; AVX2-NEXT:    retq1398;1399; AVX512F-LABEL: avg_v64i8_3:1400; AVX512F:       # %bb.0:1401; AVX512F-NEXT:    vextracti64x4 $1, %zmm1, %ymm21402; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm31403; AVX512F-NEXT:    vpavgb %ymm2, %ymm3, %ymm21404; AVX512F-NEXT:    vpavgb %ymm1, %ymm0, %ymm01405; AVX512F-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm01406; AVX512F-NEXT:    retq1407;1408; AVX512BW-LABEL: avg_v64i8_3:1409; AVX512BW:       # %bb.0:1410; AVX512BW-NEXT:    vpavgb %zmm1, %zmm0, %zmm01411; AVX512BW-NEXT:    retq1412  %za = zext <64 x i8> %a to <64 x i16>1413  %zb = zext <64 x i8> %b to <64 x i16>1414  %add = add nuw nsw <64 x i16> %za, %zb1415  %add1 = add nuw nsw <64 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1416  %lshr = lshr <64 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1417  %res = trunc <64 x i16> %lshr to <64 x i8>1418  ret <64 x i8> %res1419}1420 1421define <512 x i8> @avg_v512i8_3(<512 x i8> %a, <512 x i8> %b) nounwind {1422; SSE2-LABEL: avg_v512i8_3:1423; SSE2:       # %bb.0:1424; SSE2-NEXT:    movq %rdi, %rax1425; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81426; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81427; SSE2-NEXT:    movdqa %xmm8, 496(%rdi)1428; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81429; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81430; SSE2-NEXT:    movdqa %xmm8, 480(%rdi)1431; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81432; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81433; SSE2-NEXT:    movdqa %xmm8, 464(%rdi)1434; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81435; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81436; SSE2-NEXT:    movdqa %xmm8, 448(%rdi)1437; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81438; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81439; SSE2-NEXT:    movdqa %xmm8, 432(%rdi)1440; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81441; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81442; SSE2-NEXT:    movdqa %xmm8, 416(%rdi)1443; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81444; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81445; SSE2-NEXT:    movdqa %xmm8, 400(%rdi)1446; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81447; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81448; SSE2-NEXT:    movdqa %xmm8, 384(%rdi)1449; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81450; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81451; SSE2-NEXT:    movdqa %xmm8, 368(%rdi)1452; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81453; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81454; SSE2-NEXT:    movdqa %xmm8, 352(%rdi)1455; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81456; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81457; SSE2-NEXT:    movdqa %xmm8, 336(%rdi)1458; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81459; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81460; SSE2-NEXT:    movdqa %xmm8, 320(%rdi)1461; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81462; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81463; SSE2-NEXT:    movdqa %xmm8, 304(%rdi)1464; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81465; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81466; SSE2-NEXT:    movdqa %xmm8, 288(%rdi)1467; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81468; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81469; SSE2-NEXT:    movdqa %xmm8, 272(%rdi)1470; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81471; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81472; SSE2-NEXT:    movdqa %xmm8, 256(%rdi)1473; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81474; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81475; SSE2-NEXT:    movdqa %xmm8, 240(%rdi)1476; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81477; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81478; SSE2-NEXT:    movdqa %xmm8, 224(%rdi)1479; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81480; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81481; SSE2-NEXT:    movdqa %xmm8, 208(%rdi)1482; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81483; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81484; SSE2-NEXT:    movdqa %xmm8, 192(%rdi)1485; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81486; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81487; SSE2-NEXT:    movdqa %xmm8, 176(%rdi)1488; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81489; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81490; SSE2-NEXT:    movdqa %xmm8, 160(%rdi)1491; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81492; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81493; SSE2-NEXT:    movdqa %xmm8, 144(%rdi)1494; SSE2-NEXT:    movdqa {{[0-9]+}}(%rsp), %xmm81495; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm81496; SSE2-NEXT:    movdqa %xmm8, 128(%rdi)1497; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm71498; SSE2-NEXT:    movdqa %xmm7, 112(%rdi)1499; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm61500; SSE2-NEXT:    movdqa %xmm6, 96(%rdi)1501; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm51502; SSE2-NEXT:    movdqa %xmm5, 80(%rdi)1503; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm41504; SSE2-NEXT:    movdqa %xmm4, 64(%rdi)1505; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm31506; SSE2-NEXT:    movdqa %xmm3, 48(%rdi)1507; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm21508; SSE2-NEXT:    movdqa %xmm2, 32(%rdi)1509; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm11510; SSE2-NEXT:    movdqa %xmm1, 16(%rdi)1511; SSE2-NEXT:    pavgb {{[0-9]+}}(%rsp), %xmm01512; SSE2-NEXT:    movdqa %xmm0, (%rdi)1513; SSE2-NEXT:    retq1514;1515; AVX1-LABEL: avg_v512i8_3:1516; AVX1:       # %bb.0:1517; AVX1-NEXT:    pushq %rbp1518; AVX1-NEXT:    movq %rsp, %rbp1519; AVX1-NEXT:    andq $-32, %rsp1520; AVX1-NEXT:    subq $32, %rsp1521; AVX1-NEXT:    movq %rdi, %rax1522; AVX1-NEXT:    vmovdqa 256(%rbp), %xmm81523; AVX1-NEXT:    vpavgb 768(%rbp), %xmm8, %xmm81524; AVX1-NEXT:    vmovdqa %xmm8, 496(%rdi)1525; AVX1-NEXT:    vmovdqa 240(%rbp), %xmm81526; AVX1-NEXT:    vpavgb 752(%rbp), %xmm8, %xmm81527; AVX1-NEXT:    vmovdqa %xmm8, 480(%rdi)1528; AVX1-NEXT:    vmovdqa 224(%rbp), %xmm81529; AVX1-NEXT:    vpavgb 736(%rbp), %xmm8, %xmm81530; AVX1-NEXT:    vmovdqa %xmm8, 464(%rdi)1531; AVX1-NEXT:    vmovdqa 208(%rbp), %xmm81532; AVX1-NEXT:    vpavgb 720(%rbp), %xmm8, %xmm81533; AVX1-NEXT:    vmovdqa %xmm8, 448(%rdi)1534; AVX1-NEXT:    vmovdqa 192(%rbp), %xmm81535; AVX1-NEXT:    vpavgb 704(%rbp), %xmm8, %xmm81536; AVX1-NEXT:    vmovdqa %xmm8, 432(%rdi)1537; AVX1-NEXT:    vmovdqa 176(%rbp), %xmm81538; AVX1-NEXT:    vpavgb 688(%rbp), %xmm8, %xmm81539; AVX1-NEXT:    vmovdqa %xmm8, 416(%rdi)1540; AVX1-NEXT:    vmovdqa 160(%rbp), %xmm81541; AVX1-NEXT:    vpavgb 672(%rbp), %xmm8, %xmm81542; AVX1-NEXT:    vmovdqa %xmm8, 400(%rdi)1543; AVX1-NEXT:    vmovdqa 144(%rbp), %xmm81544; AVX1-NEXT:    vpavgb 656(%rbp), %xmm8, %xmm81545; AVX1-NEXT:    vmovdqa %xmm8, 384(%rdi)1546; AVX1-NEXT:    vmovdqa 128(%rbp), %xmm81547; AVX1-NEXT:    vpavgb 640(%rbp), %xmm8, %xmm81548; AVX1-NEXT:    vmovdqa %xmm8, 368(%rdi)1549; AVX1-NEXT:    vmovdqa 112(%rbp), %xmm81550; AVX1-NEXT:    vpavgb 624(%rbp), %xmm8, %xmm81551; AVX1-NEXT:    vmovdqa %xmm8, 352(%rdi)1552; AVX1-NEXT:    vmovdqa 96(%rbp), %xmm81553; AVX1-NEXT:    vpavgb 608(%rbp), %xmm8, %xmm81554; AVX1-NEXT:    vmovdqa %xmm8, 336(%rdi)1555; AVX1-NEXT:    vmovdqa 80(%rbp), %xmm81556; AVX1-NEXT:    vpavgb 592(%rbp), %xmm8, %xmm81557; AVX1-NEXT:    vmovdqa %xmm8, 320(%rdi)1558; AVX1-NEXT:    vmovdqa 64(%rbp), %xmm81559; AVX1-NEXT:    vpavgb 576(%rbp), %xmm8, %xmm81560; AVX1-NEXT:    vmovdqa %xmm8, 304(%rdi)1561; AVX1-NEXT:    vmovdqa 48(%rbp), %xmm81562; AVX1-NEXT:    vpavgb 560(%rbp), %xmm8, %xmm81563; AVX1-NEXT:    vmovdqa %xmm8, 288(%rdi)1564; AVX1-NEXT:    vmovdqa 32(%rbp), %xmm81565; AVX1-NEXT:    vpavgb 544(%rbp), %xmm8, %xmm81566; AVX1-NEXT:    vmovdqa %xmm8, 272(%rdi)1567; AVX1-NEXT:    vmovdqa 16(%rbp), %xmm81568; AVX1-NEXT:    vpavgb 528(%rbp), %xmm8, %xmm81569; AVX1-NEXT:    vmovdqa %xmm8, 256(%rdi)1570; AVX1-NEXT:    vextractf128 $1, %ymm7, %xmm81571; AVX1-NEXT:    vpavgb 512(%rbp), %xmm8, %xmm81572; AVX1-NEXT:    vmovdqa %xmm8, 240(%rdi)1573; AVX1-NEXT:    vpavgb 496(%rbp), %xmm7, %xmm71574; AVX1-NEXT:    vmovdqa %xmm7, 224(%rdi)1575; AVX1-NEXT:    vextractf128 $1, %ymm6, %xmm71576; AVX1-NEXT:    vpavgb 480(%rbp), %xmm7, %xmm71577; AVX1-NEXT:    vmovdqa %xmm7, 208(%rdi)1578; AVX1-NEXT:    vpavgb 464(%rbp), %xmm6, %xmm61579; AVX1-NEXT:    vmovdqa %xmm6, 192(%rdi)1580; AVX1-NEXT:    vextractf128 $1, %ymm5, %xmm61581; AVX1-NEXT:    vpavgb 448(%rbp), %xmm6, %xmm61582; AVX1-NEXT:    vmovdqa %xmm6, 176(%rdi)1583; AVX1-NEXT:    vpavgb 432(%rbp), %xmm5, %xmm51584; AVX1-NEXT:    vmovdqa %xmm5, 160(%rdi)1585; AVX1-NEXT:    vextractf128 $1, %ymm4, %xmm51586; AVX1-NEXT:    vpavgb 416(%rbp), %xmm5, %xmm51587; AVX1-NEXT:    vmovdqa %xmm5, 144(%rdi)1588; AVX1-NEXT:    vpavgb 400(%rbp), %xmm4, %xmm41589; AVX1-NEXT:    vmovdqa %xmm4, 128(%rdi)1590; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm41591; AVX1-NEXT:    vpavgb 384(%rbp), %xmm4, %xmm41592; AVX1-NEXT:    vmovdqa %xmm4, 112(%rdi)1593; AVX1-NEXT:    vpavgb 368(%rbp), %xmm3, %xmm31594; AVX1-NEXT:    vmovdqa %xmm3, 96(%rdi)1595; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm31596; AVX1-NEXT:    vpavgb 352(%rbp), %xmm3, %xmm31597; AVX1-NEXT:    vmovdqa %xmm3, 80(%rdi)1598; AVX1-NEXT:    vpavgb 336(%rbp), %xmm2, %xmm21599; AVX1-NEXT:    vmovdqa %xmm2, 64(%rdi)1600; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm21601; AVX1-NEXT:    vpavgb 320(%rbp), %xmm2, %xmm21602; AVX1-NEXT:    vmovdqa %xmm2, 48(%rdi)1603; AVX1-NEXT:    vpavgb 304(%rbp), %xmm1, %xmm11604; AVX1-NEXT:    vmovdqa %xmm1, 32(%rdi)1605; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm11606; AVX1-NEXT:    vpavgb 288(%rbp), %xmm1, %xmm11607; AVX1-NEXT:    vmovdqa %xmm1, 16(%rdi)1608; AVX1-NEXT:    vpavgb 272(%rbp), %xmm0, %xmm01609; AVX1-NEXT:    vmovdqa %xmm0, (%rdi)1610; AVX1-NEXT:    movq %rbp, %rsp1611; AVX1-NEXT:    popq %rbp1612; AVX1-NEXT:    vzeroupper1613; AVX1-NEXT:    retq1614;1615; AVX2-LABEL: avg_v512i8_3:1616; AVX2:       # %bb.0:1617; AVX2-NEXT:    pushq %rbp1618; AVX2-NEXT:    movq %rsp, %rbp1619; AVX2-NEXT:    andq $-32, %rsp1620; AVX2-NEXT:    subq $32, %rsp1621; AVX2-NEXT:    movq %rdi, %rax1622; AVX2-NEXT:    vmovdqa 240(%rbp), %ymm81623; AVX2-NEXT:    vmovdqa 208(%rbp), %ymm91624; AVX2-NEXT:    vmovdqa 176(%rbp), %ymm101625; AVX2-NEXT:    vmovdqa 144(%rbp), %ymm111626; AVX2-NEXT:    vmovdqa 112(%rbp), %ymm121627; AVX2-NEXT:    vmovdqa 80(%rbp), %ymm131628; AVX2-NEXT:    vmovdqa 48(%rbp), %ymm141629; AVX2-NEXT:    vmovdqa 16(%rbp), %ymm151630; AVX2-NEXT:    vpavgb 272(%rbp), %ymm0, %ymm01631; AVX2-NEXT:    vpavgb 304(%rbp), %ymm1, %ymm11632; AVX2-NEXT:    vpavgb 336(%rbp), %ymm2, %ymm21633; AVX2-NEXT:    vpavgb 368(%rbp), %ymm3, %ymm31634; AVX2-NEXT:    vpavgb 400(%rbp), %ymm4, %ymm41635; AVX2-NEXT:    vpavgb 432(%rbp), %ymm5, %ymm51636; AVX2-NEXT:    vpavgb 464(%rbp), %ymm6, %ymm61637; AVX2-NEXT:    vpavgb 496(%rbp), %ymm7, %ymm71638; AVX2-NEXT:    vpavgb 528(%rbp), %ymm15, %ymm151639; AVX2-NEXT:    vpavgb 560(%rbp), %ymm14, %ymm141640; AVX2-NEXT:    vpavgb 592(%rbp), %ymm13, %ymm131641; AVX2-NEXT:    vpavgb 624(%rbp), %ymm12, %ymm121642; AVX2-NEXT:    vpavgb 656(%rbp), %ymm11, %ymm111643; AVX2-NEXT:    vpavgb 688(%rbp), %ymm10, %ymm101644; AVX2-NEXT:    vpavgb 720(%rbp), %ymm9, %ymm91645; AVX2-NEXT:    vpavgb 752(%rbp), %ymm8, %ymm81646; AVX2-NEXT:    vmovdqa %ymm8, 480(%rdi)1647; AVX2-NEXT:    vmovdqa %ymm9, 448(%rdi)1648; AVX2-NEXT:    vmovdqa %ymm10, 416(%rdi)1649; AVX2-NEXT:    vmovdqa %ymm11, 384(%rdi)1650; AVX2-NEXT:    vmovdqa %ymm12, 352(%rdi)1651; AVX2-NEXT:    vmovdqa %ymm13, 320(%rdi)1652; AVX2-NEXT:    vmovdqa %ymm14, 288(%rdi)1653; AVX2-NEXT:    vmovdqa %ymm15, 256(%rdi)1654; AVX2-NEXT:    vmovdqa %ymm7, 224(%rdi)1655; AVX2-NEXT:    vmovdqa %ymm6, 192(%rdi)1656; AVX2-NEXT:    vmovdqa %ymm5, 160(%rdi)1657; AVX2-NEXT:    vmovdqa %ymm4, 128(%rdi)1658; AVX2-NEXT:    vmovdqa %ymm3, 96(%rdi)1659; AVX2-NEXT:    vmovdqa %ymm2, 64(%rdi)1660; AVX2-NEXT:    vmovdqa %ymm1, 32(%rdi)1661; AVX2-NEXT:    vmovdqa %ymm0, (%rdi)1662; AVX2-NEXT:    movq %rbp, %rsp1663; AVX2-NEXT:    popq %rbp1664; AVX2-NEXT:    vzeroupper1665; AVX2-NEXT:    retq1666;1667; AVX512F-LABEL: avg_v512i8_3:1668; AVX512F:       # %bb.0:1669; AVX512F-NEXT:    pushq %rbp1670; AVX512F-NEXT:    movq %rsp, %rbp1671; AVX512F-NEXT:    andq $-64, %rsp1672; AVX512F-NEXT:    subq $64, %rsp1673; AVX512F-NEXT:    movq %rdi, %rax1674; AVX512F-NEXT:    vpavgb 16(%rbp), %ymm0, %ymm81675; AVX512F-NEXT:    vextracti64x4 $1, %zmm0, %ymm01676; AVX512F-NEXT:    vpavgb 48(%rbp), %ymm0, %ymm01677; AVX512F-NEXT:    vpavgb 80(%rbp), %ymm1, %ymm91678; AVX512F-NEXT:    vextracti64x4 $1, %zmm1, %ymm11679; AVX512F-NEXT:    vpavgb 112(%rbp), %ymm1, %ymm11680; AVX512F-NEXT:    vpavgb 144(%rbp), %ymm2, %ymm101681; AVX512F-NEXT:    vextracti64x4 $1, %zmm2, %ymm21682; AVX512F-NEXT:    vpavgb 176(%rbp), %ymm2, %ymm21683; AVX512F-NEXT:    vpavgb 208(%rbp), %ymm3, %ymm111684; AVX512F-NEXT:    vextracti64x4 $1, %zmm3, %ymm31685; AVX512F-NEXT:    vpavgb 240(%rbp), %ymm3, %ymm31686; AVX512F-NEXT:    vpavgb 272(%rbp), %ymm4, %ymm121687; AVX512F-NEXT:    vextracti64x4 $1, %zmm4, %ymm41688; AVX512F-NEXT:    vpavgb 304(%rbp), %ymm4, %ymm41689; AVX512F-NEXT:    vpavgb 336(%rbp), %ymm5, %ymm131690; AVX512F-NEXT:    vextracti64x4 $1, %zmm5, %ymm51691; AVX512F-NEXT:    vpavgb 368(%rbp), %ymm5, %ymm51692; AVX512F-NEXT:    vpavgb 400(%rbp), %ymm6, %ymm141693; AVX512F-NEXT:    vextracti64x4 $1, %zmm6, %ymm61694; AVX512F-NEXT:    vpavgb 432(%rbp), %ymm6, %ymm61695; AVX512F-NEXT:    vpavgb 464(%rbp), %ymm7, %ymm151696; AVX512F-NEXT:    vextracti64x4 $1, %zmm7, %ymm71697; AVX512F-NEXT:    vpavgb 496(%rbp), %ymm7, %ymm71698; AVX512F-NEXT:    vmovdqa %ymm7, 480(%rdi)1699; AVX512F-NEXT:    vmovdqa %ymm15, 448(%rdi)1700; AVX512F-NEXT:    vmovdqa %ymm6, 416(%rdi)1701; AVX512F-NEXT:    vmovdqa %ymm14, 384(%rdi)1702; AVX512F-NEXT:    vmovdqa %ymm5, 352(%rdi)1703; AVX512F-NEXT:    vmovdqa %ymm13, 320(%rdi)1704; AVX512F-NEXT:    vmovdqa %ymm4, 288(%rdi)1705; AVX512F-NEXT:    vmovdqa %ymm12, 256(%rdi)1706; AVX512F-NEXT:    vmovdqa %ymm3, 224(%rdi)1707; AVX512F-NEXT:    vmovdqa %ymm11, 192(%rdi)1708; AVX512F-NEXT:    vmovdqa %ymm2, 160(%rdi)1709; AVX512F-NEXT:    vmovdqa %ymm10, 128(%rdi)1710; AVX512F-NEXT:    vmovdqa %ymm1, 96(%rdi)1711; AVX512F-NEXT:    vmovdqa %ymm9, 64(%rdi)1712; AVX512F-NEXT:    vmovdqa %ymm0, 32(%rdi)1713; AVX512F-NEXT:    vmovdqa %ymm8, (%rdi)1714; AVX512F-NEXT:    movq %rbp, %rsp1715; AVX512F-NEXT:    popq %rbp1716; AVX512F-NEXT:    vzeroupper1717; AVX512F-NEXT:    retq1718;1719; AVX512BW-LABEL: avg_v512i8_3:1720; AVX512BW:       # %bb.0:1721; AVX512BW-NEXT:    pushq %rbp1722; AVX512BW-NEXT:    movq %rsp, %rbp1723; AVX512BW-NEXT:    andq $-64, %rsp1724; AVX512BW-NEXT:    subq $64, %rsp1725; AVX512BW-NEXT:    movq %rdi, %rax1726; AVX512BW-NEXT:    vpavgb 16(%rbp), %zmm0, %zmm01727; AVX512BW-NEXT:    vpavgb 80(%rbp), %zmm1, %zmm11728; AVX512BW-NEXT:    vpavgb 144(%rbp), %zmm2, %zmm21729; AVX512BW-NEXT:    vpavgb 208(%rbp), %zmm3, %zmm31730; AVX512BW-NEXT:    vpavgb 272(%rbp), %zmm4, %zmm41731; AVX512BW-NEXT:    vpavgb 336(%rbp), %zmm5, %zmm51732; AVX512BW-NEXT:    vpavgb 400(%rbp), %zmm6, %zmm61733; AVX512BW-NEXT:    vpavgb 464(%rbp), %zmm7, %zmm71734; AVX512BW-NEXT:    vmovdqa64 %zmm7, 448(%rdi)1735; AVX512BW-NEXT:    vmovdqa64 %zmm6, 384(%rdi)1736; AVX512BW-NEXT:    vmovdqa64 %zmm5, 320(%rdi)1737; AVX512BW-NEXT:    vmovdqa64 %zmm4, 256(%rdi)1738; AVX512BW-NEXT:    vmovdqa64 %zmm3, 192(%rdi)1739; AVX512BW-NEXT:    vmovdqa64 %zmm2, 128(%rdi)1740; AVX512BW-NEXT:    vmovdqa64 %zmm1, 64(%rdi)1741; AVX512BW-NEXT:    vmovdqa64 %zmm0, (%rdi)1742; AVX512BW-NEXT:    movq %rbp, %rsp1743; AVX512BW-NEXT:    popq %rbp1744; AVX512BW-NEXT:    vzeroupper1745; AVX512BW-NEXT:    retq1746  %za = zext <512 x i8> %a to <512 x i16>1747  %zb = zext <512 x i8> %b to <512 x i16>1748  %add = add nuw nsw <512 x i16> %za, %zb1749  %add1 = add nuw nsw <512 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1750  %lshr = lshr <512 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>1751  %res = trunc <512 x i16> %lshr to <512 x i8>1752  ret <512 x i8> %res1753}1754 1755; This is not an avgceilu, but its structurally similar and previously caused a crash1756; because the constants can't be read with APInt::getZExtValue.1757define void @not_avg_v16i8_wide_constants(ptr %a, ptr %b) nounwind {1758; SSE2-LABEL: not_avg_v16i8_wide_constants:1759; SSE2:       # %bb.0:1760; SSE2-NEXT:    movaps (%rdi), %xmm11761; SSE2-NEXT:    movdqa (%rsi), %xmm01762; SSE2-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)1763; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1764; SSE2-NEXT:    decl %eax1765; SSE2-NEXT:    movd %eax, %xmm21766; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1767; SSE2-NEXT:    decl %eax1768; SSE2-NEXT:    movd %eax, %xmm11769; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1770; SSE2-NEXT:    decl %eax1771; SSE2-NEXT:    movd %eax, %xmm31772; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1773; SSE2-NEXT:    decl %eax1774; SSE2-NEXT:    movd %eax, %xmm41775; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1776; SSE2-NEXT:    decl %eax1777; SSE2-NEXT:    movd %eax, %xmm51778; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1779; SSE2-NEXT:    decl %eax1780; SSE2-NEXT:    movd %eax, %xmm61781; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1782; SSE2-NEXT:    decl %eax1783; SSE2-NEXT:    movd %eax, %xmm71784; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1785; SSE2-NEXT:    decl %eax1786; SSE2-NEXT:    movd %eax, %xmm81787; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1788; SSE2-NEXT:    decl %eax1789; SSE2-NEXT:    movd %eax, %xmm101790; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1791; SSE2-NEXT:    decl %eax1792; SSE2-NEXT:    movd %eax, %xmm91793; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1794; SSE2-NEXT:    decl %eax1795; SSE2-NEXT:    movd %eax, %xmm111796; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1797; SSE2-NEXT:    decl %eax1798; SSE2-NEXT:    movd %eax, %xmm121799; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1800; SSE2-NEXT:    decl %eax1801; SSE2-NEXT:    movd %eax, %xmm131802; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1803; SSE2-NEXT:    decl %eax1804; SSE2-NEXT:    movd %eax, %xmm141805; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1806; SSE2-NEXT:    decl %eax1807; SSE2-NEXT:    movd %eax, %xmm151808; SSE2-NEXT:    movzbl -{{[0-9]+}}(%rsp), %eax1809; SSE2-NEXT:    decl %eax1810; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]1811; SSE2-NEXT:    movd %eax, %xmm21812; SSE2-NEXT:    punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]1813; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[0,0,0,0]1814; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]1815; SSE2-NEXT:    punpcklwd {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3]1816; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm6[0,0,0,0]1817; SSE2-NEXT:    punpcklwd {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3]1818; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm8[0,0,0,0]1819; SSE2-NEXT:    punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm3[2],xmm4[3],xmm3[3]1820; SSE2-NEXT:    movsd {{.*#+}} xmm4 = xmm1[0],xmm4[1]1821; SSE2-NEXT:    pxor %xmm3, %xmm31822; SSE2-NEXT:    movdqa %xmm0, %xmm11823; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7]1824; SSE2-NEXT:    movapd %xmm4, %xmm51825; SSE2-NEXT:    andpd %xmm1, %xmm51826; SSE2-NEXT:    xorpd %xmm4, %xmm11827; SSE2-NEXT:    psrlw $1, %xmm11828; SSE2-NEXT:    paddw %xmm5, %xmm11829; SSE2-NEXT:    punpcklwd {{.*#+}} xmm9 = xmm9[0],xmm10[0],xmm9[1],xmm10[1],xmm9[2],xmm10[2],xmm9[3],xmm10[3]1830; SSE2-NEXT:    punpcklwd {{.*#+}} xmm12 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]1831; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm12[0,0,0,0]1832; SSE2-NEXT:    punpckldq {{.*#+}} xmm9 = xmm9[0],xmm4[0],xmm9[1],xmm4[1]1833; SSE2-NEXT:    punpcklwd {{.*#+}} xmm14 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]1834; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm14[0,0,0,0]1835; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]1836; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]1837; SSE2-NEXT:    punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm4[2],xmm2[3],xmm4[3]1838; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm9[0],xmm2[1]1839; SSE2-NEXT:    punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm3[8],xmm0[9],xmm3[9],xmm0[10],xmm3[10],xmm0[11],xmm3[11],xmm0[12],xmm3[12],xmm0[13],xmm3[13],xmm0[14],xmm3[14],xmm0[15],xmm3[15]1840; SSE2-NEXT:    movapd %xmm2, %xmm31841; SSE2-NEXT:    andpd %xmm0, %xmm31842; SSE2-NEXT:    xorpd %xmm2, %xmm01843; SSE2-NEXT:    psrlw $1, %xmm01844; SSE2-NEXT:    paddw %xmm3, %xmm01845; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]1846; SSE2-NEXT:    pand %xmm2, %xmm01847; SSE2-NEXT:    pand %xmm2, %xmm11848; SSE2-NEXT:    packuswb %xmm0, %xmm11849; SSE2-NEXT:    movdqu %xmm1, (%rax)1850; SSE2-NEXT:    retq1851;1852; AVX1-LABEL: not_avg_v16i8_wide_constants:1853; AVX1:       # %bb.0:1854; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero1855; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero1856; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero1857; AVX1-NEXT:    vpmovzxbw {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero1858; AVX1-NEXT:    vpextrw $7, %xmm3, %edx1859; AVX1-NEXT:    vpextrw $6, %xmm3, %ecx1860; AVX1-NEXT:    vpextrw $5, %xmm3, %eax1861; AVX1-NEXT:    decl %edx1862; AVX1-NEXT:    vmovd %edx, %xmm41863; AVX1-NEXT:    vpextrw $4, %xmm3, %edx1864; AVX1-NEXT:    decl %ecx1865; AVX1-NEXT:    vmovd %ecx, %xmm51866; AVX1-NEXT:    vpextrw $1, %xmm3, %ecx1867; AVX1-NEXT:    decl %eax1868; AVX1-NEXT:    vmovd %eax, %xmm61869; AVX1-NEXT:    vpextrw $0, %xmm3, %eax1870; AVX1-NEXT:    decl %edx1871; AVX1-NEXT:    vmovd %edx, %xmm71872; AVX1-NEXT:    vpextrw $3, %xmm3, %edx1873; AVX1-NEXT:    decq %rcx1874; AVX1-NEXT:    vmovq %rcx, %xmm81875; AVX1-NEXT:    vpextrw $2, %xmm3, %ecx1876; AVX1-NEXT:    decq %rax1877; AVX1-NEXT:    vmovq %rax, %xmm31878; AVX1-NEXT:    vpextrw $7, %xmm2, %eax1879; AVX1-NEXT:    decl %edx1880; AVX1-NEXT:    vmovd %edx, %xmm91881; AVX1-NEXT:    vpextrw $6, %xmm2, %edx1882; AVX1-NEXT:    decl %ecx1883; AVX1-NEXT:    vmovd %ecx, %xmm101884; AVX1-NEXT:    vpextrw $5, %xmm2, %ecx1885; AVX1-NEXT:    decl %eax1886; AVX1-NEXT:    vmovd %eax, %xmm111887; AVX1-NEXT:    vpextrw $4, %xmm2, %eax1888; AVX1-NEXT:    decl %edx1889; AVX1-NEXT:    vmovd %edx, %xmm121890; AVX1-NEXT:    vpextrw $1, %xmm2, %edx1891; AVX1-NEXT:    decl %ecx1892; AVX1-NEXT:    vmovd %ecx, %xmm131893; AVX1-NEXT:    vpextrw $0, %xmm2, %ecx1894; AVX1-NEXT:    decl %eax1895; AVX1-NEXT:    vmovd %eax, %xmm141896; AVX1-NEXT:    vpextrw $3, %xmm2, %eax1897; AVX1-NEXT:    decq %rdx1898; AVX1-NEXT:    vmovq %rdx, %xmm151899; AVX1-NEXT:    vpextrw $2, %xmm2, %edx1900; AVX1-NEXT:    decq %rcx1901; AVX1-NEXT:    vmovq %rcx, %xmm21902; AVX1-NEXT:    decl %eax1903; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3]1904; AVX1-NEXT:    vmovd %eax, %xmm51905; AVX1-NEXT:    decl %edx1906; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3]1907; AVX1-NEXT:    vmovd %edx, %xmm71908; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]1909; AVX1-NEXT:    vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]1910; AVX1-NEXT:    vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]1911; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm8[0],xmm3[1],xmm8[1],xmm3[2],xmm8[2],xmm3[3],xmm8[3]1912; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm6 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3]1913; AVX1-NEXT:    vpshufd {{.*#+}} xmm6 = xmm6[0,0,1,1]1914; AVX1-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm6[2,3],xmm3[4,5,6,7]1915; AVX1-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm4[4,5,6,7]1916; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm4 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3]1917; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm6 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3]1918; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]1919; AVX1-NEXT:    vpshufd {{.*#+}} xmm6 = xmm6[0,1,0,1]1920; AVX1-NEXT:    vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3,4,5],xmm4[6,7]1921; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm15[0],xmm2[1],xmm15[1],xmm2[2],xmm15[2],xmm2[3],xmm15[3]1922; AVX1-NEXT:    vpunpcklwd {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]1923; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm5[0,0,1,1]1924; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5,6,7]1925; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm4[4,5,6,7]1926; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm21927; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm01928; AVX1-NEXT:    vandps %ymm0, %ymm2, %ymm11929; AVX1-NEXT:    vxorps %ymm0, %ymm2, %ymm01930; AVX1-NEXT:    vpsrlw $1, %xmm0, %xmm21931; AVX1-NEXT:    vpaddw %xmm2, %xmm1, %xmm21932; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm11933; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm01934; AVX1-NEXT:    vpsrlw $1, %xmm0, %xmm01935; AVX1-NEXT:    vpaddw %xmm0, %xmm1, %xmm01936; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]1937; AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm01938; AVX1-NEXT:    vpand %xmm1, %xmm2, %xmm11939; AVX1-NEXT:    vpackuswb %xmm0, %xmm1, %xmm01940; AVX1-NEXT:    vmovdqu %xmm0, (%rax)1941; AVX1-NEXT:    vzeroupper1942; AVX1-NEXT:    retq1943;1944; AVX2-LABEL: not_avg_v16i8_wide_constants:1945; AVX2:       # %bb.0:1946; AVX2-NEXT:    vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1947; AVX2-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1948; AVX2-NEXT:    vpaddw %ymm1, %ymm0, %ymm01949; AVX2-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm11950; AVX2-NEXT:    vpaddw %ymm1, %ymm0, %ymm01951; AVX2-NEXT:    vpsrlw $1, %ymm0, %ymm01952; AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm01953; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm11954; AVX2-NEXT:    vpackuswb %xmm1, %xmm0, %xmm01955; AVX2-NEXT:    vmovdqu %xmm0, (%rax)1956; AVX2-NEXT:    vzeroupper1957; AVX2-NEXT:    retq1958;1959; AVX512F-LABEL: not_avg_v16i8_wide_constants:1960; AVX512F:       # %bb.0:1961; AVX512F-NEXT:    vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1962; AVX512F-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1963; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm01964; AVX512F-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm11965; AVX512F-NEXT:    vpaddw %ymm1, %ymm0, %ymm01966; AVX512F-NEXT:    vpsrlw $1, %ymm0, %ymm01967; AVX512F-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero1968; AVX512F-NEXT:    vpmovdb %zmm0, (%rax)1969; AVX512F-NEXT:    vzeroupper1970; AVX512F-NEXT:    retq1971;1972; AVX512BW-LABEL: not_avg_v16i8_wide_constants:1973; AVX512BW:       # %bb.0:1974; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1975; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero1976; AVX512BW-NEXT:    vpaddw %ymm1, %ymm0, %ymm01977; AVX512BW-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm11978; AVX512BW-NEXT:    vpaddw %ymm1, %ymm0, %ymm01979; AVX512BW-NEXT:    vpsrlw $1, %ymm0, %ymm01980; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm01981; AVX512BW-NEXT:    vmovdqu %xmm0, (%rax)1982; AVX512BW-NEXT:    vzeroupper1983; AVX512BW-NEXT:    retq1984  %1 = load <16 x i8>, ptr %a1985  %2 = load <16 x i8>, ptr %b1986  %3 = zext <16 x i8> %1 to <16 x i128>1987  %4 = zext <16 x i8> %2 to <16 x i128>1988  %5 = add <16 x i128> %3, <i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1, i128 -1>1989  %6 = add <16 x i128> %5, %41990  %7 = lshr <16 x i128> %6, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>1991  %8 = trunc <16 x i128> %7 to <16 x i8>1992  store <16 x i8> %8, ptr undef, align 41993  ret void1994}1995 1996; Make sure we don't fail on single element vectors.1997define <1 x i8> @avg_v1i8(<1 x i8> %x, <1 x i8> %y) {1998; CHECK-LABEL: avg_v1i8:1999; CHECK:       # %bb.0:2000; CHECK-NEXT:    movzbl %sil, %eax2001; CHECK-NEXT:    movzbl %dil, %ecx2002; CHECK-NEXT:    leal 1(%rcx,%rax), %eax2003; CHECK-NEXT:    shrl %eax2004; CHECK-NEXT:    # kill: def $al killed $al killed $eax2005; CHECK-NEXT:    retq2006  %a = zext <1 x i8> %x to <1 x i16>2007  %b = zext <1 x i8> %y to <1 x i16>2008  %c = add <1 x i16> %a, %b2009  %d = add <1 x i16> %c, <i16 1>2010  %e = lshr <1 x i16> %d, <i16 1>2011  %f = trunc <1 x i16> %e to <1 x i8>2012  ret <1 x i8> %f2013}2014 2015; _mm_avg_epu16( _mm_slli_epi16(a, 2), _mm_slli_epi16(b, 2))2016define <2 x i64> @PR41316(<2 x i64>, <2 x i64>) {2017; SSE2-LABEL: PR41316:2018; SSE2:       # %bb.0:2019; SSE2-NEXT:    psllw $2, %xmm02020; SSE2-NEXT:    psllw $2, %xmm12021; SSE2-NEXT:    pavgw %xmm1, %xmm02022; SSE2-NEXT:    retq2023;2024; AVX-LABEL: PR41316:2025; AVX:       # %bb.0:2026; AVX-NEXT:    vpsllw $2, %xmm0, %xmm02027; AVX-NEXT:    vpsllw $2, %xmm1, %xmm12028; AVX-NEXT:    vpavgw %xmm0, %xmm1, %xmm02029; AVX-NEXT:    retq2030  %3 = bitcast <2 x i64> %0 to <8 x i16>2031  %4 = shl <8 x i16> %3, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>2032  %5 = bitcast <2 x i64> %1 to <8 x i16>2033  %6 = shl <8 x i16> %5, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>2034  %7 = zext <8 x i16> %6 to <8 x i32>2035  %8 = or <8 x i16> %4, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2036  %9 = zext <8 x i16> %8 to <8 x i32>2037  %10 = add nuw nsw <8 x i32> %9, %72038  %11 = lshr <8 x i32> %10, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2039  %12 = trunc <8 x i32> %11 to <8 x i16>2040  %13 = bitcast <8 x i16> %12 to <2 x i64>2041  ret <2 x i64> %132042}2043 2044; shuffle(avg(shuffle(),shuffle())) -> avg(shuffle(),shuffle())2045define  <16 x i8> @fold_avgb_shuffles(<16 x i8> %x, <16 x i8> %y) {2046; SSE2-LABEL: fold_avgb_shuffles:2047; SSE2:       # %bb.0: # %entry2048; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]2049; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]2050; SSE2-NEXT:    pavgb %xmm1, %xmm02051; SSE2-NEXT:    retq2052;2053; AVX-LABEL: fold_avgb_shuffles:2054; AVX:       # %bb.0: # %entry2055; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]2056; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]2057; AVX-NEXT:    vpavgb %xmm1, %xmm0, %xmm02058; AVX-NEXT:    retq2059entry:2060   %0 = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>2061   %1 = shufflevector <16 x i8> %y, <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>2062   %2 = tail call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %0, <16 x i8> %1)2063   %3 = shufflevector <16 x i8> %2, <16 x i8> poison, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>2064   ret <16 x i8> %32065}2066declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>)2067 2068define <8 x i16> @fold_avgw_shuffles(<8 x i16> %x, <8 x i16> %y) {2069; SSE2-LABEL: fold_avgw_shuffles:2070; SSE2:       # %bb.0: # %entry2071; SSE2-NEXT:    pavgw %xmm1, %xmm02072; SSE2-NEXT:    retq2073;2074; AVX-LABEL: fold_avgw_shuffles:2075; AVX:       # %bb.0: # %entry2076; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm02077; AVX-NEXT:    retq2078entry:2079   %0 = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>2080   %1 = shufflevector <8 x i16> %y, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>2081   %2 = tail call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %0, <8 x i16> %1)2082   %3 = shufflevector <8 x i16> %2, <8 x i16> poison, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 2, i32 3, i32 0, i32 1>2083   ret <8 x i16> %32084}2085declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>)2086 2087define <8 x i16> @PR52131_pavg_chain(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {2088; SSE2-LABEL: PR52131_pavg_chain:2089; SSE2:       # %bb.0:2090; SSE2-NEXT:    pavgw %xmm1, %xmm02091; SSE2-NEXT:    pavgw %xmm2, %xmm02092; SSE2-NEXT:    retq2093;2094; AVX-LABEL: PR52131_pavg_chain:2095; AVX:       # %bb.0:2096; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm02097; AVX-NEXT:    vpavgw %xmm0, %xmm2, %xmm02098; AVX-NEXT:    retq2099  %i = zext <8 x i16> %a to <8 x i32>2100  %i1 = zext <8 x i16> %b to <8 x i32>2101  %i2 = add nuw nsw <8 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2102  %i3 = add nuw nsw <8 x i32> %i2, %i12103  %i4 = lshr <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2104  %i5 = and <8 x i32> %i4, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>2105  %i6 = zext <8 x i16> %c to <8 x i32>2106  %i7 = add nuw nsw <8 x i32> %i6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2107  %i8 = add nuw nsw <8 x i32> %i7, %i52108  %i9 = lshr <8 x i32> %i8, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2109  %i10 = trunc <8 x i32> %i9 to <8 x i16>2110  ret <8 x i16> %i102111}2112 2113define <8 x i16> @PR52131_pavg_chainlike_but_not_zext(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {2114; SSE2-LABEL: PR52131_pavg_chainlike_but_not_zext:2115; SSE2:       # %bb.0:2116; SSE2-NEXT:    pavgw %xmm1, %xmm02117; SSE2-NEXT:    pavgw %xmm2, %xmm02118; SSE2-NEXT:    retq2119;2120; AVX-LABEL: PR52131_pavg_chainlike_but_not_zext:2121; AVX:       # %bb.0:2122; AVX-NEXT:    vpavgw %xmm1, %xmm0, %xmm02123; AVX-NEXT:    vpavgw %xmm0, %xmm2, %xmm02124; AVX-NEXT:    retq2125  %i = zext <8 x i16> %a to <8 x i32>2126  %i1 = zext <8 x i16> %b to <8 x i32>2127  %i2 = add nuw nsw <8 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2128  %i3 = add nuw nsw <8 x i32> %i2, %i12129  %i4 = lshr <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2130  %i5 = and <8 x i32> %i4, <i32 131071, i32 131071, i32 131071, i32 131071, i32 131071, i32 131071, i32 131071, i32 131071>2131  %i6 = zext <8 x i16> %c to <8 x i32>2132  %i7 = add nuw nsw <8 x i32> %i6, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2133  %i8 = add nuw nsw <8 x i32> %i7, %i52134  %i9 = lshr <8 x i32> %i8, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2135  %i10 = trunc <8 x i32> %i9 to <8 x i16>2136  ret <8 x i16> %i102137}2138 2139define <8 x i16> @PR52131_pavg_with_mask(<8 x i32> %a, <8 x i16> %b) {2140; SSE2-LABEL: PR52131_pavg_with_mask:2141; SSE2:       # %bb.0:2142; SSE2-NEXT:    pslld $16, %xmm12143; SSE2-NEXT:    psrad $16, %xmm12144; SSE2-NEXT:    pslld $16, %xmm02145; SSE2-NEXT:    psrad $16, %xmm02146; SSE2-NEXT:    packssdw %xmm1, %xmm02147; SSE2-NEXT:    pavgw %xmm2, %xmm02148; SSE2-NEXT:    retq2149;2150; AVX1-LABEL: PR52131_pavg_with_mask:2151; AVX1:       # %bb.0:2152; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm02153; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm22154; AVX1-NEXT:    vpackusdw %xmm2, %xmm0, %xmm02155; AVX1-NEXT:    vpavgw %xmm0, %xmm1, %xmm02156; AVX1-NEXT:    vzeroupper2157; AVX1-NEXT:    retq2158;2159; AVX2-LABEL: PR52131_pavg_with_mask:2160; AVX2:       # %bb.0:2161; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]2162; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]2163; AVX2-NEXT:    vpavgw %xmm0, %xmm1, %xmm02164; AVX2-NEXT:    vzeroupper2165; AVX2-NEXT:    retq2166;2167; AVX512-LABEL: PR52131_pavg_with_mask:2168; AVX512:       # %bb.0:2169; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm02170; AVX512-NEXT:    vpmovdw %zmm0, %ymm02171; AVX512-NEXT:    vpavgw %xmm0, %xmm1, %xmm02172; AVX512-NEXT:    vzeroupper2173; AVX512-NEXT:    retq2174  %i = and <8 x i32> %a, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>2175  %i3 = zext <8 x i16> %b to <8 x i32>2176  %i4 = add nuw nsw <8 x i32> %i3, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2177  %i5 = add nuw nsw <8 x i32> %i4, %i2178  %i6 = lshr <8 x i32> %i5, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2179  %i7 = trunc <8 x i32> %i6 to <8 x i16>2180  ret <8 x i16> %i72181}2182 2183define <8 x i16> @PR52131_not_zext_with_constant(<8 x i32> %a) {2184; SSE2-LABEL: PR52131_not_zext_with_constant:2185; SSE2:       # %bb.0:2186; SSE2-NEXT:    pslld $16, %xmm12187; SSE2-NEXT:    psrad $16, %xmm12188; SSE2-NEXT:    pslld $16, %xmm02189; SSE2-NEXT:    psrad $16, %xmm02190; SSE2-NEXT:    packssdw %xmm1, %xmm02191; SSE2-NEXT:    pavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm02192; SSE2-NEXT:    retq2193;2194; AVX1-LABEL: PR52131_not_zext_with_constant:2195; AVX1:       # %bb.0:2196; AVX1-NEXT:    vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm02197; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm12198; AVX1-NEXT:    vpackusdw %xmm1, %xmm0, %xmm02199; AVX1-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm02200; AVX1-NEXT:    vzeroupper2201; AVX1-NEXT:    retq2202;2203; AVX2-LABEL: PR52131_not_zext_with_constant:2204; AVX2:       # %bb.0:2205; AVX2-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]2206; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]2207; AVX2-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm02208; AVX2-NEXT:    vzeroupper2209; AVX2-NEXT:    retq2210;2211; AVX512-LABEL: PR52131_not_zext_with_constant:2212; AVX512:       # %bb.0:2213; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm02214; AVX512-NEXT:    vpmovdw %zmm0, %ymm02215; AVX512-NEXT:    vpavgw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm02216; AVX512-NEXT:    vzeroupper2217; AVX512-NEXT:    retq2218  %i = and <8 x i32> %a, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>2219  %i1 = add nuw nsw <8 x i32> %i, <i32 43, i32 43, i32 43, i32 43, i32 43, i32 43, i32 43, i32 43>2220  %i2 = lshr <8 x i32> %i1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2221  %i3 = trunc <8 x i32> %i2 to <8 x i16>2222  ret <8 x i16> %i32223}2224 2225define i64 @PR95284(i32 %a0) {2226; CHECK-LABEL: PR95284:2227; CHECK:       # %bb.0:2228; CHECK-NEXT:    movl %edi, %eax2229; CHECK-NEXT:    decq %rax2230; CHECK-NEXT:    shrq %rax2231; CHECK-NEXT:    incq %rax2232; CHECK-NEXT:    andq $-2, %rax2233; CHECK-NEXT:    retq2234  %ext = zext nneg i32 %a0 to i642235  %dec = add i64 %ext, -12236  %srl = lshr i64 %dec, 12237  %inc = add nuw nsw i64 %srl, 12238  %res = and i64 %inc, 92233720368547758062239  ret i64 %res2240}2241