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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE44; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX15; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX26; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5127 8;9; 128-bit vectors10;11 12define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind {13; SSE-LABEL: test_fixed_v16i8:14; SSE: # %bb.0:15; SSE-NEXT: pavgb %xmm1, %xmm016; SSE-NEXT: retq17;18; AVX-LABEL: test_fixed_v16i8:19; AVX: # %bb.0:20; AVX-NEXT: vpavgb %xmm1, %xmm0, %xmm021; AVX-NEXT: retq22 %or = or <16 x i8> %a0, %a123 %xor = xor <16 x i8> %a0, %a124 %shift = lshr <16 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>25 %res = sub <16 x i8> %or, %shift26 ret <16 x i8> %res27}28 29define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind {30; SSE-LABEL: test_ext_v16i8:31; SSE: # %bb.0:32; SSE-NEXT: pavgb %xmm1, %xmm033; SSE-NEXT: retq34;35; AVX-LABEL: test_ext_v16i8:36; AVX: # %bb.0:37; AVX-NEXT: vpavgb %xmm1, %xmm0, %xmm038; AVX-NEXT: retq39 %x0 = zext <16 x i8> %a0 to <16 x i16>40 %x1 = zext <16 x i8> %a1 to <16 x i16>41 %sum = add <16 x i16> %x0, %x142 %inc = add <16 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>43 %shift = lshr <16 x i16> %inc, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>44 %res = trunc <16 x i16> %shift to <16 x i8>45 ret <16 x i8> %res46}47 48define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind {49; SSE-LABEL: test_fixed_v8i16:50; SSE: # %bb.0:51; SSE-NEXT: pavgw %xmm1, %xmm052; SSE-NEXT: retq53;54; AVX-LABEL: test_fixed_v8i16:55; AVX: # %bb.0:56; AVX-NEXT: vpavgw %xmm1, %xmm0, %xmm057; AVX-NEXT: retq58 %or = or <8 x i16> %a0, %a159 %xor = xor <8 x i16> %a1, %a060 %shift = lshr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>61 %res = sub <8 x i16> %or, %shift62 ret <8 x i16> %res63}64 65define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind {66; SSE-LABEL: test_ext_v8i16:67; SSE: # %bb.0:68; SSE-NEXT: pavgw %xmm1, %xmm069; SSE-NEXT: retq70;71; AVX-LABEL: test_ext_v8i16:72; AVX: # %bb.0:73; AVX-NEXT: vpavgw %xmm1, %xmm0, %xmm074; AVX-NEXT: retq75 %x0 = zext <8 x i16> %a0 to <8 x i32>76 %x1 = zext <8 x i16> %a1 to <8 x i32>77 %sum = add <8 x i32> %x0, %x178 %inc = add <8 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>79 %shift = lshr <8 x i32> %inc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>80 %res = trunc <8 x i32> %shift to <8 x i16>81 ret <8 x i16> %res82}83 84define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {85; SSE-LABEL: test_fixed_v4i32:86; SSE: # %bb.0:87; SSE-NEXT: movdqa %xmm0, %xmm288; SSE-NEXT: por %xmm1, %xmm289; SSE-NEXT: pxor %xmm1, %xmm090; SSE-NEXT: psrld $1, %xmm091; SSE-NEXT: psubd %xmm0, %xmm292; SSE-NEXT: movdqa %xmm2, %xmm093; SSE-NEXT: retq94;95; AVX-LABEL: test_fixed_v4i32:96; AVX: # %bb.0:97; AVX-NEXT: vpor %xmm1, %xmm0, %xmm298; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm099; AVX-NEXT: vpsrld $1, %xmm0, %xmm0100; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0101; AVX-NEXT: retq102 %or = or <4 x i32> %a0, %a1103 %xor = xor <4 x i32> %a1, %a0104 %shift = lshr <4 x i32> %xor, <i32 1, i32 1, i32 1, i32 1>105 %res = sub <4 x i32> %or, %shift106 ret <4 x i32> %res107}108 109define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {110; SSE-LABEL: test_ext_v4i32:111; SSE: # %bb.0:112; SSE-NEXT: movdqa %xmm0, %xmm2113; SSE-NEXT: por %xmm1, %xmm2114; SSE-NEXT: pxor %xmm1, %xmm0115; SSE-NEXT: psrld $1, %xmm0116; SSE-NEXT: psubd %xmm0, %xmm2117; SSE-NEXT: movdqa %xmm2, %xmm0118; SSE-NEXT: retq119;120; AVX-LABEL: test_ext_v4i32:121; AVX: # %bb.0:122; AVX-NEXT: vpor %xmm1, %xmm0, %xmm2123; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0124; AVX-NEXT: vpsrld $1, %xmm0, %xmm0125; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0126; AVX-NEXT: retq127 %x0 = zext <4 x i32> %a0 to <4 x i64>128 %x1 = zext <4 x i32> %a1 to <4 x i64>129 %sum = add <4 x i64> %x0, %x1130 %inc = add <4 x i64> %sum, <i64 1, i64 1, i64 1, i64 1>131 %shift = lshr <4 x i64> %inc, <i64 1, i64 1, i64 1, i64 1>132 %res = trunc <4 x i64> %shift to <4 x i32>133 ret <4 x i32> %res134}135 136define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind {137; SSE-LABEL: test_fixed_v2i64:138; SSE: # %bb.0:139; SSE-NEXT: movdqa %xmm0, %xmm2140; SSE-NEXT: por %xmm1, %xmm2141; SSE-NEXT: pxor %xmm1, %xmm0142; SSE-NEXT: psrlq $1, %xmm0143; SSE-NEXT: psubq %xmm0, %xmm2144; SSE-NEXT: movdqa %xmm2, %xmm0145; SSE-NEXT: retq146;147; AVX-LABEL: test_fixed_v2i64:148; AVX: # %bb.0:149; AVX-NEXT: vpor %xmm1, %xmm0, %xmm2150; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0151; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0152; AVX-NEXT: vpsubq %xmm0, %xmm2, %xmm0153; AVX-NEXT: retq154 %or = or <2 x i64> %a0, %a1155 %xor = xor <2 x i64> %a1, %a0156 %shift = lshr <2 x i64> %xor, <i64 1, i64 1>157 %res = sub <2 x i64> %or, %shift158 ret <2 x i64> %res159}160 161define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind {162; SSE-LABEL: test_ext_v2i64:163; SSE: # %bb.0:164; SSE-NEXT: movdqa %xmm0, %xmm2165; SSE-NEXT: por %xmm1, %xmm2166; SSE-NEXT: pxor %xmm1, %xmm0167; SSE-NEXT: psrlq $1, %xmm0168; SSE-NEXT: psubq %xmm0, %xmm2169; SSE-NEXT: movdqa %xmm2, %xmm0170; SSE-NEXT: retq171;172; AVX-LABEL: test_ext_v2i64:173; AVX: # %bb.0:174; AVX-NEXT: vpor %xmm1, %xmm0, %xmm2175; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0176; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0177; AVX-NEXT: vpsubq %xmm0, %xmm2, %xmm0178; AVX-NEXT: retq179 %x0 = zext <2 x i64> %a0 to <2 x i128>180 %x1 = zext <2 x i64> %a1 to <2 x i128>181 %sum = add <2 x i128> %x0, %x1182 %inc = add <2 x i128> %sum, <i128 1, i128 1>183 %shift = lshr <2 x i128> %inc, <i128 1, i128 1>184 %res = trunc <2 x i128> %shift to <2 x i64>185 ret <2 x i64> %res186}187 188;189; 256-bit vectors190;191 192define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind {193; SSE-LABEL: test_fixed_v32i8:194; SSE: # %bb.0:195; SSE-NEXT: pavgb %xmm2, %xmm0196; SSE-NEXT: pavgb %xmm3, %xmm1197; SSE-NEXT: retq198;199; AVX1-LABEL: test_fixed_v32i8:200; AVX1: # %bb.0:201; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2202; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3203; AVX1-NEXT: vpavgb %xmm2, %xmm3, %xmm2204; AVX1-NEXT: vpavgb %xmm1, %xmm0, %xmm0205; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0206; AVX1-NEXT: retq207;208; AVX2-LABEL: test_fixed_v32i8:209; AVX2: # %bb.0:210; AVX2-NEXT: vpavgb %ymm1, %ymm0, %ymm0211; AVX2-NEXT: retq212;213; AVX512-LABEL: test_fixed_v32i8:214; AVX512: # %bb.0:215; AVX512-NEXT: vpavgb %ymm1, %ymm0, %ymm0216; AVX512-NEXT: retq217 %or = or <32 x i8> %a0, %a1218 %xor = xor <32 x i8> %a0, %a1219 %shift = lshr <32 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>220 %res = sub <32 x i8> %or, %shift221 ret <32 x i8> %res222}223 224define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind {225; SSE-LABEL: test_ext_v32i8:226; SSE: # %bb.0:227; SSE-NEXT: pavgb %xmm2, %xmm0228; SSE-NEXT: pavgb %xmm3, %xmm1229; SSE-NEXT: retq230;231; AVX1-LABEL: test_ext_v32i8:232; AVX1: # %bb.0:233; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2234; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3235; AVX1-NEXT: vpavgb %xmm2, %xmm3, %xmm2236; AVX1-NEXT: vpavgb %xmm1, %xmm0, %xmm0237; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0238; AVX1-NEXT: retq239;240; AVX2-LABEL: test_ext_v32i8:241; AVX2: # %bb.0:242; AVX2-NEXT: vpavgb %ymm1, %ymm0, %ymm0243; AVX2-NEXT: retq244;245; AVX512-LABEL: test_ext_v32i8:246; AVX512: # %bb.0:247; AVX512-NEXT: vpavgb %ymm1, %ymm0, %ymm0248; AVX512-NEXT: retq249 %x0 = zext <32 x i8> %a0 to <32 x i16>250 %x1 = zext <32 x i8> %a1 to <32 x i16>251 %sum = add <32 x i16> %x0, %x1252 %inc = add <32 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>253 %shift = lshr <32 x i16> %inc, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>254 %res = trunc <32 x i16> %shift to <32 x i8>255 ret <32 x i8> %res256}257 258define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind {259; SSE-LABEL: test_fixed_v16i16:260; SSE: # %bb.0:261; SSE-NEXT: pavgw %xmm2, %xmm0262; SSE-NEXT: pavgw %xmm3, %xmm1263; SSE-NEXT: retq264;265; AVX1-LABEL: test_fixed_v16i16:266; AVX1: # %bb.0:267; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2268; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3269; AVX1-NEXT: vpavgw %xmm2, %xmm3, %xmm2270; AVX1-NEXT: vpavgw %xmm1, %xmm0, %xmm0271; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0272; AVX1-NEXT: retq273;274; AVX2-LABEL: test_fixed_v16i16:275; AVX2: # %bb.0:276; AVX2-NEXT: vpavgw %ymm1, %ymm0, %ymm0277; AVX2-NEXT: retq278;279; AVX512-LABEL: test_fixed_v16i16:280; AVX512: # %bb.0:281; AVX512-NEXT: vpavgw %ymm1, %ymm0, %ymm0282; AVX512-NEXT: retq283 %or = or <16 x i16> %a0, %a1284 %xor = xor <16 x i16> %a1, %a0285 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>286 %res = sub <16 x i16> %or, %shift287 ret <16 x i16> %res288}289 290define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind {291; SSE-LABEL: test_ext_v16i16:292; SSE: # %bb.0:293; SSE-NEXT: pavgw %xmm2, %xmm0294; SSE-NEXT: pavgw %xmm3, %xmm1295; SSE-NEXT: retq296;297; AVX1-LABEL: test_ext_v16i16:298; AVX1: # %bb.0:299; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2300; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3301; AVX1-NEXT: vpavgw %xmm2, %xmm3, %xmm2302; AVX1-NEXT: vpavgw %xmm1, %xmm0, %xmm0303; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0304; AVX1-NEXT: retq305;306; AVX2-LABEL: test_ext_v16i16:307; AVX2: # %bb.0:308; AVX2-NEXT: vpavgw %ymm1, %ymm0, %ymm0309; AVX2-NEXT: retq310;311; AVX512-LABEL: test_ext_v16i16:312; AVX512: # %bb.0:313; AVX512-NEXT: vpavgw %ymm1, %ymm0, %ymm0314; AVX512-NEXT: retq315 %x0 = zext <16 x i16> %a0 to <16 x i32>316 %x1 = zext <16 x i16> %a1 to <16 x i32>317 %sum = add <16 x i32> %x0, %x1318 %inc = add <16 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>319 %shift = lshr <16 x i32> %inc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>320 %res = trunc <16 x i32> %shift to <16 x i16>321 ret <16 x i16> %res322}323 324define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind {325; SSE-LABEL: test_fixed_v8i32:326; SSE: # %bb.0:327; SSE-NEXT: movdqa %xmm0, %xmm4328; SSE-NEXT: por %xmm2, %xmm4329; SSE-NEXT: pxor %xmm2, %xmm0330; SSE-NEXT: psrld $1, %xmm0331; SSE-NEXT: psubd %xmm0, %xmm4332; SSE-NEXT: movdqa %xmm1, %xmm2333; SSE-NEXT: por %xmm3, %xmm2334; SSE-NEXT: pxor %xmm3, %xmm1335; SSE-NEXT: psrld $1, %xmm1336; SSE-NEXT: psubd %xmm1, %xmm2337; SSE-NEXT: movdqa %xmm4, %xmm0338; SSE-NEXT: movdqa %xmm2, %xmm1339; SSE-NEXT: retq340;341; AVX1-LABEL: test_fixed_v8i32:342; AVX1: # %bb.0:343; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm2344; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3345; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0346; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1347; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1348; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1349; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0350; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0351; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0352; AVX1-NEXT: retq353;354; AVX2-LABEL: test_fixed_v8i32:355; AVX2: # %bb.0:356; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm2357; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0358; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0359; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0360; AVX2-NEXT: retq361;362; AVX512-LABEL: test_fixed_v8i32:363; AVX512: # %bb.0:364; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm2365; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0366; AVX512-NEXT: vpsrld $1, %ymm0, %ymm0367; AVX512-NEXT: vpsubd %ymm0, %ymm2, %ymm0368; AVX512-NEXT: retq369 %or = or <8 x i32> %a0, %a1370 %xor = xor <8 x i32> %a1, %a0371 %shift = lshr <8 x i32> %xor, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>372 %res = sub <8 x i32> %or, %shift373 ret <8 x i32> %res374}375 376define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind {377; SSE-LABEL: test_ext_v8i32:378; SSE: # %bb.0:379; SSE-NEXT: movdqa %xmm0, %xmm4380; SSE-NEXT: por %xmm2, %xmm4381; SSE-NEXT: pxor %xmm2, %xmm0382; SSE-NEXT: psrld $1, %xmm0383; SSE-NEXT: psubd %xmm0, %xmm4384; SSE-NEXT: movdqa %xmm1, %xmm2385; SSE-NEXT: por %xmm3, %xmm2386; SSE-NEXT: pxor %xmm3, %xmm1387; SSE-NEXT: psrld $1, %xmm1388; SSE-NEXT: psubd %xmm1, %xmm2389; SSE-NEXT: movdqa %xmm4, %xmm0390; SSE-NEXT: movdqa %xmm2, %xmm1391; SSE-NEXT: retq392;393; AVX1-LABEL: test_ext_v8i32:394; AVX1: # %bb.0:395; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm2396; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3397; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0398; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1399; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1400; AVX1-NEXT: vpsubd %xmm1, %xmm3, %xmm1401; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0402; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0403; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0404; AVX1-NEXT: retq405;406; AVX2-LABEL: test_ext_v8i32:407; AVX2: # %bb.0:408; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm2409; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0410; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0411; AVX2-NEXT: vpsubd %ymm0, %ymm2, %ymm0412; AVX2-NEXT: retq413;414; AVX512-LABEL: test_ext_v8i32:415; AVX512: # %bb.0:416; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm2417; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0418; AVX512-NEXT: vpsrld $1, %ymm0, %ymm0419; AVX512-NEXT: vpsubd %ymm0, %ymm2, %ymm0420; AVX512-NEXT: retq421 %x0 = zext <8 x i32> %a0 to <8 x i64>422 %x1 = zext <8 x i32> %a1 to <8 x i64>423 %sum = add <8 x i64> %x0, %x1424 %inc = add <8 x i64> %sum, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>425 %shift = lshr <8 x i64> %inc, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>426 %res = trunc <8 x i64> %shift to <8 x i32>427 ret <8 x i32> %res428}429 430define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind {431; SSE-LABEL: test_fixed_v4i64:432; SSE: # %bb.0:433; SSE-NEXT: movdqa %xmm0, %xmm4434; SSE-NEXT: por %xmm2, %xmm4435; SSE-NEXT: pxor %xmm2, %xmm0436; SSE-NEXT: psrlq $1, %xmm0437; SSE-NEXT: psubq %xmm0, %xmm4438; SSE-NEXT: movdqa %xmm1, %xmm2439; SSE-NEXT: por %xmm3, %xmm2440; SSE-NEXT: pxor %xmm3, %xmm1441; SSE-NEXT: psrlq $1, %xmm1442; SSE-NEXT: psubq %xmm1, %xmm2443; SSE-NEXT: movdqa %xmm4, %xmm0444; SSE-NEXT: movdqa %xmm2, %xmm1445; SSE-NEXT: retq446;447; AVX1-LABEL: test_fixed_v4i64:448; AVX1: # %bb.0:449; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm2450; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3451; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0452; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1453; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1454; AVX1-NEXT: vpsubq %xmm1, %xmm3, %xmm1455; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0456; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0457; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0458; AVX1-NEXT: retq459;460; AVX2-LABEL: test_fixed_v4i64:461; AVX2: # %bb.0:462; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm2463; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0464; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0465; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0466; AVX2-NEXT: retq467;468; AVX512-LABEL: test_fixed_v4i64:469; AVX512: # %bb.0:470; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm2471; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0472; AVX512-NEXT: vpsrlq $1, %ymm0, %ymm0473; AVX512-NEXT: vpsubq %ymm0, %ymm2, %ymm0474; AVX512-NEXT: retq475 %or = or <4 x i64> %a0, %a1476 %xor = xor <4 x i64> %a1, %a0477 %shift = lshr <4 x i64> %xor, <i64 1, i64 1, i64 1, i64 1>478 %res = sub <4 x i64> %or, %shift479 ret <4 x i64> %res480}481 482define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind {483; SSE-LABEL: test_ext_v4i64:484; SSE: # %bb.0:485; SSE-NEXT: movdqa %xmm0, %xmm4486; SSE-NEXT: por %xmm2, %xmm4487; SSE-NEXT: pxor %xmm2, %xmm0488; SSE-NEXT: psrlq $1, %xmm0489; SSE-NEXT: psubq %xmm0, %xmm4490; SSE-NEXT: movdqa %xmm1, %xmm2491; SSE-NEXT: por %xmm3, %xmm2492; SSE-NEXT: pxor %xmm3, %xmm1493; SSE-NEXT: psrlq $1, %xmm1494; SSE-NEXT: psubq %xmm1, %xmm2495; SSE-NEXT: movdqa %xmm4, %xmm0496; SSE-NEXT: movdqa %xmm2, %xmm1497; SSE-NEXT: retq498;499; AVX1-LABEL: test_ext_v4i64:500; AVX1: # %bb.0:501; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm2502; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3503; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0504; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1505; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1506; AVX1-NEXT: vpsubq %xmm1, %xmm3, %xmm1507; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0508; AVX1-NEXT: vpsubq %xmm0, %xmm2, %xmm0509; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0510; AVX1-NEXT: retq511;512; AVX2-LABEL: test_ext_v4i64:513; AVX2: # %bb.0:514; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm2515; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0516; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0517; AVX2-NEXT: vpsubq %ymm0, %ymm2, %ymm0518; AVX2-NEXT: retq519;520; AVX512-LABEL: test_ext_v4i64:521; AVX512: # %bb.0:522; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm2523; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0524; AVX512-NEXT: vpsrlq $1, %ymm0, %ymm0525; AVX512-NEXT: vpsubq %ymm0, %ymm2, %ymm0526; AVX512-NEXT: retq527 %x0 = zext <4 x i64> %a0 to <4 x i128>528 %x1 = zext <4 x i64> %a1 to <4 x i128>529 %sum = add <4 x i128> %x0, %x1530 %inc = add <4 x i128> %sum, <i128 1, i128 1, i128 1, i128 1>531 %shift = lshr <4 x i128> %inc, <i128 1, i128 1, i128 1, i128 1>532 %res = trunc <4 x i128> %shift to <4 x i64>533 ret <4 x i64> %res534}535 536;537; 512-bit vectors538;539 540define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind {541; SSE-LABEL: test_fixed_v64i8:542; SSE: # %bb.0:543; SSE-NEXT: pavgb %xmm4, %xmm0544; SSE-NEXT: pavgb %xmm5, %xmm1545; SSE-NEXT: pavgb %xmm6, %xmm2546; SSE-NEXT: pavgb %xmm7, %xmm3547; SSE-NEXT: retq548;549; AVX1-LABEL: test_fixed_v64i8:550; AVX1: # %bb.0:551; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4552; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5553; AVX1-NEXT: vpavgb %xmm4, %xmm5, %xmm4554; AVX1-NEXT: vpavgb %xmm2, %xmm0, %xmm0555; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0556; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2557; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4558; AVX1-NEXT: vpavgb %xmm2, %xmm4, %xmm2559; AVX1-NEXT: vpavgb %xmm3, %xmm1, %xmm1560; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1561; AVX1-NEXT: retq562;563; AVX2-LABEL: test_fixed_v64i8:564; AVX2: # %bb.0:565; AVX2-NEXT: vpavgb %ymm2, %ymm0, %ymm0566; AVX2-NEXT: vpavgb %ymm3, %ymm1, %ymm1567; AVX2-NEXT: retq568;569; AVX512-LABEL: test_fixed_v64i8:570; AVX512: # %bb.0:571; AVX512-NEXT: vpavgb %zmm1, %zmm0, %zmm0572; AVX512-NEXT: retq573 %or = or <64 x i8> %a0, %a1574 %xor = xor <64 x i8> %a0, %a1575 %shift = lshr <64 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>576 %res = sub <64 x i8> %or, %shift577 ret <64 x i8> %res578}579 580define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind {581; SSE-LABEL: test_ext_v64i8:582; SSE: # %bb.0:583; SSE-NEXT: pavgb %xmm4, %xmm0584; SSE-NEXT: pavgb %xmm5, %xmm1585; SSE-NEXT: pavgb %xmm6, %xmm2586; SSE-NEXT: pavgb %xmm7, %xmm3587; SSE-NEXT: retq588;589; AVX1-LABEL: test_ext_v64i8:590; AVX1: # %bb.0:591; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4592; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5593; AVX1-NEXT: vpavgb %xmm4, %xmm5, %xmm4594; AVX1-NEXT: vpavgb %xmm2, %xmm0, %xmm0595; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0596; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2597; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4598; AVX1-NEXT: vpavgb %xmm2, %xmm4, %xmm2599; AVX1-NEXT: vpavgb %xmm3, %xmm1, %xmm1600; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1601; AVX1-NEXT: retq602;603; AVX2-LABEL: test_ext_v64i8:604; AVX2: # %bb.0:605; AVX2-NEXT: vpavgb %ymm2, %ymm0, %ymm0606; AVX2-NEXT: vpavgb %ymm3, %ymm1, %ymm1607; AVX2-NEXT: retq608;609; AVX512-LABEL: test_ext_v64i8:610; AVX512: # %bb.0:611; AVX512-NEXT: vpavgb %zmm1, %zmm0, %zmm0612; AVX512-NEXT: retq613 %x0 = zext <64 x i8> %a0 to <64 x i16>614 %x1 = zext <64 x i8> %a1 to <64 x i16>615 %sum = add <64 x i16> %x0, %x1616 %inc = add <64 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>617 %shift = lshr <64 x i16> %inc, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>618 %res = trunc <64 x i16> %shift to <64 x i8>619 ret <64 x i8> %res620}621 622define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind {623; SSE-LABEL: test_fixed_v32i16:624; SSE: # %bb.0:625; SSE-NEXT: pavgw %xmm4, %xmm0626; SSE-NEXT: pavgw %xmm5, %xmm1627; SSE-NEXT: pavgw %xmm6, %xmm2628; SSE-NEXT: pavgw %xmm7, %xmm3629; SSE-NEXT: retq630;631; AVX1-LABEL: test_fixed_v32i16:632; AVX1: # %bb.0:633; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4634; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5635; AVX1-NEXT: vpavgw %xmm4, %xmm5, %xmm4636; AVX1-NEXT: vpavgw %xmm2, %xmm0, %xmm0637; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0638; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2639; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4640; AVX1-NEXT: vpavgw %xmm2, %xmm4, %xmm2641; AVX1-NEXT: vpavgw %xmm3, %xmm1, %xmm1642; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1643; AVX1-NEXT: retq644;645; AVX2-LABEL: test_fixed_v32i16:646; AVX2: # %bb.0:647; AVX2-NEXT: vpavgw %ymm2, %ymm0, %ymm0648; AVX2-NEXT: vpavgw %ymm3, %ymm1, %ymm1649; AVX2-NEXT: retq650;651; AVX512-LABEL: test_fixed_v32i16:652; AVX512: # %bb.0:653; AVX512-NEXT: vpavgw %zmm1, %zmm0, %zmm0654; AVX512-NEXT: retq655 %or = or <32 x i16> %a0, %a1656 %xor = xor <32 x i16> %a1, %a0657 %shift = lshr <32 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>658 %res = sub <32 x i16> %or, %shift659 ret <32 x i16> %res660}661 662define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind {663; SSE-LABEL: test_ext_v32i16:664; SSE: # %bb.0:665; SSE-NEXT: pavgw %xmm4, %xmm0666; SSE-NEXT: pavgw %xmm5, %xmm1667; SSE-NEXT: pavgw %xmm6, %xmm2668; SSE-NEXT: pavgw %xmm7, %xmm3669; SSE-NEXT: retq670;671; AVX1-LABEL: test_ext_v32i16:672; AVX1: # %bb.0:673; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4674; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5675; AVX1-NEXT: vpavgw %xmm4, %xmm5, %xmm4676; AVX1-NEXT: vpavgw %xmm2, %xmm0, %xmm0677; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0678; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2679; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4680; AVX1-NEXT: vpavgw %xmm2, %xmm4, %xmm2681; AVX1-NEXT: vpavgw %xmm3, %xmm1, %xmm1682; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1683; AVX1-NEXT: retq684;685; AVX2-LABEL: test_ext_v32i16:686; AVX2: # %bb.0:687; AVX2-NEXT: vpavgw %ymm2, %ymm0, %ymm0688; AVX2-NEXT: vpavgw %ymm3, %ymm1, %ymm1689; AVX2-NEXT: retq690;691; AVX512-LABEL: test_ext_v32i16:692; AVX512: # %bb.0:693; AVX512-NEXT: vpavgw %zmm1, %zmm0, %zmm0694; AVX512-NEXT: retq695 %x0 = zext <32 x i16> %a0 to <32 x i32>696 %x1 = zext <32 x i16> %a1 to <32 x i32>697 %sum = add <32 x i32> %x0, %x1698 %inc = add <32 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>699 %shift = lshr <32 x i32> %inc, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>700 %res = trunc <32 x i32> %shift to <32 x i16>701 ret <32 x i16> %res702}703 704define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind {705; SSE-LABEL: test_fixed_v16i32:706; SSE: # %bb.0:707; SSE-NEXT: movdqa %xmm0, %xmm8708; SSE-NEXT: por %xmm4, %xmm8709; SSE-NEXT: pxor %xmm4, %xmm0710; SSE-NEXT: psrld $1, %xmm0711; SSE-NEXT: psubd %xmm0, %xmm8712; SSE-NEXT: movdqa %xmm1, %xmm4713; SSE-NEXT: por %xmm5, %xmm4714; SSE-NEXT: pxor %xmm5, %xmm1715; SSE-NEXT: psrld $1, %xmm1716; SSE-NEXT: psubd %xmm1, %xmm4717; SSE-NEXT: movdqa %xmm2, %xmm5718; SSE-NEXT: por %xmm6, %xmm5719; SSE-NEXT: pxor %xmm6, %xmm2720; SSE-NEXT: psrld $1, %xmm2721; SSE-NEXT: psubd %xmm2, %xmm5722; SSE-NEXT: movdqa %xmm3, %xmm6723; SSE-NEXT: por %xmm7, %xmm6724; SSE-NEXT: pxor %xmm7, %xmm3725; SSE-NEXT: psrld $1, %xmm3726; SSE-NEXT: psubd %xmm3, %xmm6727; SSE-NEXT: movdqa %xmm8, %xmm0728; SSE-NEXT: movdqa %xmm4, %xmm1729; SSE-NEXT: movdqa %xmm5, %xmm2730; SSE-NEXT: movdqa %xmm6, %xmm3731; SSE-NEXT: retq732;733; AVX1-LABEL: test_fixed_v16i32:734; AVX1: # %bb.0:735; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm4736; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5737; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0738; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2739; AVX1-NEXT: vpsrld $1, %xmm2, %xmm2740; AVX1-NEXT: vpsubd %xmm2, %xmm5, %xmm2741; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0742; AVX1-NEXT: vpsubd %xmm0, %xmm4, %xmm0743; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0744; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm2745; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4746; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1747; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3748; AVX1-NEXT: vpsrld $1, %xmm3, %xmm3749; AVX1-NEXT: vpsubd %xmm3, %xmm4, %xmm3750; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1751; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1752; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1753; AVX1-NEXT: retq754;755; AVX2-LABEL: test_fixed_v16i32:756; AVX2: # %bb.0:757; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm4758; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0759; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0760; AVX2-NEXT: vpsubd %ymm0, %ymm4, %ymm0761; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm2762; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1763; AVX2-NEXT: vpsrld $1, %ymm1, %ymm1764; AVX2-NEXT: vpsubd %ymm1, %ymm2, %ymm1765; AVX2-NEXT: retq766;767; AVX512-LABEL: test_fixed_v16i32:768; AVX512: # %bb.0:769; AVX512-NEXT: vpord %zmm1, %zmm0, %zmm2770; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm0771; AVX512-NEXT: vpsrld $1, %zmm0, %zmm0772; AVX512-NEXT: vpsubd %zmm0, %zmm2, %zmm0773; AVX512-NEXT: retq774 %or = or <16 x i32> %a0, %a1775 %xor = xor <16 x i32> %a1, %a0776 %shift = lshr <16 x i32> %xor, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>777 %res = sub <16 x i32> %or, %shift778 ret <16 x i32> %res779}780 781define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind {782; SSE-LABEL: test_ext_v16i32:783; SSE: # %bb.0:784; SSE-NEXT: movdqa %xmm0, %xmm8785; SSE-NEXT: por %xmm4, %xmm8786; SSE-NEXT: pxor %xmm4, %xmm0787; SSE-NEXT: psrld $1, %xmm0788; SSE-NEXT: psubd %xmm0, %xmm8789; SSE-NEXT: movdqa %xmm1, %xmm4790; SSE-NEXT: por %xmm5, %xmm4791; SSE-NEXT: pxor %xmm5, %xmm1792; SSE-NEXT: psrld $1, %xmm1793; SSE-NEXT: psubd %xmm1, %xmm4794; SSE-NEXT: movdqa %xmm2, %xmm5795; SSE-NEXT: por %xmm6, %xmm5796; SSE-NEXT: pxor %xmm6, %xmm2797; SSE-NEXT: psrld $1, %xmm2798; SSE-NEXT: psubd %xmm2, %xmm5799; SSE-NEXT: movdqa %xmm3, %xmm6800; SSE-NEXT: por %xmm7, %xmm6801; SSE-NEXT: pxor %xmm7, %xmm3802; SSE-NEXT: psrld $1, %xmm3803; SSE-NEXT: psubd %xmm3, %xmm6804; SSE-NEXT: movdqa %xmm8, %xmm0805; SSE-NEXT: movdqa %xmm4, %xmm1806; SSE-NEXT: movdqa %xmm5, %xmm2807; SSE-NEXT: movdqa %xmm6, %xmm3808; SSE-NEXT: retq809;810; AVX1-LABEL: test_ext_v16i32:811; AVX1: # %bb.0:812; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm4813; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5814; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0815; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2816; AVX1-NEXT: vpsrld $1, %xmm2, %xmm2817; AVX1-NEXT: vpsubd %xmm2, %xmm5, %xmm2818; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0819; AVX1-NEXT: vpsubd %xmm0, %xmm4, %xmm0820; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0821; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm2822; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4823; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1824; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3825; AVX1-NEXT: vpsrld $1, %xmm3, %xmm3826; AVX1-NEXT: vpsubd %xmm3, %xmm4, %xmm3827; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1828; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1829; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1830; AVX1-NEXT: retq831;832; AVX2-LABEL: test_ext_v16i32:833; AVX2: # %bb.0:834; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm4835; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0836; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0837; AVX2-NEXT: vpsubd %ymm0, %ymm4, %ymm0838; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm2839; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1840; AVX2-NEXT: vpsrld $1, %ymm1, %ymm1841; AVX2-NEXT: vpsubd %ymm1, %ymm2, %ymm1842; AVX2-NEXT: retq843;844; AVX512-LABEL: test_ext_v16i32:845; AVX512: # %bb.0:846; AVX512-NEXT: vpord %zmm1, %zmm0, %zmm2847; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm0848; AVX512-NEXT: vpsrld $1, %zmm0, %zmm0849; AVX512-NEXT: vpsubd %zmm0, %zmm2, %zmm0850; AVX512-NEXT: retq851 %x0 = zext <16 x i32> %a0 to <16 x i64>852 %x1 = zext <16 x i32> %a1 to <16 x i64>853 %sum = add <16 x i64> %x0, %x1854 %inc = add <16 x i64> %sum, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>855 %shift = lshr <16 x i64> %inc, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>856 %res = trunc <16 x i64> %shift to <16 x i32>857 ret <16 x i32> %res858}859 860define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind {861; SSE-LABEL: test_fixed_v8i64:862; SSE: # %bb.0:863; SSE-NEXT: movdqa %xmm0, %xmm8864; SSE-NEXT: por %xmm4, %xmm8865; SSE-NEXT: pxor %xmm4, %xmm0866; SSE-NEXT: psrlq $1, %xmm0867; SSE-NEXT: psubq %xmm0, %xmm8868; SSE-NEXT: movdqa %xmm1, %xmm4869; SSE-NEXT: por %xmm5, %xmm4870; SSE-NEXT: pxor %xmm5, %xmm1871; SSE-NEXT: psrlq $1, %xmm1872; SSE-NEXT: psubq %xmm1, %xmm4873; SSE-NEXT: movdqa %xmm2, %xmm5874; SSE-NEXT: por %xmm6, %xmm5875; SSE-NEXT: pxor %xmm6, %xmm2876; SSE-NEXT: psrlq $1, %xmm2877; SSE-NEXT: psubq %xmm2, %xmm5878; SSE-NEXT: movdqa %xmm3, %xmm6879; SSE-NEXT: por %xmm7, %xmm6880; SSE-NEXT: pxor %xmm7, %xmm3881; SSE-NEXT: psrlq $1, %xmm3882; SSE-NEXT: psubq %xmm3, %xmm6883; SSE-NEXT: movdqa %xmm8, %xmm0884; SSE-NEXT: movdqa %xmm4, %xmm1885; SSE-NEXT: movdqa %xmm5, %xmm2886; SSE-NEXT: movdqa %xmm6, %xmm3887; SSE-NEXT: retq888;889; AVX1-LABEL: test_fixed_v8i64:890; AVX1: # %bb.0:891; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm4892; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5893; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0894; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2895; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm2896; AVX1-NEXT: vpsubq %xmm2, %xmm5, %xmm2897; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0898; AVX1-NEXT: vpsubq %xmm0, %xmm4, %xmm0899; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0900; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm2901; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4902; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1903; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3904; AVX1-NEXT: vpsrlq $1, %xmm3, %xmm3905; AVX1-NEXT: vpsubq %xmm3, %xmm4, %xmm3906; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1907; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1908; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1909; AVX1-NEXT: retq910;911; AVX2-LABEL: test_fixed_v8i64:912; AVX2: # %bb.0:913; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm4914; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0915; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0916; AVX2-NEXT: vpsubq %ymm0, %ymm4, %ymm0917; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm2918; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1919; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm1920; AVX2-NEXT: vpsubq %ymm1, %ymm2, %ymm1921; AVX2-NEXT: retq922;923; AVX512-LABEL: test_fixed_v8i64:924; AVX512: # %bb.0:925; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm2926; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0927; AVX512-NEXT: vpsrlq $1, %zmm0, %zmm0928; AVX512-NEXT: vpsubq %zmm0, %zmm2, %zmm0929; AVX512-NEXT: retq930 %or = or <8 x i64> %a0, %a1931 %xor = xor <8 x i64> %a1, %a0932 %shift = lshr <8 x i64> %xor, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>933 %res = sub <8 x i64> %or, %shift934 ret <8 x i64> %res935}936 937define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind {938; SSE-LABEL: test_ext_v8i64:939; SSE: # %bb.0:940; SSE-NEXT: movdqa %xmm0, %xmm8941; SSE-NEXT: por %xmm4, %xmm8942; SSE-NEXT: pxor %xmm4, %xmm0943; SSE-NEXT: psrlq $1, %xmm0944; SSE-NEXT: psubq %xmm0, %xmm8945; SSE-NEXT: movdqa %xmm1, %xmm4946; SSE-NEXT: por %xmm5, %xmm4947; SSE-NEXT: pxor %xmm5, %xmm1948; SSE-NEXT: psrlq $1, %xmm1949; SSE-NEXT: psubq %xmm1, %xmm4950; SSE-NEXT: movdqa %xmm2, %xmm5951; SSE-NEXT: por %xmm6, %xmm5952; SSE-NEXT: pxor %xmm6, %xmm2953; SSE-NEXT: psrlq $1, %xmm2954; SSE-NEXT: psubq %xmm2, %xmm5955; SSE-NEXT: movdqa %xmm3, %xmm6956; SSE-NEXT: por %xmm7, %xmm6957; SSE-NEXT: pxor %xmm7, %xmm3958; SSE-NEXT: psrlq $1, %xmm3959; SSE-NEXT: psubq %xmm3, %xmm6960; SSE-NEXT: movdqa %xmm8, %xmm0961; SSE-NEXT: movdqa %xmm4, %xmm1962; SSE-NEXT: movdqa %xmm5, %xmm2963; SSE-NEXT: movdqa %xmm6, %xmm3964; SSE-NEXT: retq965;966; AVX1-LABEL: test_ext_v8i64:967; AVX1: # %bb.0:968; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm4969; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5970; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0971; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2972; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm2973; AVX1-NEXT: vpsubq %xmm2, %xmm5, %xmm2974; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0975; AVX1-NEXT: vpsubq %xmm0, %xmm4, %xmm0976; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0977; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm2978; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4979; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1980; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3981; AVX1-NEXT: vpsrlq $1, %xmm3, %xmm3982; AVX1-NEXT: vpsubq %xmm3, %xmm4, %xmm3983; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1984; AVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1985; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1986; AVX1-NEXT: retq987;988; AVX2-LABEL: test_ext_v8i64:989; AVX2: # %bb.0:990; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm4991; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0992; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0993; AVX2-NEXT: vpsubq %ymm0, %ymm4, %ymm0994; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm2995; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1996; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm1997; AVX2-NEXT: vpsubq %ymm1, %ymm2, %ymm1998; AVX2-NEXT: retq999;1000; AVX512-LABEL: test_ext_v8i64:1001; AVX512: # %bb.0:1002; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm21003; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm01004; AVX512-NEXT: vpsrlq $1, %zmm0, %zmm01005; AVX512-NEXT: vpsubq %zmm0, %zmm2, %zmm01006; AVX512-NEXT: retq1007 %x0 = zext <8 x i64> %a0 to <8 x i128>1008 %x1 = zext <8 x i64> %a1 to <8 x i128>1009 %sum = add <8 x i128> %x0, %x11010 %inc = add <8 x i128> %sum, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>1011 %shift = lshr <8 x i128> %inc, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>1012 %res = trunc <8 x i128> %shift to <8 x i64>1013 ret <8 x i64> %res1014}1015 1016;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1017; SSE2: {{.*}}1018; SSE4: {{.*}}1019