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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=x86_64 < %s | FileCheck %s3 4define i128 @avgflooru_i128(i128 %x, i128 %y) {5; CHECK-LABEL: avgflooru_i128:6; CHECK: # %bb.0: # %start7; CHECK-NEXT: movq %rdi, %rax8; CHECK-NEXT: addq %rdx, %rax9; CHECK-NEXT: adcq %rcx, %rsi10; CHECK-NEXT: setb %cl11; CHECK-NEXT: shrdq $1, %rsi, %rax12; CHECK-NEXT: movzbl %cl, %edx13; CHECK-NEXT: shldq $63, %rsi, %rdx14; CHECK-NEXT: retq15start:16 %xor = xor i128 %y, %x17 %lshr = lshr i128 %xor, 118 %and = and i128 %y, %x19 %add = add i128 %lshr, %and20 ret i128 %add21}22 23declare void @use(i8)24 25define i128 @avgflooru_i128_multi_use(i128 %x, i128 %y) nounwind {26; CHECK-LABEL: avgflooru_i128_multi_use:27; CHECK: # %bb.0: # %start28; CHECK-NEXT: pushq %rbp29; CHECK-NEXT: pushq %r1530; CHECK-NEXT: pushq %r1431; CHECK-NEXT: pushq %r1332; CHECK-NEXT: pushq %r1233; CHECK-NEXT: pushq %rbx34; CHECK-NEXT: pushq %rax35; CHECK-NEXT: movq %rcx, %rbx36; CHECK-NEXT: movq %rdx, %r1437; CHECK-NEXT: movq %rsi, %r1538; CHECK-NEXT: movq %rdi, %r1239; CHECK-NEXT: movq %rdx, %r1340; CHECK-NEXT: xorq %rdi, %r1341; CHECK-NEXT: movq %rcx, %rbp42; CHECK-NEXT: xorq %rsi, %rbp43; CHECK-NEXT: movq %r13, %rdi44; CHECK-NEXT: movq %rbp, %rsi45; CHECK-NEXT: callq use@PLT46; CHECK-NEXT: shrdq $1, %rbp, %r1347; CHECK-NEXT: shrq %rbp48; CHECK-NEXT: movq %r13, %rdi49; CHECK-NEXT: movq %rbp, %rsi50; CHECK-NEXT: callq use@PLT51; CHECK-NEXT: addq %r14, %r1252; CHECK-NEXT: adcq %rbx, %r1553; CHECK-NEXT: setb %al54; CHECK-NEXT: shrdq $1, %r15, %r1255; CHECK-NEXT: movzbl %al, %edx56; CHECK-NEXT: shldq $63, %r15, %rdx57; CHECK-NEXT: movq %r12, %rax58; CHECK-NEXT: addq $8, %rsp59; CHECK-NEXT: popq %rbx60; CHECK-NEXT: popq %r1261; CHECK-NEXT: popq %r1362; CHECK-NEXT: popq %r1463; CHECK-NEXT: popq %r1564; CHECK-NEXT: popq %rbp65; CHECK-NEXT: retq66start:67 %xor = xor i128 %y, %x68 call void @use(i128 %xor)69 %lshr = lshr i128 %xor, 170 call void @use(i128 %lshr)71 %and = and i128 %y, %x72 %add = add i128 %lshr, %and73 ret i128 %add74}75 76; This test case shouldn't combine because it's not77; an avgflooru operation78 79define i128 @avgflooru_i128_negative(i128 %x, i128 %y) {80; CHECK-LABEL: avgflooru_i128_negative:81; CHECK: # %bb.0: # %start82; CHECK-NEXT: movq %rdi, %rax83; CHECK-NEXT: andq %rsi, %rcx84; CHECK-NEXT: notq %rsi85; CHECK-NEXT: andq %rdi, %rdx86; CHECK-NEXT: notq %rax87; CHECK-NEXT: addq %rdx, %rax88; CHECK-NEXT: adcq %rcx, %rsi89; CHECK-NEXT: movq %rsi, %rdx90; CHECK-NEXT: retq91start:92 %xor = xor i128 %x, -193 %and = and i128 %y, %x94 %add = add i128 %xor, %and95 ret i128 %add96}97 98; This negative test case shouldn't combine, i32 is already properly99; handled in terms of legalization, compared to the i128100 101define i32 @avgflooru_i128_negative2(i32 %x, i32 %y) {102; CHECK-LABEL: avgflooru_i128_negative2:103; CHECK: # %bb.0: # %start104; CHECK-NEXT: movl %edi, %ecx105; CHECK-NEXT: movl %esi, %eax106; CHECK-NEXT: addq %rcx, %rax107; CHECK-NEXT: shrq %rax108; CHECK-NEXT: # kill: def $eax killed $eax killed $rax109; CHECK-NEXT: retq110start:111 %xor = xor i32 %y, %x112 %lshr = lshr i32 %xor, 1113 %and = and i32 %y, %x114 %add = add i32 %lshr, %and115 ret i32 %add116}117 118define <2 x i128> @avgflooru_i128_vec(<2 x i128> %x, <2 x i128> %y) {119; CHECK-LABEL: avgflooru_i128_vec:120; CHECK: # %bb.0: # %start121; CHECK-NEXT: movq %rdi, %rax122; CHECK-NEXT: addq %r9, %rsi123; CHECK-NEXT: adcq {{[0-9]+}}(%rsp), %rdx124; CHECK-NEXT: setb %dil125; CHECK-NEXT: movzbl %dil, %edi126; CHECK-NEXT: shldq $63, %rdx, %rdi127; CHECK-NEXT: addq {{[0-9]+}}(%rsp), %rcx128; CHECK-NEXT: adcq {{[0-9]+}}(%rsp), %r8129; CHECK-NEXT: setb %r9b130; CHECK-NEXT: movzbl %r9b, %r9d131; CHECK-NEXT: shldq $63, %r8, %r9132; CHECK-NEXT: shldq $63, %rsi, %rdx133; CHECK-NEXT: shldq $63, %rcx, %r8134; CHECK-NEXT: movq %r8, 16(%rax)135; CHECK-NEXT: movq %rdx, (%rax)136; CHECK-NEXT: movq %r9, 24(%rax)137; CHECK-NEXT: movq %rdi, 8(%rax)138; CHECK-NEXT: retq139start:140 %xor = xor <2 x i128> %y, %x141 %lshr = lshr <2 x i128> %xor, <i128 1, i128 1>142 %and = and <2 x i128> %y, %x143 %add = add <2 x i128> %lshr, %and144 ret <2 x i128> %add145}146