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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE44; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX15; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX26; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX5127 8;9; 128-bit vectors10;11 12define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind {13; SSE-LABEL: test_fixed_v16i8:14; SSE: # %bb.0:15; SSE-NEXT: movdqa %xmm0, %xmm216; SSE-NEXT: pand %xmm1, %xmm217; SSE-NEXT: pxor %xmm1, %xmm018; SSE-NEXT: psrlw $1, %xmm019; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm020; SSE-NEXT: paddb %xmm2, %xmm021; SSE-NEXT: retq22;23; AVX1-LABEL: test_fixed_v16i8:24; AVX1: # %bb.0:25; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm226; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm027; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm028; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm029; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm030; AVX1-NEXT: retq31;32; AVX2-LABEL: test_fixed_v16i8:33; AVX2: # %bb.0:34; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm235; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm036; AVX2-NEXT: vpsrlw $1, %xmm0, %xmm037; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm038; AVX2-NEXT: vpaddb %xmm0, %xmm2, %xmm039; AVX2-NEXT: retq40;41; AVX512-LABEL: test_fixed_v16i8:42; AVX512: # %bb.0:43; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm244; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm045; AVX512-NEXT: vpsrlw $1, %xmm0, %xmm046; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm047; AVX512-NEXT: vpaddb %xmm0, %xmm2, %xmm048; AVX512-NEXT: retq49 %and = and <16 x i8> %a0, %a150 %xor = xor <16 x i8> %a0, %a151 %shift = lshr <16 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>52 %res = add <16 x i8> %and, %shift53 ret <16 x i8> %res54}55 56define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind {57; SSE-LABEL: test_ext_v16i8:58; SSE: # %bb.0:59; SSE-NEXT: movdqa %xmm0, %xmm260; SSE-NEXT: pand %xmm1, %xmm261; SSE-NEXT: pxor %xmm1, %xmm062; SSE-NEXT: psrlw $1, %xmm063; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm064; SSE-NEXT: paddb %xmm2, %xmm065; SSE-NEXT: retq66;67; AVX1-LABEL: test_ext_v16i8:68; AVX1: # %bb.0:69; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm270; AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm071; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm072; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm073; AVX1-NEXT: vpaddb %xmm0, %xmm2, %xmm074; AVX1-NEXT: retq75;76; AVX2-LABEL: test_ext_v16i8:77; AVX2: # %bb.0:78; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm279; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm080; AVX2-NEXT: vpsrlw $1, %xmm0, %xmm081; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm082; AVX2-NEXT: vpaddb %xmm0, %xmm2, %xmm083; AVX2-NEXT: retq84;85; AVX512-LABEL: test_ext_v16i8:86; AVX512: # %bb.0:87; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm288; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm089; AVX512-NEXT: vpsrlw $1, %xmm0, %xmm090; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm091; AVX512-NEXT: vpaddb %xmm0, %xmm2, %xmm092; AVX512-NEXT: retq93 %x0 = zext <16 x i8> %a0 to <16 x i16>94 %x1 = zext <16 x i8> %a1 to <16 x i16>95 %sum = add <16 x i16> %x0, %x196 %shift = lshr <16 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>97 %res = trunc <16 x i16> %shift to <16 x i8>98 ret <16 x i8> %res99}100 101define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind {102; SSE-LABEL: test_fixed_v8i16:103; SSE: # %bb.0:104; SSE-NEXT: movdqa %xmm0, %xmm2105; SSE-NEXT: pand %xmm1, %xmm2106; SSE-NEXT: pxor %xmm1, %xmm0107; SSE-NEXT: psrlw $1, %xmm0108; SSE-NEXT: paddw %xmm2, %xmm0109; SSE-NEXT: retq110;111; AVX-LABEL: test_fixed_v8i16:112; AVX: # %bb.0:113; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2114; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0115; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0116; AVX-NEXT: vpaddw %xmm0, %xmm2, %xmm0117; AVX-NEXT: retq118 %and = and <8 x i16> %a0, %a1119 %xor = xor <8 x i16> %a1, %a0120 %shift = lshr <8 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>121 %res = add <8 x i16> %and, %shift122 ret <8 x i16> %res123}124 125define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind {126; SSE-LABEL: test_ext_v8i16:127; SSE: # %bb.0:128; SSE-NEXT: movdqa %xmm0, %xmm2129; SSE-NEXT: pand %xmm1, %xmm2130; SSE-NEXT: pxor %xmm1, %xmm0131; SSE-NEXT: psrlw $1, %xmm0132; SSE-NEXT: paddw %xmm2, %xmm0133; SSE-NEXT: retq134;135; AVX-LABEL: test_ext_v8i16:136; AVX: # %bb.0:137; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2138; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0139; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0140; AVX-NEXT: vpaddw %xmm0, %xmm2, %xmm0141; AVX-NEXT: retq142 %x0 = zext <8 x i16> %a0 to <8 x i32>143 %x1 = zext <8 x i16> %a1 to <8 x i32>144 %sum = add <8 x i32> %x0, %x1145 %shift = lshr <8 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>146 %res = trunc <8 x i32> %shift to <8 x i16>147 ret <8 x i16> %res148}149 150define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {151; SSE-LABEL: test_fixed_v4i32:152; SSE: # %bb.0:153; SSE-NEXT: movdqa %xmm0, %xmm2154; SSE-NEXT: pand %xmm1, %xmm2155; SSE-NEXT: pxor %xmm1, %xmm0156; SSE-NEXT: psrld $1, %xmm0157; SSE-NEXT: paddd %xmm2, %xmm0158; SSE-NEXT: retq159;160; AVX-LABEL: test_fixed_v4i32:161; AVX: # %bb.0:162; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2163; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0164; AVX-NEXT: vpsrld $1, %xmm0, %xmm0165; AVX-NEXT: vpaddd %xmm0, %xmm2, %xmm0166; AVX-NEXT: retq167 %and = and <4 x i32> %a0, %a1168 %xor = xor <4 x i32> %a1, %a0169 %shift = lshr <4 x i32> %xor, <i32 1, i32 1, i32 1, i32 1>170 %res = add <4 x i32> %and, %shift171 ret <4 x i32> %res172}173 174define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {175; SSE-LABEL: test_ext_v4i32:176; SSE: # %bb.0:177; SSE-NEXT: movdqa %xmm0, %xmm2178; SSE-NEXT: pand %xmm1, %xmm2179; SSE-NEXT: pxor %xmm1, %xmm0180; SSE-NEXT: psrld $1, %xmm0181; SSE-NEXT: paddd %xmm2, %xmm0182; SSE-NEXT: retq183;184; AVX-LABEL: test_ext_v4i32:185; AVX: # %bb.0:186; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2187; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0188; AVX-NEXT: vpsrld $1, %xmm0, %xmm0189; AVX-NEXT: vpaddd %xmm0, %xmm2, %xmm0190; AVX-NEXT: retq191 %x0 = zext <4 x i32> %a0 to <4 x i64>192 %x1 = zext <4 x i32> %a1 to <4 x i64>193 %sum = add <4 x i64> %x0, %x1194 %shift = lshr <4 x i64> %sum, <i64 1, i64 1, i64 1, i64 1>195 %res = trunc <4 x i64> %shift to <4 x i32>196 ret <4 x i32> %res197}198 199define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind {200; SSE-LABEL: test_fixed_v2i64:201; SSE: # %bb.0:202; SSE-NEXT: movdqa %xmm0, %xmm2203; SSE-NEXT: pand %xmm1, %xmm2204; SSE-NEXT: pxor %xmm1, %xmm0205; SSE-NEXT: psrlq $1, %xmm0206; SSE-NEXT: paddq %xmm2, %xmm0207; SSE-NEXT: retq208;209; AVX-LABEL: test_fixed_v2i64:210; AVX: # %bb.0:211; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2212; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0213; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0214; AVX-NEXT: vpaddq %xmm0, %xmm2, %xmm0215; AVX-NEXT: retq216 %and = and <2 x i64> %a0, %a1217 %xor = xor <2 x i64> %a1, %a0218 %shift = lshr <2 x i64> %xor, <i64 1, i64 1>219 %res = add <2 x i64> %and, %shift220 ret <2 x i64> %res221}222 223define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind {224; SSE-LABEL: test_ext_v2i64:225; SSE: # %bb.0:226; SSE-NEXT: movdqa %xmm0, %xmm2227; SSE-NEXT: pand %xmm1, %xmm2228; SSE-NEXT: pxor %xmm1, %xmm0229; SSE-NEXT: psrlq $1, %xmm0230; SSE-NEXT: paddq %xmm2, %xmm0231; SSE-NEXT: retq232;233; AVX-LABEL: test_ext_v2i64:234; AVX: # %bb.0:235; AVX-NEXT: vpand %xmm1, %xmm0, %xmm2236; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0237; AVX-NEXT: vpsrlq $1, %xmm0, %xmm0238; AVX-NEXT: vpaddq %xmm0, %xmm2, %xmm0239; AVX-NEXT: retq240 %x0 = zext <2 x i64> %a0 to <2 x i128>241 %x1 = zext <2 x i64> %a1 to <2 x i128>242 %sum = add <2 x i128> %x0, %x1243 %shift = lshr <2 x i128> %sum, <i128 1, i128 1>244 %res = trunc <2 x i128> %shift to <2 x i64>245 ret <2 x i64> %res246}247 248;249; 256-bit vectors250;251 252define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind {253; SSE-LABEL: test_fixed_v32i8:254; SSE: # %bb.0:255; SSE-NEXT: movdqa %xmm0, %xmm4256; SSE-NEXT: pand %xmm2, %xmm4257; SSE-NEXT: pxor %xmm2, %xmm0258; SSE-NEXT: psrlw $1, %xmm0259; SSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]260; SSE-NEXT: pand %xmm2, %xmm0261; SSE-NEXT: paddb %xmm4, %xmm0262; SSE-NEXT: movdqa %xmm1, %xmm4263; SSE-NEXT: pand %xmm3, %xmm4264; SSE-NEXT: pxor %xmm3, %xmm1265; SSE-NEXT: psrlw $1, %xmm1266; SSE-NEXT: pand %xmm2, %xmm1267; SSE-NEXT: paddb %xmm4, %xmm1268; SSE-NEXT: retq269;270; AVX1-LABEL: test_fixed_v32i8:271; AVX1: # %bb.0:272; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm2273; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3274; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm3275; AVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]276; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3277; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0278; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1279; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1280; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2281; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2282; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0283; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0284; AVX1-NEXT: retq285;286; AVX2-LABEL: test_fixed_v32i8:287; AVX2: # %bb.0:288; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2289; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0290; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0291; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0292; AVX2-NEXT: vpaddb %ymm0, %ymm2, %ymm0293; AVX2-NEXT: retq294;295; AVX512-LABEL: test_fixed_v32i8:296; AVX512: # %bb.0:297; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2298; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0299; AVX512-NEXT: vpsrlw $1, %ymm0, %ymm0300; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0301; AVX512-NEXT: vpaddb %ymm0, %ymm2, %ymm0302; AVX512-NEXT: retq303 %and = and <32 x i8> %a0, %a1304 %xor = xor <32 x i8> %a0, %a1305 %shift = lshr <32 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>306 %res = add <32 x i8> %and, %shift307 ret <32 x i8> %res308}309 310define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind {311; SSE-LABEL: test_ext_v32i8:312; SSE: # %bb.0:313; SSE-NEXT: movdqa %xmm0, %xmm4314; SSE-NEXT: pand %xmm2, %xmm4315; SSE-NEXT: pxor %xmm2, %xmm0316; SSE-NEXT: psrlw $1, %xmm0317; SSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]318; SSE-NEXT: pand %xmm2, %xmm0319; SSE-NEXT: paddb %xmm4, %xmm0320; SSE-NEXT: movdqa %xmm1, %xmm4321; SSE-NEXT: pand %xmm3, %xmm4322; SSE-NEXT: pxor %xmm3, %xmm1323; SSE-NEXT: psrlw $1, %xmm1324; SSE-NEXT: pand %xmm2, %xmm1325; SSE-NEXT: paddb %xmm4, %xmm1326; SSE-NEXT: retq327;328; AVX1-LABEL: test_ext_v32i8:329; AVX1: # %bb.0:330; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm2331; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3332; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm3333; AVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]334; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3335; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0336; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1337; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1338; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2339; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2340; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0341; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0342; AVX1-NEXT: retq343;344; AVX2-LABEL: test_ext_v32i8:345; AVX2: # %bb.0:346; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2347; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0348; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0349; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0350; AVX2-NEXT: vpaddb %ymm0, %ymm2, %ymm0351; AVX2-NEXT: retq352;353; AVX512-LABEL: test_ext_v32i8:354; AVX512: # %bb.0:355; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2356; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0357; AVX512-NEXT: vpsrlw $1, %ymm0, %ymm0358; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0359; AVX512-NEXT: vpaddb %ymm0, %ymm2, %ymm0360; AVX512-NEXT: retq361 %x0 = zext <32 x i8> %a0 to <32 x i16>362 %x1 = zext <32 x i8> %a1 to <32 x i16>363 %sum = add <32 x i16> %x0, %x1364 %shift = lshr <32 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>365 %res = trunc <32 x i16> %shift to <32 x i8>366 ret <32 x i8> %res367}368 369define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind {370; SSE-LABEL: test_fixed_v16i16:371; SSE: # %bb.0:372; SSE-NEXT: movdqa %xmm0, %xmm4373; SSE-NEXT: pand %xmm2, %xmm4374; SSE-NEXT: pxor %xmm2, %xmm0375; SSE-NEXT: psrlw $1, %xmm0376; SSE-NEXT: paddw %xmm4, %xmm0377; SSE-NEXT: movdqa %xmm1, %xmm2378; SSE-NEXT: pand %xmm3, %xmm2379; SSE-NEXT: pxor %xmm3, %xmm1380; SSE-NEXT: psrlw $1, %xmm1381; SSE-NEXT: paddw %xmm2, %xmm1382; SSE-NEXT: retq383;384; AVX1-LABEL: test_fixed_v16i16:385; AVX1: # %bb.0:386; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2387; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3388; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0389; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1390; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm1391; AVX1-NEXT: vpaddw %xmm1, %xmm3, %xmm1392; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0393; AVX1-NEXT: vpaddw %xmm0, %xmm2, %xmm0394; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0395; AVX1-NEXT: retq396;397; AVX2-LABEL: test_fixed_v16i16:398; AVX2: # %bb.0:399; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2400; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0401; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0402; AVX2-NEXT: vpaddw %ymm0, %ymm2, %ymm0403; AVX2-NEXT: retq404;405; AVX512-LABEL: test_fixed_v16i16:406; AVX512: # %bb.0:407; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2408; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0409; AVX512-NEXT: vpsrlw $1, %ymm0, %ymm0410; AVX512-NEXT: vpaddw %ymm0, %ymm2, %ymm0411; AVX512-NEXT: retq412 %and = and <16 x i16> %a0, %a1413 %xor = xor <16 x i16> %a1, %a0414 %shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>415 %res = add <16 x i16> %and, %shift416 ret <16 x i16> %res417}418 419define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind {420; SSE-LABEL: test_ext_v16i16:421; SSE: # %bb.0:422; SSE-NEXT: movdqa %xmm0, %xmm4423; SSE-NEXT: pand %xmm2, %xmm4424; SSE-NEXT: pxor %xmm2, %xmm0425; SSE-NEXT: psrlw $1, %xmm0426; SSE-NEXT: paddw %xmm4, %xmm0427; SSE-NEXT: movdqa %xmm1, %xmm2428; SSE-NEXT: pand %xmm3, %xmm2429; SSE-NEXT: pxor %xmm3, %xmm1430; SSE-NEXT: psrlw $1, %xmm1431; SSE-NEXT: paddw %xmm2, %xmm1432; SSE-NEXT: retq433;434; AVX1-LABEL: test_ext_v16i16:435; AVX1: # %bb.0:436; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2437; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3438; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0439; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1440; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm1441; AVX1-NEXT: vpaddw %xmm1, %xmm3, %xmm1442; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0443; AVX1-NEXT: vpaddw %xmm0, %xmm2, %xmm0444; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0445; AVX1-NEXT: retq446;447; AVX2-LABEL: test_ext_v16i16:448; AVX2: # %bb.0:449; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2450; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0451; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0452; AVX2-NEXT: vpaddw %ymm0, %ymm2, %ymm0453; AVX2-NEXT: retq454;455; AVX512-LABEL: test_ext_v16i16:456; AVX512: # %bb.0:457; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2458; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0459; AVX512-NEXT: vpsrlw $1, %ymm0, %ymm0460; AVX512-NEXT: vpaddw %ymm0, %ymm2, %ymm0461; AVX512-NEXT: retq462 %x0 = zext <16 x i16> %a0 to <16 x i32>463 %x1 = zext <16 x i16> %a1 to <16 x i32>464 %sum = add <16 x i32> %x0, %x1465 %shift = lshr <16 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>466 %res = trunc <16 x i32> %shift to <16 x i16>467 ret <16 x i16> %res468}469 470define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind {471; SSE-LABEL: test_fixed_v8i32:472; SSE: # %bb.0:473; SSE-NEXT: movdqa %xmm0, %xmm4474; SSE-NEXT: pand %xmm2, %xmm4475; SSE-NEXT: pxor %xmm2, %xmm0476; SSE-NEXT: psrld $1, %xmm0477; SSE-NEXT: paddd %xmm4, %xmm0478; SSE-NEXT: movdqa %xmm1, %xmm2479; SSE-NEXT: pand %xmm3, %xmm2480; SSE-NEXT: pxor %xmm3, %xmm1481; SSE-NEXT: psrld $1, %xmm1482; SSE-NEXT: paddd %xmm2, %xmm1483; SSE-NEXT: retq484;485; AVX1-LABEL: test_fixed_v8i32:486; AVX1: # %bb.0:487; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2488; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3489; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0490; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1491; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1492; AVX1-NEXT: vpaddd %xmm1, %xmm3, %xmm1493; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0494; AVX1-NEXT: vpaddd %xmm0, %xmm2, %xmm0495; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0496; AVX1-NEXT: retq497;498; AVX2-LABEL: test_fixed_v8i32:499; AVX2: # %bb.0:500; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2501; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0502; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0503; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0504; AVX2-NEXT: retq505;506; AVX512-LABEL: test_fixed_v8i32:507; AVX512: # %bb.0:508; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2509; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0510; AVX512-NEXT: vpsrld $1, %ymm0, %ymm0511; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0512; AVX512-NEXT: retq513 %and = and <8 x i32> %a0, %a1514 %xor = xor <8 x i32> %a1, %a0515 %shift = lshr <8 x i32> %xor, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>516 %res = add <8 x i32> %and, %shift517 ret <8 x i32> %res518}519 520define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind {521; SSE-LABEL: test_ext_v8i32:522; SSE: # %bb.0:523; SSE-NEXT: movdqa %xmm0, %xmm4524; SSE-NEXT: pand %xmm2, %xmm4525; SSE-NEXT: pxor %xmm2, %xmm0526; SSE-NEXT: psrld $1, %xmm0527; SSE-NEXT: paddd %xmm4, %xmm0528; SSE-NEXT: movdqa %xmm1, %xmm2529; SSE-NEXT: pand %xmm3, %xmm2530; SSE-NEXT: pxor %xmm3, %xmm1531; SSE-NEXT: psrld $1, %xmm1532; SSE-NEXT: paddd %xmm2, %xmm1533; SSE-NEXT: retq534;535; AVX1-LABEL: test_ext_v8i32:536; AVX1: # %bb.0:537; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2538; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3539; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0540; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1541; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1542; AVX1-NEXT: vpaddd %xmm1, %xmm3, %xmm1543; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0544; AVX1-NEXT: vpaddd %xmm0, %xmm2, %xmm0545; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0546; AVX1-NEXT: retq547;548; AVX2-LABEL: test_ext_v8i32:549; AVX2: # %bb.0:550; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2551; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0552; AVX2-NEXT: vpsrld $1, %ymm0, %ymm0553; AVX2-NEXT: vpaddd %ymm0, %ymm2, %ymm0554; AVX2-NEXT: retq555;556; AVX512-LABEL: test_ext_v8i32:557; AVX512: # %bb.0:558; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2559; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0560; AVX512-NEXT: vpsrld $1, %ymm0, %ymm0561; AVX512-NEXT: vpaddd %ymm0, %ymm2, %ymm0562; AVX512-NEXT: retq563 %x0 = zext <8 x i32> %a0 to <8 x i64>564 %x1 = zext <8 x i32> %a1 to <8 x i64>565 %sum = add <8 x i64> %x0, %x1566 %shift = lshr <8 x i64> %sum, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>567 %res = trunc <8 x i64> %shift to <8 x i32>568 ret <8 x i32> %res569}570 571define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind {572; SSE-LABEL: test_fixed_v4i64:573; SSE: # %bb.0:574; SSE-NEXT: movdqa %xmm0, %xmm4575; SSE-NEXT: pand %xmm2, %xmm4576; SSE-NEXT: pxor %xmm2, %xmm0577; SSE-NEXT: psrlq $1, %xmm0578; SSE-NEXT: paddq %xmm4, %xmm0579; SSE-NEXT: movdqa %xmm1, %xmm2580; SSE-NEXT: pand %xmm3, %xmm2581; SSE-NEXT: pxor %xmm3, %xmm1582; SSE-NEXT: psrlq $1, %xmm1583; SSE-NEXT: paddq %xmm2, %xmm1584; SSE-NEXT: retq585;586; AVX1-LABEL: test_fixed_v4i64:587; AVX1: # %bb.0:588; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2589; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3590; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0591; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1592; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1593; AVX1-NEXT: vpaddq %xmm1, %xmm3, %xmm1594; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0595; AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0596; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0597; AVX1-NEXT: retq598;599; AVX2-LABEL: test_fixed_v4i64:600; AVX2: # %bb.0:601; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2602; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0603; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0604; AVX2-NEXT: vpaddq %ymm0, %ymm2, %ymm0605; AVX2-NEXT: retq606;607; AVX512-LABEL: test_fixed_v4i64:608; AVX512: # %bb.0:609; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2610; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0611; AVX512-NEXT: vpsrlq $1, %ymm0, %ymm0612; AVX512-NEXT: vpaddq %ymm0, %ymm2, %ymm0613; AVX512-NEXT: retq614 %and = and <4 x i64> %a0, %a1615 %xor = xor <4 x i64> %a1, %a0616 %shift = lshr <4 x i64> %xor, <i64 1, i64 1, i64 1, i64 1>617 %res = add <4 x i64> %and, %shift618 ret <4 x i64> %res619}620 621define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind {622; SSE-LABEL: test_ext_v4i64:623; SSE: # %bb.0:624; SSE-NEXT: movdqa %xmm0, %xmm4625; SSE-NEXT: pand %xmm2, %xmm4626; SSE-NEXT: pxor %xmm2, %xmm0627; SSE-NEXT: psrlq $1, %xmm0628; SSE-NEXT: paddq %xmm4, %xmm0629; SSE-NEXT: movdqa %xmm1, %xmm2630; SSE-NEXT: pand %xmm3, %xmm2631; SSE-NEXT: pxor %xmm3, %xmm1632; SSE-NEXT: psrlq $1, %xmm1633; SSE-NEXT: paddq %xmm2, %xmm1634; SSE-NEXT: retq635;636; AVX1-LABEL: test_ext_v4i64:637; AVX1: # %bb.0:638; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm2639; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3640; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0641; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1642; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm1643; AVX1-NEXT: vpaddq %xmm1, %xmm3, %xmm1644; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0645; AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0646; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0647; AVX1-NEXT: retq648;649; AVX2-LABEL: test_ext_v4i64:650; AVX2: # %bb.0:651; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm2652; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0653; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm0654; AVX2-NEXT: vpaddq %ymm0, %ymm2, %ymm0655; AVX2-NEXT: retq656;657; AVX512-LABEL: test_ext_v4i64:658; AVX512: # %bb.0:659; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm2660; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0661; AVX512-NEXT: vpsrlq $1, %ymm0, %ymm0662; AVX512-NEXT: vpaddq %ymm0, %ymm2, %ymm0663; AVX512-NEXT: retq664 %x0 = zext <4 x i64> %a0 to <4 x i128>665 %x1 = zext <4 x i64> %a1 to <4 x i128>666 %sum = add <4 x i128> %x0, %x1667 %shift = lshr <4 x i128> %sum, <i128 1, i128 1, i128 1, i128 1>668 %res = trunc <4 x i128> %shift to <4 x i64>669 ret <4 x i64> %res670}671 672;673; 512-bit vectors674;675 676define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind {677; SSE-LABEL: test_fixed_v64i8:678; SSE: # %bb.0:679; SSE-NEXT: movdqa %xmm0, %xmm8680; SSE-NEXT: pand %xmm4, %xmm8681; SSE-NEXT: pxor %xmm4, %xmm0682; SSE-NEXT: psrlw $1, %xmm0683; SSE-NEXT: movdqa {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]684; SSE-NEXT: pand %xmm4, %xmm0685; SSE-NEXT: paddb %xmm8, %xmm0686; SSE-NEXT: movdqa %xmm1, %xmm8687; SSE-NEXT: pand %xmm5, %xmm8688; SSE-NEXT: pxor %xmm5, %xmm1689; SSE-NEXT: psrlw $1, %xmm1690; SSE-NEXT: pand %xmm4, %xmm1691; SSE-NEXT: paddb %xmm8, %xmm1692; SSE-NEXT: movdqa %xmm2, %xmm5693; SSE-NEXT: pand %xmm6, %xmm5694; SSE-NEXT: pxor %xmm6, %xmm2695; SSE-NEXT: psrlw $1, %xmm2696; SSE-NEXT: pand %xmm4, %xmm2697; SSE-NEXT: paddb %xmm5, %xmm2698; SSE-NEXT: movdqa %xmm3, %xmm5699; SSE-NEXT: pand %xmm7, %xmm5700; SSE-NEXT: pxor %xmm7, %xmm3701; SSE-NEXT: psrlw $1, %xmm3702; SSE-NEXT: pand %xmm4, %xmm3703; SSE-NEXT: paddb %xmm5, %xmm3704; SSE-NEXT: retq705;706; AVX1-LABEL: test_fixed_v64i8:707; AVX1: # %bb.0:708; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm4709; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5710; AVX1-NEXT: vpsrlw $1, %xmm5, %xmm5711; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]712; AVX1-NEXT: vpand %xmm6, %xmm5, %xmm5713; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0714; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2715; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2716; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm4717; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4718; AVX1-NEXT: vpaddb %xmm4, %xmm0, %xmm0719; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0720; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm2721; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4722; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm4723; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4724; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1725; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3726; AVX1-NEXT: vpaddb %xmm4, %xmm3, %xmm3727; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2728; AVX1-NEXT: vpand %xmm6, %xmm2, %xmm2729; AVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm1730; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1731; AVX1-NEXT: retq732;733; AVX2-LABEL: test_fixed_v64i8:734; AVX2: # %bb.0:735; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm4736; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0737; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0738; AVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]739; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0740; AVX2-NEXT: vpaddb %ymm0, %ymm4, %ymm0741; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm4742; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1743; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1744; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1745; AVX2-NEXT: vpaddb %ymm1, %ymm4, %ymm1746; AVX2-NEXT: retq747;748; AVX512-LABEL: test_fixed_v64i8:749; AVX512: # %bb.0:750; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm2751; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0752; AVX512-NEXT: vpsrlw $1, %zmm0, %zmm0753; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0754; AVX512-NEXT: vpaddb %zmm0, %zmm2, %zmm0755; AVX512-NEXT: retq756 %and = and <64 x i8> %a0, %a1757 %xor = xor <64 x i8> %a0, %a1758 %shift = lshr <64 x i8> %xor, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>759 %res = add <64 x i8> %and, %shift760 ret <64 x i8> %res761}762 763define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind {764; SSE-LABEL: test_ext_v64i8:765; SSE: # %bb.0:766; SSE-NEXT: movdqa %xmm0, %xmm8767; SSE-NEXT: pand %xmm4, %xmm8768; SSE-NEXT: pxor %xmm4, %xmm0769; SSE-NEXT: psrlw $1, %xmm0770; SSE-NEXT: movdqa {{.*#+}} xmm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]771; SSE-NEXT: pand %xmm4, %xmm0772; SSE-NEXT: paddb %xmm8, %xmm0773; SSE-NEXT: movdqa %xmm1, %xmm8774; SSE-NEXT: pand %xmm5, %xmm8775; SSE-NEXT: pxor %xmm5, %xmm1776; SSE-NEXT: psrlw $1, %xmm1777; SSE-NEXT: pand %xmm4, %xmm1778; SSE-NEXT: paddb %xmm8, %xmm1779; SSE-NEXT: movdqa %xmm2, %xmm5780; SSE-NEXT: pand %xmm6, %xmm5781; SSE-NEXT: pxor %xmm6, %xmm2782; SSE-NEXT: psrlw $1, %xmm2783; SSE-NEXT: pand %xmm4, %xmm2784; SSE-NEXT: paddb %xmm5, %xmm2785; SSE-NEXT: movdqa %xmm3, %xmm5786; SSE-NEXT: pand %xmm7, %xmm5787; SSE-NEXT: pxor %xmm7, %xmm3788; SSE-NEXT: psrlw $1, %xmm3789; SSE-NEXT: pand %xmm4, %xmm3790; SSE-NEXT: paddb %xmm5, %xmm3791; SSE-NEXT: retq792;793; AVX1-LABEL: test_ext_v64i8:794; AVX1: # %bb.0:795; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm4796; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5797; AVX1-NEXT: vpsrlw $1, %xmm5, %xmm5798; AVX1-NEXT: vbroadcastss {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]799; AVX1-NEXT: vpand %xmm6, %xmm5, %xmm5800; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0801; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2802; AVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2803; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm4804; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4805; AVX1-NEXT: vpaddb %xmm4, %xmm0, %xmm0806; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0807; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm2808; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4809; AVX1-NEXT: vpsrlw $1, %xmm4, %xmm4810; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm4811; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1812; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3813; AVX1-NEXT: vpaddb %xmm4, %xmm3, %xmm3814; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2815; AVX1-NEXT: vpand %xmm6, %xmm2, %xmm2816; AVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm1817; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1818; AVX1-NEXT: retq819;820; AVX2-LABEL: test_ext_v64i8:821; AVX2: # %bb.0:822; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm4823; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0824; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0825; AVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]826; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0827; AVX2-NEXT: vpaddb %ymm0, %ymm4, %ymm0828; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm4829; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1830; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1831; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1832; AVX2-NEXT: vpaddb %ymm1, %ymm4, %ymm1833; AVX2-NEXT: retq834;835; AVX512-LABEL: test_ext_v64i8:836; AVX512: # %bb.0:837; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm2838; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0839; AVX512-NEXT: vpsrlw $1, %zmm0, %zmm0840; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0841; AVX512-NEXT: vpaddb %zmm0, %zmm2, %zmm0842; AVX512-NEXT: retq843 %x0 = zext <64 x i8> %a0 to <64 x i16>844 %x1 = zext <64 x i8> %a1 to <64 x i16>845 %sum = add <64 x i16> %x0, %x1846 %shift = lshr <64 x i16> %sum, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>847 %res = trunc <64 x i16> %shift to <64 x i8>848 ret <64 x i8> %res849}850 851define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind {852; SSE-LABEL: test_fixed_v32i16:853; SSE: # %bb.0:854; SSE-NEXT: movdqa %xmm0, %xmm8855; SSE-NEXT: pand %xmm4, %xmm8856; SSE-NEXT: pxor %xmm4, %xmm0857; SSE-NEXT: psrlw $1, %xmm0858; SSE-NEXT: paddw %xmm8, %xmm0859; SSE-NEXT: movdqa %xmm1, %xmm4860; SSE-NEXT: pand %xmm5, %xmm4861; SSE-NEXT: pxor %xmm5, %xmm1862; SSE-NEXT: psrlw $1, %xmm1863; SSE-NEXT: paddw %xmm4, %xmm1864; SSE-NEXT: movdqa %xmm2, %xmm4865; SSE-NEXT: pand %xmm6, %xmm4866; SSE-NEXT: pxor %xmm6, %xmm2867; SSE-NEXT: psrlw $1, %xmm2868; SSE-NEXT: paddw %xmm4, %xmm2869; SSE-NEXT: movdqa %xmm3, %xmm4870; SSE-NEXT: pand %xmm7, %xmm4871; SSE-NEXT: pxor %xmm7, %xmm3872; SSE-NEXT: psrlw $1, %xmm3873; SSE-NEXT: paddw %xmm4, %xmm3874; SSE-NEXT: retq875;876; AVX1-LABEL: test_fixed_v32i16:877; AVX1: # %bb.0:878; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm4879; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5880; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0881; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2882; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2883; AVX1-NEXT: vpaddw %xmm2, %xmm5, %xmm2884; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0885; AVX1-NEXT: vpaddw %xmm0, %xmm4, %xmm0886; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0887; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm2888; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4889; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1890; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3891; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm3892; AVX1-NEXT: vpaddw %xmm3, %xmm4, %xmm3893; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm1894; AVX1-NEXT: vpaddw %xmm1, %xmm2, %xmm1895; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1896; AVX1-NEXT: retq897;898; AVX2-LABEL: test_fixed_v32i16:899; AVX2: # %bb.0:900; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm4901; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0902; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0903; AVX2-NEXT: vpaddw %ymm0, %ymm4, %ymm0904; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm2905; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1906; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1907; AVX2-NEXT: vpaddw %ymm1, %ymm2, %ymm1908; AVX2-NEXT: retq909;910; AVX512-LABEL: test_fixed_v32i16:911; AVX512: # %bb.0:912; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm2913; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0914; AVX512-NEXT: vpsrlw $1, %zmm0, %zmm0915; AVX512-NEXT: vpaddw %zmm0, %zmm2, %zmm0916; AVX512-NEXT: retq917 %and = and <32 x i16> %a0, %a1918 %xor = xor <32 x i16> %a1, %a0919 %shift = lshr <32 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>920 %res = add <32 x i16> %and, %shift921 ret <32 x i16> %res922}923 924define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind {925; SSE-LABEL: test_ext_v32i16:926; SSE: # %bb.0:927; SSE-NEXT: movdqa %xmm0, %xmm8928; SSE-NEXT: pand %xmm4, %xmm8929; SSE-NEXT: pxor %xmm4, %xmm0930; SSE-NEXT: psrlw $1, %xmm0931; SSE-NEXT: paddw %xmm8, %xmm0932; SSE-NEXT: movdqa %xmm1, %xmm4933; SSE-NEXT: pand %xmm5, %xmm4934; SSE-NEXT: pxor %xmm5, %xmm1935; SSE-NEXT: psrlw $1, %xmm1936; SSE-NEXT: paddw %xmm4, %xmm1937; SSE-NEXT: movdqa %xmm2, %xmm4938; SSE-NEXT: pand %xmm6, %xmm4939; SSE-NEXT: pxor %xmm6, %xmm2940; SSE-NEXT: psrlw $1, %xmm2941; SSE-NEXT: paddw %xmm4, %xmm2942; SSE-NEXT: movdqa %xmm3, %xmm4943; SSE-NEXT: pand %xmm7, %xmm4944; SSE-NEXT: pxor %xmm7, %xmm3945; SSE-NEXT: psrlw $1, %xmm3946; SSE-NEXT: paddw %xmm4, %xmm3947; SSE-NEXT: retq948;949; AVX1-LABEL: test_ext_v32i16:950; AVX1: # %bb.0:951; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm4952; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm5953; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0954; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2955; AVX1-NEXT: vpsrlw $1, %xmm2, %xmm2956; AVX1-NEXT: vpaddw %xmm2, %xmm5, %xmm2957; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm0958; AVX1-NEXT: vpaddw %xmm0, %xmm4, %xmm0959; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0960; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm2961; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4962; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1963; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3964; AVX1-NEXT: vpsrlw $1, %xmm3, %xmm3965; AVX1-NEXT: vpaddw %xmm3, %xmm4, %xmm3966; AVX1-NEXT: vpsrlw $1, %xmm1, %xmm1967; AVX1-NEXT: vpaddw %xmm1, %xmm2, %xmm1968; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1969; AVX1-NEXT: retq970;971; AVX2-LABEL: test_ext_v32i16:972; AVX2: # %bb.0:973; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm4974; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0975; AVX2-NEXT: vpsrlw $1, %ymm0, %ymm0976; AVX2-NEXT: vpaddw %ymm0, %ymm4, %ymm0977; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm2978; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1979; AVX2-NEXT: vpsrlw $1, %ymm1, %ymm1980; AVX2-NEXT: vpaddw %ymm1, %ymm2, %ymm1981; AVX2-NEXT: retq982;983; AVX512-LABEL: test_ext_v32i16:984; AVX512: # %bb.0:985; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm2986; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0987; AVX512-NEXT: vpsrlw $1, %zmm0, %zmm0988; AVX512-NEXT: vpaddw %zmm0, %zmm2, %zmm0989; AVX512-NEXT: retq990 %x0 = zext <32 x i16> %a0 to <32 x i32>991 %x1 = zext <32 x i16> %a1 to <32 x i32>992 %sum = add <32 x i32> %x0, %x1993 %shift = lshr <32 x i32> %sum, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>994 %res = trunc <32 x i32> %shift to <32 x i16>995 ret <32 x i16> %res996}997 998define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind {999; SSE-LABEL: test_fixed_v16i32:1000; SSE: # %bb.0:1001; SSE-NEXT: movdqa %xmm0, %xmm81002; SSE-NEXT: pand %xmm4, %xmm81003; SSE-NEXT: pxor %xmm4, %xmm01004; SSE-NEXT: psrld $1, %xmm01005; SSE-NEXT: paddd %xmm8, %xmm01006; SSE-NEXT: movdqa %xmm1, %xmm41007; SSE-NEXT: pand %xmm5, %xmm41008; SSE-NEXT: pxor %xmm5, %xmm11009; SSE-NEXT: psrld $1, %xmm11010; SSE-NEXT: paddd %xmm4, %xmm11011; SSE-NEXT: movdqa %xmm2, %xmm41012; SSE-NEXT: pand %xmm6, %xmm41013; SSE-NEXT: pxor %xmm6, %xmm21014; SSE-NEXT: psrld $1, %xmm21015; SSE-NEXT: paddd %xmm4, %xmm21016; SSE-NEXT: movdqa %xmm3, %xmm41017; SSE-NEXT: pand %xmm7, %xmm41018; SSE-NEXT: pxor %xmm7, %xmm31019; SSE-NEXT: psrld $1, %xmm31020; SSE-NEXT: paddd %xmm4, %xmm31021; SSE-NEXT: retq1022;1023; AVX1-LABEL: test_fixed_v16i32:1024; AVX1: # %bb.0:1025; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm41026; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm51027; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm01028; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21029; AVX1-NEXT: vpsrld $1, %xmm2, %xmm21030; AVX1-NEXT: vpaddd %xmm2, %xmm5, %xmm21031; AVX1-NEXT: vpsrld $1, %xmm0, %xmm01032; AVX1-NEXT: vpaddd %xmm0, %xmm4, %xmm01033; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01034; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm21035; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm41036; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm11037; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm31038; AVX1-NEXT: vpsrld $1, %xmm3, %xmm31039; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm31040; AVX1-NEXT: vpsrld $1, %xmm1, %xmm11041; AVX1-NEXT: vpaddd %xmm1, %xmm2, %xmm11042; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm11043; AVX1-NEXT: retq1044;1045; AVX2-LABEL: test_fixed_v16i32:1046; AVX2: # %bb.0:1047; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm41048; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm01049; AVX2-NEXT: vpsrld $1, %ymm0, %ymm01050; AVX2-NEXT: vpaddd %ymm0, %ymm4, %ymm01051; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm21052; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm11053; AVX2-NEXT: vpsrld $1, %ymm1, %ymm11054; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm11055; AVX2-NEXT: retq1056;1057; AVX512-LABEL: test_fixed_v16i32:1058; AVX512: # %bb.0:1059; AVX512-NEXT: vpandd %zmm1, %zmm0, %zmm21060; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm01061; AVX512-NEXT: vpsrld $1, %zmm0, %zmm01062; AVX512-NEXT: vpaddd %zmm0, %zmm2, %zmm01063; AVX512-NEXT: retq1064 %and = and <16 x i32> %a0, %a11065 %xor = xor <16 x i32> %a1, %a01066 %shift = lshr <16 x i32> %xor, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1067 %res = add <16 x i32> %and, %shift1068 ret <16 x i32> %res1069}1070 1071define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind {1072; SSE-LABEL: test_ext_v16i32:1073; SSE: # %bb.0:1074; SSE-NEXT: movdqa %xmm0, %xmm81075; SSE-NEXT: pand %xmm4, %xmm81076; SSE-NEXT: pxor %xmm4, %xmm01077; SSE-NEXT: psrld $1, %xmm01078; SSE-NEXT: paddd %xmm8, %xmm01079; SSE-NEXT: movdqa %xmm1, %xmm41080; SSE-NEXT: pand %xmm5, %xmm41081; SSE-NEXT: pxor %xmm5, %xmm11082; SSE-NEXT: psrld $1, %xmm11083; SSE-NEXT: paddd %xmm4, %xmm11084; SSE-NEXT: movdqa %xmm2, %xmm41085; SSE-NEXT: pand %xmm6, %xmm41086; SSE-NEXT: pxor %xmm6, %xmm21087; SSE-NEXT: psrld $1, %xmm21088; SSE-NEXT: paddd %xmm4, %xmm21089; SSE-NEXT: movdqa %xmm3, %xmm41090; SSE-NEXT: pand %xmm7, %xmm41091; SSE-NEXT: pxor %xmm7, %xmm31092; SSE-NEXT: psrld $1, %xmm31093; SSE-NEXT: paddd %xmm4, %xmm31094; SSE-NEXT: retq1095;1096; AVX1-LABEL: test_ext_v16i32:1097; AVX1: # %bb.0:1098; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm41099; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm51100; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm01101; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21102; AVX1-NEXT: vpsrld $1, %xmm2, %xmm21103; AVX1-NEXT: vpaddd %xmm2, %xmm5, %xmm21104; AVX1-NEXT: vpsrld $1, %xmm0, %xmm01105; AVX1-NEXT: vpaddd %xmm0, %xmm4, %xmm01106; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01107; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm21108; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm41109; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm11110; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm31111; AVX1-NEXT: vpsrld $1, %xmm3, %xmm31112; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm31113; AVX1-NEXT: vpsrld $1, %xmm1, %xmm11114; AVX1-NEXT: vpaddd %xmm1, %xmm2, %xmm11115; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm11116; AVX1-NEXT: retq1117;1118; AVX2-LABEL: test_ext_v16i32:1119; AVX2: # %bb.0:1120; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm41121; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm01122; AVX2-NEXT: vpsrld $1, %ymm0, %ymm01123; AVX2-NEXT: vpaddd %ymm0, %ymm4, %ymm01124; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm21125; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm11126; AVX2-NEXT: vpsrld $1, %ymm1, %ymm11127; AVX2-NEXT: vpaddd %ymm1, %ymm2, %ymm11128; AVX2-NEXT: retq1129;1130; AVX512-LABEL: test_ext_v16i32:1131; AVX512: # %bb.0:1132; AVX512-NEXT: vpandd %zmm1, %zmm0, %zmm21133; AVX512-NEXT: vpxord %zmm1, %zmm0, %zmm01134; AVX512-NEXT: vpsrld $1, %zmm0, %zmm01135; AVX512-NEXT: vpaddd %zmm0, %zmm2, %zmm01136; AVX512-NEXT: retq1137 %x0 = zext <16 x i32> %a0 to <16 x i64>1138 %x1 = zext <16 x i32> %a1 to <16 x i64>1139 %sum = add <16 x i64> %x0, %x11140 %shift = lshr <16 x i64> %sum, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>1141 %res = trunc <16 x i64> %shift to <16 x i32>1142 ret <16 x i32> %res1143}1144 1145define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind {1146; SSE-LABEL: test_fixed_v8i64:1147; SSE: # %bb.0:1148; SSE-NEXT: movdqa %xmm0, %xmm81149; SSE-NEXT: pand %xmm4, %xmm81150; SSE-NEXT: pxor %xmm4, %xmm01151; SSE-NEXT: psrlq $1, %xmm01152; SSE-NEXT: paddq %xmm8, %xmm01153; SSE-NEXT: movdqa %xmm1, %xmm41154; SSE-NEXT: pand %xmm5, %xmm41155; SSE-NEXT: pxor %xmm5, %xmm11156; SSE-NEXT: psrlq $1, %xmm11157; SSE-NEXT: paddq %xmm4, %xmm11158; SSE-NEXT: movdqa %xmm2, %xmm41159; SSE-NEXT: pand %xmm6, %xmm41160; SSE-NEXT: pxor %xmm6, %xmm21161; SSE-NEXT: psrlq $1, %xmm21162; SSE-NEXT: paddq %xmm4, %xmm21163; SSE-NEXT: movdqa %xmm3, %xmm41164; SSE-NEXT: pand %xmm7, %xmm41165; SSE-NEXT: pxor %xmm7, %xmm31166; SSE-NEXT: psrlq $1, %xmm31167; SSE-NEXT: paddq %xmm4, %xmm31168; SSE-NEXT: retq1169;1170; AVX1-LABEL: test_fixed_v8i64:1171; AVX1: # %bb.0:1172; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm41173; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm51174; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm01175; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21176; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm21177; AVX1-NEXT: vpaddq %xmm2, %xmm5, %xmm21178; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm01179; AVX1-NEXT: vpaddq %xmm0, %xmm4, %xmm01180; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01181; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm21182; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm41183; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm11184; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm31185; AVX1-NEXT: vpsrlq $1, %xmm3, %xmm31186; AVX1-NEXT: vpaddq %xmm3, %xmm4, %xmm31187; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm11188; AVX1-NEXT: vpaddq %xmm1, %xmm2, %xmm11189; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm11190; AVX1-NEXT: retq1191;1192; AVX2-LABEL: test_fixed_v8i64:1193; AVX2: # %bb.0:1194; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm41195; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm01196; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm01197; AVX2-NEXT: vpaddq %ymm0, %ymm4, %ymm01198; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm21199; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm11200; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm11201; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm11202; AVX2-NEXT: retq1203;1204; AVX512-LABEL: test_fixed_v8i64:1205; AVX512: # %bb.0:1206; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm21207; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm01208; AVX512-NEXT: vpsrlq $1, %zmm0, %zmm01209; AVX512-NEXT: vpaddq %zmm0, %zmm2, %zmm01210; AVX512-NEXT: retq1211 %and = and <8 x i64> %a0, %a11212 %xor = xor <8 x i64> %a1, %a01213 %shift = lshr <8 x i64> %xor, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>1214 %res = add <8 x i64> %and, %shift1215 ret <8 x i64> %res1216}1217 1218define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind {1219; SSE-LABEL: test_ext_v8i64:1220; SSE: # %bb.0:1221; SSE-NEXT: movdqa %xmm0, %xmm81222; SSE-NEXT: pand %xmm4, %xmm81223; SSE-NEXT: pxor %xmm4, %xmm01224; SSE-NEXT: psrlq $1, %xmm01225; SSE-NEXT: paddq %xmm8, %xmm01226; SSE-NEXT: movdqa %xmm1, %xmm41227; SSE-NEXT: pand %xmm5, %xmm41228; SSE-NEXT: pxor %xmm5, %xmm11229; SSE-NEXT: psrlq $1, %xmm11230; SSE-NEXT: paddq %xmm4, %xmm11231; SSE-NEXT: movdqa %xmm2, %xmm41232; SSE-NEXT: pand %xmm6, %xmm41233; SSE-NEXT: pxor %xmm6, %xmm21234; SSE-NEXT: psrlq $1, %xmm21235; SSE-NEXT: paddq %xmm4, %xmm21236; SSE-NEXT: movdqa %xmm3, %xmm41237; SSE-NEXT: pand %xmm7, %xmm41238; SSE-NEXT: pxor %xmm7, %xmm31239; SSE-NEXT: psrlq $1, %xmm31240; SSE-NEXT: paddq %xmm4, %xmm31241; SSE-NEXT: retq1242;1243; AVX1-LABEL: test_ext_v8i64:1244; AVX1: # %bb.0:1245; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm41246; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm51247; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm01248; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21249; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm21250; AVX1-NEXT: vpaddq %xmm2, %xmm5, %xmm21251; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm01252; AVX1-NEXT: vpaddq %xmm0, %xmm4, %xmm01253; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01254; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm21255; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm41256; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm11257; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm31258; AVX1-NEXT: vpsrlq $1, %xmm3, %xmm31259; AVX1-NEXT: vpaddq %xmm3, %xmm4, %xmm31260; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm11261; AVX1-NEXT: vpaddq %xmm1, %xmm2, %xmm11262; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm11263; AVX1-NEXT: retq1264;1265; AVX2-LABEL: test_ext_v8i64:1266; AVX2: # %bb.0:1267; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm41268; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm01269; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm01270; AVX2-NEXT: vpaddq %ymm0, %ymm4, %ymm01271; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm21272; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm11273; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm11274; AVX2-NEXT: vpaddq %ymm1, %ymm2, %ymm11275; AVX2-NEXT: retq1276;1277; AVX512-LABEL: test_ext_v8i64:1278; AVX512: # %bb.0:1279; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm21280; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm01281; AVX512-NEXT: vpsrlq $1, %zmm0, %zmm01282; AVX512-NEXT: vpaddq %zmm0, %zmm2, %zmm01283; AVX512-NEXT: retq1284 %x0 = zext <8 x i64> %a0 to <8 x i128>1285 %x1 = zext <8 x i64> %a1 to <8 x i128>1286 %sum = add <8 x i128> %x0, %x11287 %shift = lshr <8 x i128> %sum, <i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1, i128 1>1288 %res = trunc <8 x i128> %shift to <8 x i64>1289 ret <8 x i64> %res1290}1291 1292;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1293; SSE2: {{.*}}1294; SSE4: {{.*}}1295