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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s3 4; Check that we generate vector conversion from float to narrower int types5 6%f32vec_t = type <8 x float>7%i16vec_t = type <8 x i16>8%i8vec_t = type <8 x i8>9 10define void @fptoui16(%f32vec_t %a, ptr%p) {11; CHECK-LABEL: fptoui16:12; CHECK: # %bb.0:13; CHECK-NEXT: vcvttps2dq %ymm0, %ymm014; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm115; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm016; CHECK-NEXT: vmovdqa %xmm0, (%rdi)17; CHECK-NEXT: vzeroupper18; CHECK-NEXT: retq19 %b = fptoui %f32vec_t %a to %i16vec_t20 store %i16vec_t %b, ptr %p21 ret void22}23 24define void @fptosi16(%f32vec_t %a, ptr%p) {25; CHECK-LABEL: fptosi16:26; CHECK: # %bb.0:27; CHECK-NEXT: vcvttps2dq %ymm0, %ymm028; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm129; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm030; CHECK-NEXT: vmovdqa %xmm0, (%rdi)31; CHECK-NEXT: vzeroupper32; CHECK-NEXT: retq33 %b = fptosi %f32vec_t %a to %i16vec_t34 store %i16vec_t %b, ptr %p35 ret void36}37 38define void @fptoui8(%f32vec_t %a, ptr%p) {39; CHECK-LABEL: fptoui8:40; CHECK: # %bb.0:41; CHECK-NEXT: vcvttps2dq %ymm0, %ymm042; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm143; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm044; CHECK-NEXT: vpackuswb %xmm0, %xmm0, %xmm045; CHECK-NEXT: vmovq %xmm0, (%rdi)46; CHECK-NEXT: vzeroupper47; CHECK-NEXT: retq48 %b = fptoui %f32vec_t %a to %i8vec_t49 store %i8vec_t %b, ptr %p50 ret void51}52 53define void @fptosi8(%f32vec_t %a, ptr%p) {54; CHECK-LABEL: fptosi8:55; CHECK: # %bb.0:56; CHECK-NEXT: vcvttps2dq %ymm0, %ymm057; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm158; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm059; CHECK-NEXT: vpacksswb %xmm0, %xmm0, %xmm060; CHECK-NEXT: vmovq %xmm0, (%rdi)61; CHECK-NEXT: vzeroupper62; CHECK-NEXT: retq63 %b = fptosi %f32vec_t %a to %i8vec_t64 store %i8vec_t %b, ptr %p65 ret void66}67