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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefix=AVX3; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefix=AVX4 5; PR37751 - https://bugs.llvm.org/show_bug.cgi?id=377516; We can't combine into 'round' instructions because the behavior is different for out-of-range values.7 8declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>)9declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>)10 11define <8 x float> @float_to_int_to_float_mem_v8f32(ptr %p) #0 {12; AVX-LABEL: float_to_int_to_float_mem_v8f32:13; AVX: # %bb.0:14; AVX-NEXT: vcvttps2dq (%rdi), %ymm015; AVX-NEXT: vcvtdq2ps %ymm0, %ymm016; AVX-NEXT: retq17 %x = load <8 x float>, ptr %p, align 1618 %fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)19 %sitofp = sitofp <8 x i32> %fptosi to <8 x float>20 ret <8 x float> %sitofp21}22 23define <8 x float> @float_to_int_to_float_reg_v8f32(<8 x float> %x) #0 {24; AVX-LABEL: float_to_int_to_float_reg_v8f32:25; AVX: # %bb.0:26; AVX-NEXT: vcvttps2dq %ymm0, %ymm027; AVX-NEXT: vcvtdq2ps %ymm0, %ymm028; AVX-NEXT: retq29 %fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)30 %sitofp = sitofp <8 x i32> %fptosi to <8 x float>31 ret <8 x float> %sitofp32}33 34define <4 x double> @float_to_int_to_float_mem_v4f64(ptr %p) #0 {35; AVX-LABEL: float_to_int_to_float_mem_v4f64:36; AVX: # %bb.0:37; AVX-NEXT: vcvttpd2dqy (%rdi), %xmm038; AVX-NEXT: vcvtdq2pd %xmm0, %ymm039; AVX-NEXT: retq40 %x = load <4 x double>, ptr %p, align 1641 %fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)42 %sitofp = sitofp <4 x i32> %fptosi to <4 x double>43 ret <4 x double> %sitofp44}45 46define <4 x double> @float_to_int_to_float_reg_v4f64(<4 x double> %x) #0 {47; AVX-LABEL: float_to_int_to_float_reg_v4f64:48; AVX: # %bb.0:49; AVX-NEXT: vcvttpd2dq %ymm0, %xmm050; AVX-NEXT: vcvtdq2pd %xmm0, %ymm051; AVX-NEXT: retq52 %fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)53 %sitofp = sitofp <4 x i32> %fptosi to <4 x double>54 ret <4 x double> %sitofp55}56 57attributes #0 = { "no-signed-zeros-fp-math"="true" }58 59