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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx,slow-unaligned-mem-32 | FileCheck %s3; RUN: llc -O0 < %s -mtriple=x86_64-unknown-unknown -mattr=avx,slow-unaligned-mem-32 | FileCheck %s -check-prefix=CHECK_O04 5define void @test_256_load(ptr nocapture %d, ptr nocapture %f, ptr nocapture %i) nounwind {6; CHECK-LABEL: test_256_load:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: pushq %r159; CHECK-NEXT: pushq %r1410; CHECK-NEXT: pushq %rbx11; CHECK-NEXT: subq $96, %rsp12; CHECK-NEXT: movq %rdx, %rbx13; CHECK-NEXT: movq %rsi, %r1414; CHECK-NEXT: movq %rdi, %r1515; CHECK-NEXT: vmovaps (%rdi), %ymm016; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill17; CHECK-NEXT: vmovaps (%rsi), %ymm118; CHECK-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill19; CHECK-NEXT: vmovaps (%rdx), %ymm220; CHECK-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill21; CHECK-NEXT: callq dummy@PLT22; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload23; CHECK-NEXT: vmovaps %ymm0, (%r15)24; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload25; CHECK-NEXT: vmovaps %ymm0, (%r14)26; CHECK-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload27; CHECK-NEXT: vmovaps %ymm0, (%rbx)28; CHECK-NEXT: addq $96, %rsp29; CHECK-NEXT: popq %rbx30; CHECK-NEXT: popq %r1431; CHECK-NEXT: popq %r1532; CHECK-NEXT: vzeroupper33; CHECK-NEXT: retq34;35; CHECK_O0-LABEL: test_256_load:36; CHECK_O0: # %bb.0: # %entry37; CHECK_O0-NEXT: subq $136, %rsp38; CHECK_O0-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill39; CHECK_O0-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill40; CHECK_O0-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill41; CHECK_O0-NEXT: vmovapd (%rdi), %ymm042; CHECK_O0-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill43; CHECK_O0-NEXT: vmovaps (%rsi), %ymm144; CHECK_O0-NEXT: vmovups %ymm1, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill45; CHECK_O0-NEXT: vmovdqa (%rdx), %ymm246; CHECK_O0-NEXT: vmovups %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill47; CHECK_O0-NEXT: callq dummy@PLT48; CHECK_O0-NEXT: vmovups (%rsp), %ymm2 # 32-byte Reload49; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload50; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm1 # 32-byte Reload51; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload52; CHECK_O0-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload53; CHECK_O0-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload54; CHECK_O0-NEXT: vmovapd %ymm2, (%rdi)55; CHECK_O0-NEXT: vmovaps %ymm1, (%rsi)56; CHECK_O0-NEXT: vmovdqa %ymm0, (%rdx)57; CHECK_O0-NEXT: addq $136, %rsp58; CHECK_O0-NEXT: vzeroupper59; CHECK_O0-NEXT: retq60entry:61 %tmp1.i = load <4 x double>, ptr %d, align 3262 %tmp1.i17 = load <8 x float>, ptr %f, align 3263 %tmp1.i16 = load <4 x i64>, ptr %i, align 3264 tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind65 store <4 x double> %tmp1.i, ptr %d, align 3266 store <8 x float> %tmp1.i17, ptr %f, align 3267 store <4 x i64> %tmp1.i16, ptr %i, align 3268 ret void69}70 71declare void @dummy(<4 x double>, <8 x float>, <4 x i64>)72 73;;74;; The two tests below check that we must fold load + scalar_to_vector75;; + ins_subvec+ zext into only a single vmovss or vmovsd or vinsertps from memory76 77define <8 x float> @mov00(<8 x float> %v, ptr %ptr) nounwind {78; CHECK-LABEL: mov00:79; CHECK: # %bb.0:80; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero81; CHECK-NEXT: retq82;83; CHECK_O0-LABEL: mov00:84; CHECK_O0: # %bb.0:85; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero86; CHECK_O0-NEXT: # kill: def $ymm0 killed $xmm087; CHECK_O0-NEXT: retq88 %val = load float, ptr %ptr89 %i0 = insertelement <8 x float> zeroinitializer, float %val, i32 090 ret <8 x float> %i091}92 93define <4 x double> @mov01(<4 x double> %v, ptr %ptr) nounwind {94; CHECK-LABEL: mov01:95; CHECK: # %bb.0:96; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero97; CHECK-NEXT: retq98;99; CHECK_O0-LABEL: mov01:100; CHECK_O0: # %bb.0:101; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero102; CHECK_O0-NEXT: # kill: def $ymm0 killed $xmm0103; CHECK_O0-NEXT: retq104 %val = load double, ptr %ptr105 %i0 = insertelement <4 x double> zeroinitializer, double %val, i32 0106 ret <4 x double> %i0107}108 109define void @storev16i16(<16 x i16> %a) nounwind {110; CHECK-LABEL: storev16i16:111; CHECK: # %bb.0:112; CHECK-NEXT: vmovaps %ymm0, (%rax)113;114; CHECK_O0-LABEL: storev16i16:115; CHECK_O0: # %bb.0:116; CHECK_O0-NEXT: # implicit-def: $rax117; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)118 store <16 x i16> %a, ptr undef, align 32119 unreachable120}121 122define void @storev16i16_01(<16 x i16> %a) nounwind {123; CHECK-LABEL: storev16i16_01:124; CHECK: # %bb.0:125; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)126; CHECK-NEXT: vmovups %xmm0, (%rax)127;128; CHECK_O0-LABEL: storev16i16_01:129; CHECK_O0: # %bb.0:130; CHECK_O0-NEXT: # implicit-def: $rax131; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)132 store <16 x i16> %a, ptr undef, align 4133 unreachable134}135 136define void @storev32i8(<32 x i8> %a) nounwind {137; CHECK-LABEL: storev32i8:138; CHECK: # %bb.0:139; CHECK-NEXT: vmovaps %ymm0, (%rax)140;141; CHECK_O0-LABEL: storev32i8:142; CHECK_O0: # %bb.0:143; CHECK_O0-NEXT: # implicit-def: $rax144; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)145 store <32 x i8> %a, ptr undef, align 32146 unreachable147}148 149define void @storev32i8_01(<32 x i8> %a) nounwind {150; CHECK-LABEL: storev32i8_01:151; CHECK: # %bb.0:152; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)153; CHECK-NEXT: vmovups %xmm0, (%rax)154;155; CHECK_O0-LABEL: storev32i8_01:156; CHECK_O0: # %bb.0:157; CHECK_O0-NEXT: # implicit-def: $rax158; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)159 store <32 x i8> %a, ptr undef, align 4160 unreachable161}162 163; It is faster to make two saves, if the data is already in xmm registers. For164; example, after making an integer operation.165define void @double_save(<4 x i32> %A, <4 x i32> %B, ptr %P) nounwind ssp {166; CHECK-LABEL: double_save:167; CHECK: # %bb.0:168; CHECK-NEXT: vmovaps %xmm1, 16(%rdi)169; CHECK-NEXT: vmovaps %xmm0, (%rdi)170; CHECK-NEXT: retq171;172; CHECK_O0-LABEL: double_save:173; CHECK_O0: # %bb.0:174; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2175; CHECK_O0-NEXT: # implicit-def: $ymm0176; CHECK_O0-NEXT: vmovaps %xmm2, %xmm0177; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0178; CHECK_O0-NEXT: vmovdqu %ymm0, (%rdi)179; CHECK_O0-NEXT: vzeroupper180; CHECK_O0-NEXT: retq181 %Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>182 store <8 x i32> %Z, ptr %P, align 16183 ret void184}185 186define void @double_save_volatile(<4 x i32> %A, <4 x i32> %B, ptr %P) nounwind {187; CHECK-LABEL: double_save_volatile:188; CHECK: # %bb.0:189; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0190; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0191; CHECK-NEXT: vmovups %ymm0, (%rdi)192; CHECK-NEXT: vzeroupper193; CHECK-NEXT: retq194;195; CHECK_O0-LABEL: double_save_volatile:196; CHECK_O0: # %bb.0:197; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2198; CHECK_O0-NEXT: # implicit-def: $ymm0199; CHECK_O0-NEXT: vmovaps %xmm2, %xmm0200; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0201; CHECK_O0-NEXT: vmovdqu %ymm0, (%rdi)202; CHECK_O0-NEXT: vzeroupper203; CHECK_O0-NEXT: retq204 %Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>205 store volatile <8 x i32> %Z, ptr %P, align 16206 ret void207}208 209declare void @llvm.x86.avx.maskstore.ps.256(ptr, <8 x i32>, <8 x float>) nounwind210 211define void @f_f() nounwind {212; CHECK-LABEL: f_f:213; CHECK: # %bb.0: # %allocas214; CHECK-NEXT: xorl %eax, %eax215; CHECK-NEXT: testb %al, %al216; CHECK-NEXT: jne .LBB9_2217; CHECK-NEXT: # %bb.1: # %cif_mask_all218; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed219; CHECK-NEXT: xorl %eax, %eax220; CHECK-NEXT: testb %al, %al221; CHECK-NEXT: jne .LBB9_4222; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all223; CHECK-NEXT: vmovss {{.*#+}} xmm0 = [4294967295,0,0,0]224; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)225; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check226;227; CHECK_O0-LABEL: f_f:228; CHECK_O0: # %bb.0: # %allocas229; CHECK_O0-NEXT: # implicit-def: $al230; CHECK_O0-NEXT: testb $1, %al231; CHECK_O0-NEXT: jne .LBB9_1232; CHECK_O0-NEXT: jmp .LBB9_2233; CHECK_O0-NEXT: .LBB9_1: # %cif_mask_all234; CHECK_O0-NEXT: .LBB9_2: # %cif_mask_mixed235; CHECK_O0-NEXT: # implicit-def: $al236; CHECK_O0-NEXT: testb $1, %al237; CHECK_O0-NEXT: jne .LBB9_3238; CHECK_O0-NEXT: jmp .LBB9_4239; CHECK_O0-NEXT: .LBB9_3: # %cif_mixed_test_all240; CHECK_O0-NEXT: vmovdqa {{.*#+}} xmm0 = [4294967295,0,0,0]241; CHECK_O0-NEXT: vmovdqa %xmm0, %xmm0242; CHECK_O0-NEXT: # kill: def $ymm0 killed $xmm0243; CHECK_O0-NEXT: # implicit-def: $rax244; CHECK_O0-NEXT: # implicit-def: $ymm1245; CHECK_O0-NEXT: vmaskmovps %ymm1, %ymm0, (%rax)246; CHECK_O0-NEXT: .LBB9_4: # %cif_mixed_test_any_check247allocas:248 br i1 undef, label %cif_mask_all, label %cif_mask_mixed249 250cif_mask_all:251 unreachable252 253cif_mask_mixed:254 br i1 undef, label %cif_mixed_test_all, label %cif_mixed_test_any_check255 256cif_mixed_test_all:257 call void @llvm.x86.avx.maskstore.ps.256(ptr undef, <8 x i32> <i32 -1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <8 x float> undef) nounwind258 unreachable259 260cif_mixed_test_any_check:261 unreachable262}263 264define void @add8i32(ptr %ret, ptr %bp) nounwind {265; CHECK-LABEL: add8i32:266; CHECK: # %bb.0:267; CHECK-NEXT: vmovups (%rsi), %xmm0268; CHECK-NEXT: vmovups 16(%rsi), %xmm1269; CHECK-NEXT: vmovups %xmm1, 16(%rdi)270; CHECK-NEXT: vmovups %xmm0, (%rdi)271; CHECK-NEXT: retq272;273; CHECK_O0-LABEL: add8i32:274; CHECK_O0: # %bb.0:275; CHECK_O0-NEXT: vmovdqu (%rsi), %xmm2276; CHECK_O0-NEXT: vmovdqu 16(%rsi), %xmm1277; CHECK_O0-NEXT: # implicit-def: $ymm0278; CHECK_O0-NEXT: vmovaps %xmm2, %xmm0279; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0280; CHECK_O0-NEXT: vmovdqu %ymm0, (%rdi)281; CHECK_O0-NEXT: vzeroupper282; CHECK_O0-NEXT: retq283 %b = load <8 x i32>, ptr %bp, align 1284 %x = add <8 x i32> zeroinitializer, %b285 store <8 x i32> %x, ptr %ret, align 1286 ret void287}288 289define void @add4i64a64(ptr %ret, ptr %bp) nounwind {290; CHECK-LABEL: add4i64a64:291; CHECK: # %bb.0:292; CHECK-NEXT: vmovaps (%rsi), %ymm0293; CHECK-NEXT: vmovaps %ymm0, (%rdi)294; CHECK-NEXT: vzeroupper295; CHECK-NEXT: retq296;297; CHECK_O0-LABEL: add4i64a64:298; CHECK_O0: # %bb.0:299; CHECK_O0-NEXT: vmovaps (%rsi), %ymm0300; CHECK_O0-NEXT: vmovdqa %ymm0, (%rdi)301; CHECK_O0-NEXT: vzeroupper302; CHECK_O0-NEXT: retq303 %b = load <4 x i64>, ptr %bp, align 64304 %x = add <4 x i64> zeroinitializer, %b305 store <4 x i64> %x, ptr %ret, align 64306 ret void307}308 309define void @add4i64a16(ptr %ret, ptr %bp) nounwind {310; CHECK-LABEL: add4i64a16:311; CHECK: # %bb.0:312; CHECK-NEXT: vmovaps (%rsi), %xmm0313; CHECK-NEXT: vmovaps 16(%rsi), %xmm1314; CHECK-NEXT: vmovaps %xmm1, 16(%rdi)315; CHECK-NEXT: vmovaps %xmm0, (%rdi)316; CHECK-NEXT: retq317;318; CHECK_O0-LABEL: add4i64a16:319; CHECK_O0: # %bb.0:320; CHECK_O0-NEXT: vmovdqa (%rsi), %xmm2321; CHECK_O0-NEXT: vmovdqa 16(%rsi), %xmm1322; CHECK_O0-NEXT: # implicit-def: $ymm0323; CHECK_O0-NEXT: vmovaps %xmm2, %xmm0324; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0325; CHECK_O0-NEXT: vmovdqu %ymm0, (%rdi)326; CHECK_O0-NEXT: vzeroupper327; CHECK_O0-NEXT: retq328 %b = load <4 x i64>, ptr %bp, align 16329 %x = add <4 x i64> zeroinitializer, %b330 store <4 x i64> %x, ptr %ret, align 16331 ret void332}333 334; This used to crash.335; v2i128 may not be a "simple" (MVT) type, but we can split that.336; This example gets split further in legalization.337 338define void @PR43916(<2 x i128> %y, ptr %z) {339; CHECK-LABEL: PR43916:340; CHECK: # %bb.0:341; CHECK-NEXT: movq %rcx, 24(%r8)342; CHECK-NEXT: movq %rdx, 16(%r8)343; CHECK-NEXT: movq %rsi, 8(%r8)344; CHECK-NEXT: movq %rdi, (%r8)345; CHECK-NEXT: retq346;347; CHECK_O0-LABEL: PR43916:348; CHECK_O0: # %bb.0:349; CHECK_O0-NEXT: movq %rdi, (%r8)350; CHECK_O0-NEXT: movq %rsi, 8(%r8)351; CHECK_O0-NEXT: movq %rdx, 16(%r8)352; CHECK_O0-NEXT: movq %rcx, 24(%r8)353; CHECK_O0-NEXT: retq354 store <2 x i128> %y, ptr %z, align 16355 ret void356}357