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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s3 4;;; Shift left5define <8 x i32> @vshift00(<8 x i32> %a) {6; CHECK-LABEL: vshift00:7; CHECK: # %bb.0:8; CHECK-NEXT: vpslld $2, %xmm0, %xmm19; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm010; CHECK-NEXT: vpslld $2, %xmm0, %xmm011; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm012; CHECK-NEXT: retq13 %s = shl <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>14 ret <8 x i32> %s15}16 17define <16 x i16> @vshift01(<16 x i16> %a) {18; CHECK-LABEL: vshift01:19; CHECK: # %bb.0:20; CHECK-NEXT: vpsllw $2, %xmm0, %xmm121; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm022; CHECK-NEXT: vpsllw $2, %xmm0, %xmm023; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm024; CHECK-NEXT: retq25 %s = shl <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>26 ret <16 x i16> %s27}28 29define <4 x i64> @vshift02(<4 x i64> %a) {30; CHECK-LABEL: vshift02:31; CHECK: # %bb.0:32; CHECK-NEXT: vpsllq $2, %xmm0, %xmm133; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm034; CHECK-NEXT: vpsllq $2, %xmm0, %xmm035; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm036; CHECK-NEXT: retq37 %s = shl <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>38 ret <4 x i64> %s39}40 41;;; Logical Shift right42define <8 x i32> @vshift03(<8 x i32> %a) {43; CHECK-LABEL: vshift03:44; CHECK: # %bb.0:45; CHECK-NEXT: vpsrld $2, %xmm0, %xmm146; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm047; CHECK-NEXT: vpsrld $2, %xmm0, %xmm048; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm049; CHECK-NEXT: retq50 %s = lshr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>51 ret <8 x i32> %s52}53 54define <16 x i16> @vshift04(<16 x i16> %a) {55; CHECK-LABEL: vshift04:56; CHECK: # %bb.0:57; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm158; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm059; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm060; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm061; CHECK-NEXT: retq62 %s = lshr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>63 ret <16 x i16> %s64}65 66define <4 x i64> @vshift05(<4 x i64> %a) {67; CHECK-LABEL: vshift05:68; CHECK: # %bb.0:69; CHECK-NEXT: vpsrlq $2, %xmm0, %xmm170; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm071; CHECK-NEXT: vpsrlq $2, %xmm0, %xmm072; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm073; CHECK-NEXT: retq74 %s = lshr <4 x i64> %a, <i64 2, i64 2, i64 2, i64 2>75 ret <4 x i64> %s76}77 78;;; Arithmetic Shift right79define <8 x i32> @vshift06(<8 x i32> %a) {80; CHECK-LABEL: vshift06:81; CHECK: # %bb.0:82; CHECK-NEXT: vpsrad $2, %xmm0, %xmm183; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm084; CHECK-NEXT: vpsrad $2, %xmm0, %xmm085; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm086; CHECK-NEXT: retq87 %s = ashr <8 x i32> %a, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>88 ret <8 x i32> %s89}90 91define <16 x i16> @vshift07(<16 x i16> %a) {92; CHECK-LABEL: vshift07:93; CHECK: # %bb.0:94; CHECK-NEXT: vpsraw $2, %xmm0, %xmm195; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm096; CHECK-NEXT: vpsraw $2, %xmm0, %xmm097; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm098; CHECK-NEXT: retq99 %s = ashr <16 x i16> %a, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>100 ret <16 x i16> %s101}102 103define <32 x i8> @vshift09(<32 x i8> %a) {104; CHECK-LABEL: vshift09:105; CHECK: # %bb.0:106; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1107; CHECK-NEXT: vpsrlw $2, %xmm1, %xmm1108; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]109; CHECK-NEXT: vpand %xmm2, %xmm1, %xmm1110; CHECK-NEXT: vbroadcastss {{.*#+}} xmm3 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]111; CHECK-NEXT: vpxor %xmm3, %xmm1, %xmm1112; CHECK-NEXT: vpsubb %xmm3, %xmm1, %xmm1113; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm0114; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0115; CHECK-NEXT: vpxor %xmm3, %xmm0, %xmm0116; CHECK-NEXT: vpsubb %xmm3, %xmm0, %xmm0117; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0118; CHECK-NEXT: retq119 %s = ashr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>120 ret <32 x i8> %s121}122 123define <32 x i8> @vshift10(<32 x i8> %a) {124; CHECK-LABEL: vshift10:125; CHECK: # %bb.0:126; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1127; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2128; CHECK-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1129; CHECK-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0130; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0131; CHECK-NEXT: retq132 %s = ashr <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>133 ret <32 x i8> %s134}135 136define <32 x i8> @vshift11(<32 x i8> %a) {137; CHECK-LABEL: vshift11:138; CHECK: # %bb.0:139; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm1140; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0141; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm0142; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0143; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0144; CHECK-NEXT: retq145 %s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>146 ret <32 x i8> %s147}148 149define <32 x i8> @vshift12(<32 x i8> %a) {150; CHECK-LABEL: vshift12:151; CHECK: # %bb.0:152; CHECK-NEXT: vpsllw $2, %xmm0, %xmm1153; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0154; CHECK-NEXT: vpsllw $2, %xmm0, %xmm0155; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0156; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0157; CHECK-NEXT: retq158 %s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>159 ret <32 x i8> %s160}161 162;;; Support variable shifts163define <8 x i32> @vshift08(<8 x i32> %a) {164; CHECK-LABEL: vshift08:165; CHECK: # %bb.0:166; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1167; CHECK-NEXT: vpslld $23, %xmm1, %xmm1168; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [1065353216,1065353216,1065353216,1065353216]169; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1170; CHECK-NEXT: vpslld $23, %xmm0, %xmm0171; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0172; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0173; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0174; CHECK-NEXT: retq175 %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a176 ret <8 x i32> %bitop177}178 179define <8 x i32> @vshift08_add(<8 x i32> %a, <8 x i32> %y) {180; CHECK-LABEL: vshift08_add:181; CHECK: # %bb.0:182; CHECK-NEXT: vpslld $23, %xmm0, %xmm2183; CHECK-NEXT: vbroadcastss {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]184; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm2185; CHECK-NEXT: vcvttps2dq %xmm2, %xmm2186; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0187; CHECK-NEXT: vpslld $23, %xmm0, %xmm0188; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0189; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0190; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm3191; CHECK-NEXT: vpaddd %xmm3, %xmm0, %xmm0192; CHECK-NEXT: vpaddd %xmm1, %xmm2, %xmm1193; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0194; CHECK-NEXT: retq195 %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a196 %r = add <8 x i32> %bitop, %y197 ret <8 x i32> %r198}199 200; PR15141201define <4 x i32> @vshift13(<4 x i32> %in) {202; CHECK-LABEL: vshift13:203; CHECK: # %bb.0:204; CHECK-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,2,4,16]205; CHECK-NEXT: retq206 %T = shl <4 x i32> %in, <i32 0, i32 1, i32 2, i32 4>207 ret <4 x i32> %T208}209 210;;; Uses shifts for sign extension211define <16 x i16> @sext_v16i16(<16 x i16> %a) {212; CHECK-LABEL: sext_v16i16:213; CHECK: # %bb.0:214; CHECK-NEXT: vpsllw $8, %xmm0, %xmm1215; CHECK-NEXT: vpsraw $8, %xmm1, %xmm1216; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0217; CHECK-NEXT: vpsllw $8, %xmm0, %xmm0218; CHECK-NEXT: vpsraw $8, %xmm0, %xmm0219; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0220; CHECK-NEXT: retq221 %b = trunc <16 x i16> %a to <16 x i8>222 %c = sext <16 x i8> %b to <16 x i16>223 ret <16 x i16> %c224}225 226define <8 x i32> @sext_v8i32(<8 x i32> %a) {227; CHECK-LABEL: sext_v8i32:228; CHECK: # %bb.0:229; CHECK-NEXT: vpslld $16, %xmm0, %xmm1230; CHECK-NEXT: vpsrad $16, %xmm1, %xmm1231; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0232; CHECK-NEXT: vpslld $16, %xmm0, %xmm0233; CHECK-NEXT: vpsrad $16, %xmm0, %xmm0234; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0235; CHECK-NEXT: retq236 %b = trunc <8 x i32> %a to <8 x i16>237 %c = sext <8 x i16> %b to <8 x i32>238 ret <8 x i32> %c239}240