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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s3 4define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {5; CHECK-LABEL: A:6; CHECK: # %bb.0:7; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm08; CHECK-NEXT: retq9 %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3>10 ret <8 x float> %shuffle11}12 13define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {14; CHECK-LABEL: B:15; CHECK: # %bb.0:16; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm017; CHECK-NEXT: retq18 %shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 1>19 ret <4 x double> %shuffle20}21 22declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone23declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone24 25define void @insert_crash() nounwind {26; CHECK-LABEL: insert_crash:27; CHECK: # %bb.0: # %allocas28; CHECK-NEXT: vxorpd %xmm0, %xmm0, %xmm029; CHECK-NEXT: vminpd %xmm0, %xmm0, %xmm030; CHECK-NEXT: vminsd %xmm0, %xmm0, %xmm031; CHECK-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm032; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,0,0]33; CHECK-NEXT: vmovups %xmm0, (%rax)34; CHECK-NEXT: retq35allocas:36 %v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>37 %ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>38 %vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind39 %ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind40 %ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 041 %double2float = fptrunc double %ret.i1.i.i464 to float42 %smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 343 %blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>44 store <4 x i32> %blendAsInt.i503, ptr undef, align 445 ret void46}47 48;; DAG Combine must remove useless vinsertf128 instructions49 50define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {51; CHECK-LABEL: DAGCombineA:52; CHECK: # %bb.0:53; CHECK-NEXT: retq54 %t1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>55 %t2 = shufflevector <8 x i32> %t1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>56 ret <4 x i32> %t257}58 59define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {60; CHECK-LABEL: DAGCombineB:61; CHECK: # %bb.0:62; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm263; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm164; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm365; CHECK-NEXT: vpaddd %xmm1, %xmm3, %xmm166; CHECK-NEXT: vpaddd %xmm3, %xmm1, %xmm167; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm068; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm069; CHECK-NEXT: retq70 %t1 = add <8 x i32> %v1, %v271 %t2 = add <8 x i32> %t1, %v172 ret <8 x i32> %t273}74 75define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) {76; CHECK-LABEL: insert_undef_pd:77; CHECK: # %bb.0:78; CHECK-NEXT: vmovaps %xmm1, %xmm079; CHECK-NEXT: retq80%res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0)81ret <4 x double> %res82}83declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone84 85define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) {86; CHECK-LABEL: insert_undef_ps:87; CHECK: # %bb.0:88; CHECK-NEXT: vmovaps %xmm1, %xmm089; CHECK-NEXT: retq90%res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0)91ret <8 x float> %res92}93declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone94 95define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) {96; CHECK-LABEL: insert_undef_si:97; CHECK: # %bb.0:98; CHECK-NEXT: vmovaps %xmm1, %xmm099; CHECK-NEXT: retq100%res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0)101ret <8 x i32> %res102}103declare <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32>, <4 x i32>, i8) nounwind readnone104 105; rdar://10643481106define <8 x float> @vinsertf128_combine(ptr nocapture %f) nounwind uwtable readonly ssp {107; CHECK-LABEL: vinsertf128_combine:108; CHECK: # %bb.0:109; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0110; CHECK-NEXT: retq111 %add.ptr = getelementptr inbounds float, ptr %f, i64 4112 %t1 = load <4 x float>, ptr %add.ptr, align 16113 %t2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %t1, i8 1)114 ret <8 x float> %t2115}116 117; rdar://11076953118define <8 x float> @vinsertf128_ucombine(ptr nocapture %f) nounwind uwtable readonly ssp {119; CHECK-LABEL: vinsertf128_ucombine:120; CHECK: # %bb.0:121; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0122; CHECK-NEXT: retq123 %add.ptr = getelementptr inbounds float, ptr %f, i64 4124 %t1 = load <4 x float>, ptr %add.ptr, align 8125 %t2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %t1, i8 1)126 ret <8 x float> %t2127}128 129