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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s3 4define i64 @test_x86_avx512_vcvttsd2si64(<2 x double> %a0) {5; CHECK-LABEL: test_x86_avx512_vcvttsd2si64:6; CHECK: # %bb.0:7; CHECK-NEXT: vcvttsd2sis %xmm0, %rcx # encoding: [0x62,0xf5,0xff,0x08,0x6d,0xc8]8; CHECK-NEXT: vcvttsd2sis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xff,0x18,0x6d,0xc0]9; CHECK-NEXT: addq %rcx, %rax # encoding: [0x48,0x01,0xc8]10; CHECK-NEXT: retq # encoding: [0xc3]11 %res0 = call i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double> %a0, i32 4) ;12 %res1 = call i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double> %a0, i32 8) ;13 %res2 = add i64 %res0, %res114 ret i64 %res215}16declare i64 @llvm.x86.avx10.vcvttsd2sis64(<2 x double>, i32) nounwind readnone17 18define i64 @test_x86_avx512_vcvttsd2usi64(<2 x double> %a0) {19; CHECK-LABEL: test_x86_avx512_vcvttsd2usi64:20; CHECK: # %bb.0:21; CHECK-NEXT: vcvttsd2usis %xmm0, %rcx # encoding: [0x62,0xf5,0xff,0x08,0x6c,0xc8]22; CHECK-NEXT: vcvttsd2usis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xff,0x18,0x6c,0xc0]23; CHECK-NEXT: addq %rcx, %rax # encoding: [0x48,0x01,0xc8]24; CHECK-NEXT: retq # encoding: [0xc3]25 %res0 = call i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double> %a0, i32 4) ;26 %res1 = call i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double> %a0, i32 8) ;27 %res2 = add i64 %res0, %res128 ret i64 %res229}30declare i64 @llvm.x86.avx10.vcvttsd2usis64(<2 x double>, i32) nounwind readnone31 32define i64 @test_x86_avx512_vcvttss2sis64(<4 x float> %a0) {33; CHECK-LABEL: test_x86_avx512_vcvttss2sis64:34; CHECK: # %bb.0:35; CHECK-NEXT: vcvttss2sis %xmm0, %rcx # encoding: [0x62,0xf5,0xfe,0x08,0x6d,0xc8]36; CHECK-NEXT: vcvttss2sis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xfe,0x18,0x6d,0xc0]37; CHECK-NEXT: addq %rcx, %rax # encoding: [0x48,0x01,0xc8]38; CHECK-NEXT: retq # encoding: [0xc3]39 %res0 = call i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float> %a0, i32 4) ;40 %res1 = call i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float> %a0, i32 8) ;41 %res2 = add i64 %res0, %res142 ret i64 %res243}44declare i64 @llvm.x86.avx10.vcvttss2sis64(<4 x float>, i32) nounwind readnone45 46define i64 @test_x86_avx512_vcvttss2usis64(<4 x float> %a0) {47; CHECK-LABEL: test_x86_avx512_vcvttss2usis64:48; CHECK: # %bb.0:49; CHECK-NEXT: vcvttss2usis %xmm0, %rcx # encoding: [0x62,0xf5,0xfe,0x08,0x6c,0xc8]50; CHECK-NEXT: vcvttss2usis {sae}, %xmm0, %rax # encoding: [0x62,0xf5,0xfe,0x18,0x6c,0xc0]51; CHECK-NEXT: addq %rcx, %rax # encoding: [0x48,0x01,0xc8]52; CHECK-NEXT: retq # encoding: [0xc3]53 %res0 = call i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float> %a0, i32 4) ;54 %res1 = call i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float> %a0, i32 8) ;55 %res2 = add i64 %res0, %res156 ret i64 %res257}58declare i64 @llvm.x86.avx10.vcvttss2usis64(<4 x float>, i32) nounwind readnone59