204 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -disable-peephole -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X863; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X644; RUN: llc < %s -disable-peephole -mtriple=i686-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=X865; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=X646 7define <16 x i16> @test_llvm_x86_avx2_pmovsxbw(ptr %a) {8; X86-LABEL: test_llvm_x86_avx2_pmovsxbw:9; X86: ## %bb.0:10; X86-NEXT: movl {{[0-9]+}}(%esp), %eax11; X86-NEXT: vpmovsxbw (%eax), %ymm012; X86-NEXT: retl13;14; X64-LABEL: test_llvm_x86_avx2_pmovsxbw:15; X64: ## %bb.0:16; X64-NEXT: vpmovsxbw (%rdi), %ymm017; X64-NEXT: retq18 %1 = load <16 x i8>, ptr %a, align 119 %2 = sext <16 x i8> %1 to <16 x i16>20 ret <16 x i16> %221}22 23define <8 x i32> @test_llvm_x86_avx2_pmovsxbd(ptr %a) {24; X86-LABEL: test_llvm_x86_avx2_pmovsxbd:25; X86: ## %bb.0:26; X86-NEXT: movl {{[0-9]+}}(%esp), %eax27; X86-NEXT: vpmovsxbd (%eax), %ymm028; X86-NEXT: retl29;30; X64-LABEL: test_llvm_x86_avx2_pmovsxbd:31; X64: ## %bb.0:32; X64-NEXT: vpmovsxbd (%rdi), %ymm033; X64-NEXT: retq34 %1 = load <16 x i8>, ptr %a, align 135 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>36 %3 = sext <8 x i8> %2 to <8 x i32>37 ret <8 x i32> %338}39 40define <4 x i64> @test_llvm_x86_avx2_pmovsxbq(ptr %a) {41; X86-LABEL: test_llvm_x86_avx2_pmovsxbq:42; X86: ## %bb.0:43; X86-NEXT: movl {{[0-9]+}}(%esp), %eax44; X86-NEXT: vpmovsxbq (%eax), %ymm045; X86-NEXT: retl46;47; X64-LABEL: test_llvm_x86_avx2_pmovsxbq:48; X64: ## %bb.0:49; X64-NEXT: vpmovsxbq (%rdi), %ymm050; X64-NEXT: retq51 %1 = load <16 x i8>, ptr %a, align 152 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>53 %3 = sext <4 x i8> %2 to <4 x i64>54 ret <4 x i64> %355}56 57define <8 x i32> @test_llvm_x86_avx2_pmovsxwd(ptr %a) {58; X86-LABEL: test_llvm_x86_avx2_pmovsxwd:59; X86: ## %bb.0:60; X86-NEXT: movl {{[0-9]+}}(%esp), %eax61; X86-NEXT: vpmovsxwd (%eax), %ymm062; X86-NEXT: retl63;64; X64-LABEL: test_llvm_x86_avx2_pmovsxwd:65; X64: ## %bb.0:66; X64-NEXT: vpmovsxwd (%rdi), %ymm067; X64-NEXT: retq68 %1 = load <8 x i16>, ptr %a, align 169 %2 = sext <8 x i16> %1 to <8 x i32>70 ret <8 x i32> %271}72 73define <4 x i64> @test_llvm_x86_avx2_pmovsxwq(ptr %a) {74; X86-LABEL: test_llvm_x86_avx2_pmovsxwq:75; X86: ## %bb.0:76; X86-NEXT: movl {{[0-9]+}}(%esp), %eax77; X86-NEXT: vpmovsxwq (%eax), %ymm078; X86-NEXT: retl79;80; X64-LABEL: test_llvm_x86_avx2_pmovsxwq:81; X64: ## %bb.0:82; X64-NEXT: vpmovsxwq (%rdi), %ymm083; X64-NEXT: retq84 %1 = load <8 x i16>, ptr %a, align 185 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>86 %3 = sext <4 x i16> %2 to <4 x i64>87 ret <4 x i64> %388}89 90define <4 x i64> @test_llvm_x86_avx2_pmovsxdq(ptr %a) {91; X86-LABEL: test_llvm_x86_avx2_pmovsxdq:92; X86: ## %bb.0:93; X86-NEXT: movl {{[0-9]+}}(%esp), %eax94; X86-NEXT: vpmovsxdq (%eax), %ymm095; X86-NEXT: retl96;97; X64-LABEL: test_llvm_x86_avx2_pmovsxdq:98; X64: ## %bb.0:99; X64-NEXT: vpmovsxdq (%rdi), %ymm0100; X64-NEXT: retq101 %1 = load <4 x i32>, ptr %a, align 1102 %2 = sext <4 x i32> %1 to <4 x i64>103 ret <4 x i64> %2104}105 106define <16 x i16> @test_llvm_x86_avx2_pmovzxbw(ptr %a) {107; X86-LABEL: test_llvm_x86_avx2_pmovzxbw:108; X86: ## %bb.0:109; X86-NEXT: movl {{[0-9]+}}(%esp), %eax110; X86-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero111; X86-NEXT: retl112;113; X64-LABEL: test_llvm_x86_avx2_pmovzxbw:114; X64: ## %bb.0:115; X64-NEXT: vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero116; X64-NEXT: retq117 %1 = load <16 x i8>, ptr %a, align 1118 %2 = zext <16 x i8> %1 to <16 x i16>119 ret <16 x i16> %2120}121 122define <8 x i32> @test_llvm_x86_avx2_pmovzxbd(ptr %a) {123; X86-LABEL: test_llvm_x86_avx2_pmovzxbd:124; X86: ## %bb.0:125; X86-NEXT: movl {{[0-9]+}}(%esp), %eax126; X86-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero127; X86-NEXT: retl128;129; X64-LABEL: test_llvm_x86_avx2_pmovzxbd:130; X64: ## %bb.0:131; X64-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero132; X64-NEXT: retq133 %1 = load <16 x i8>, ptr %a, align 1134 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>135 %3 = zext <8 x i8> %2 to <8 x i32>136 ret <8 x i32> %3137}138 139define <4 x i64> @test_llvm_x86_avx2_pmovzxbq(ptr %a) {140; X86-LABEL: test_llvm_x86_avx2_pmovzxbq:141; X86: ## %bb.0:142; X86-NEXT: movl {{[0-9]+}}(%esp), %eax143; X86-NEXT: vpmovzxbq {{.*#+}} ymm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero144; X86-NEXT: retl145;146; X64-LABEL: test_llvm_x86_avx2_pmovzxbq:147; X64: ## %bb.0:148; X64-NEXT: vpmovzxbq {{.*#+}} ymm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero149; X64-NEXT: retq150 %1 = load <16 x i8>, ptr %a, align 1151 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>152 %3 = zext <4 x i8> %2 to <4 x i64>153 ret <4 x i64> %3154}155 156define <8 x i32> @test_llvm_x86_avx2_pmovzxwd(ptr %a) {157; X86-LABEL: test_llvm_x86_avx2_pmovzxwd:158; X86: ## %bb.0:159; X86-NEXT: movl {{[0-9]+}}(%esp), %eax160; X86-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero161; X86-NEXT: retl162;163; X64-LABEL: test_llvm_x86_avx2_pmovzxwd:164; X64: ## %bb.0:165; X64-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero166; X64-NEXT: retq167 %1 = load <8 x i16>, ptr %a, align 1168 %2 = zext <8 x i16> %1 to <8 x i32>169 ret <8 x i32> %2170}171 172define <4 x i64> @test_llvm_x86_avx2_pmovzxwq(ptr %a) {173; X86-LABEL: test_llvm_x86_avx2_pmovzxwq:174; X86: ## %bb.0:175; X86-NEXT: movl {{[0-9]+}}(%esp), %eax176; X86-NEXT: vpmovzxwq {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero177; X86-NEXT: retl178;179; X64-LABEL: test_llvm_x86_avx2_pmovzxwq:180; X64: ## %bb.0:181; X64-NEXT: vpmovzxwq {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero182; X64-NEXT: retq183 %1 = load <8 x i16>, ptr %a, align 1184 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>185 %3 = zext <4 x i16> %2 to <4 x i64>186 ret <4 x i64> %3187}188 189define <4 x i64> @test_llvm_x86_avx2_pmovzxdq(ptr %a) {190; X86-LABEL: test_llvm_x86_avx2_pmovzxdq:191; X86: ## %bb.0:192; X86-NEXT: movl {{[0-9]+}}(%esp), %eax193; X86-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero194; X86-NEXT: retl195;196; X64-LABEL: test_llvm_x86_avx2_pmovzxdq:197; X64: ## %bb.0:198; X64-NEXT: vpmovzxdq {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero199; X64-NEXT: retq200 %1 = load <4 x i32>, ptr %a, align 1201 %2 = zext <4 x i32> %1 to <4 x i64>202 ret <4 x i64> %2203}204