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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,X86,X86-SLOW3; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,X86,X86-FAST-ALL4; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,X86,X86-FAST-PERLANE5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,X64,X64-SLOW6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,X64,X64-FAST-ALL7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,X64,X64-FAST-PERLANE8 9; AVX2 Logical Shift Left10 11define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {12; CHECK-LABEL: test_sllw_1:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: ret{{[l|q]}}15entry:16 %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>17 ret <16 x i16> %shl18}19 20define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {21; CHECK-LABEL: test_sllw_2:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: vpaddw %ymm0, %ymm0, %ymm024; CHECK-NEXT: ret{{[l|q]}}25entry:26 %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>27 ret <16 x i16> %shl28}29 30define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {31; CHECK-LABEL: test_sllw_3:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: vpsllw $15, %ymm0, %ymm034; CHECK-NEXT: ret{{[l|q]}}35entry:36 %shl = shl <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>37 ret <16 x i16> %shl38}39 40define <8 x i32> @test_slld_1(<8 x i32> %InVec) {41; CHECK-LABEL: test_slld_1:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: ret{{[l|q]}}44entry:45 %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>46 ret <8 x i32> %shl47}48 49define <8 x i32> @test_slld_2(<8 x i32> %InVec) {50; CHECK-LABEL: test_slld_2:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: vpaddd %ymm0, %ymm0, %ymm053; CHECK-NEXT: ret{{[l|q]}}54entry:55 %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>56 ret <8 x i32> %shl57}58 59define <8 x i32> @test_vpslld_var(i32 %shift) {60; X86-LABEL: test_vpslld_var:61; X86: # %bb.0:62; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero63; X86-NEXT: vpmovzxbd {{.*#+}} ymm1 = [192,193,194,195,196,197,198,199]64; X86-NEXT: vpslld %xmm0, %ymm1, %ymm065; X86-NEXT: retl66;67; X64-LABEL: test_vpslld_var:68; X64: # %bb.0:69; X64-NEXT: vmovd %edi, %xmm070; X64-NEXT: vpmovzxbd {{.*#+}} ymm1 = [192,193,194,195,196,197,198,199]71; X64-NEXT: vpslld %xmm0, %ymm1, %ymm072; X64-NEXT: retq73 %amt = insertelement <8 x i32> undef, i32 %shift, i32 074 %tmp = shl <8 x i32> <i32 192, i32 193, i32 194, i32 195, i32 196, i32 197, i32 198, i32 199>, %amt75 ret <8 x i32> %tmp76}77 78define <8 x i32> @test_slld_3(<8 x i32> %InVec) {79; CHECK-LABEL: test_slld_3:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: vpslld $31, %ymm0, %ymm082; CHECK-NEXT: ret{{[l|q]}}83entry:84 %shl = shl <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>85 ret <8 x i32> %shl86}87 88define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {89; CHECK-LABEL: test_sllq_1:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: ret{{[l|q]}}92entry:93 %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>94 ret <4 x i64> %shl95}96 97define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {98; CHECK-LABEL: test_sllq_2:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vpaddq %ymm0, %ymm0, %ymm0101; CHECK-NEXT: ret{{[l|q]}}102entry:103 %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>104 ret <4 x i64> %shl105}106 107define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {108; CHECK-LABEL: test_sllq_3:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: vpsllq $63, %ymm0, %ymm0111; CHECK-NEXT: ret{{[l|q]}}112entry:113 %shl = shl <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>114 ret <4 x i64> %shl115}116 117; AVX2 Arithmetic Shift118 119define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {120; CHECK-LABEL: test_sraw_1:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: ret{{[l|q]}}123entry:124 %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>125 ret <16 x i16> %shl126}127 128define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {129; CHECK-LABEL: test_sraw_2:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vpsraw $1, %ymm0, %ymm0132; CHECK-NEXT: ret{{[l|q]}}133entry:134 %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>135 ret <16 x i16> %shl136}137 138define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {139; CHECK-LABEL: test_sraw_3:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: vpsraw $15, %ymm0, %ymm0142; CHECK-NEXT: ret{{[l|q]}}143entry:144 %shl = ashr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>145 ret <16 x i16> %shl146}147 148define <8 x i32> @test_srad_1(<8 x i32> %InVec) {149; CHECK-LABEL: test_srad_1:150; CHECK: # %bb.0: # %entry151; CHECK-NEXT: ret{{[l|q]}}152entry:153 %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>154 ret <8 x i32> %shl155}156 157define <8 x i32> @test_srad_2(<8 x i32> %InVec) {158; CHECK-LABEL: test_srad_2:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vpsrad $1, %ymm0, %ymm0161; CHECK-NEXT: ret{{[l|q]}}162entry:163 %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>164 ret <8 x i32> %shl165}166 167define <8 x i32> @test_srad_3(<8 x i32> %InVec) {168; CHECK-LABEL: test_srad_3:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vpsrad $31, %ymm0, %ymm0171; CHECK-NEXT: ret{{[l|q]}}172entry:173 %shl = ashr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>174 ret <8 x i32> %shl175}176 177; SSE Logical Shift Right178 179define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {180; CHECK-LABEL: test_srlw_1:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: ret{{[l|q]}}183entry:184 %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>185 ret <16 x i16> %shl186}187 188define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {189; CHECK-LABEL: test_srlw_2:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vpsrlw $1, %ymm0, %ymm0192; CHECK-NEXT: ret{{[l|q]}}193entry:194 %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>195 ret <16 x i16> %shl196}197 198define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {199; CHECK-LABEL: test_srlw_3:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: vpsrlw $15, %ymm0, %ymm0202; CHECK-NEXT: ret{{[l|q]}}203entry:204 %shl = lshr <16 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>205 ret <16 x i16> %shl206}207 208define <8 x i32> @test_srld_1(<8 x i32> %InVec) {209; CHECK-LABEL: test_srld_1:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: ret{{[l|q]}}212entry:213 %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>214 ret <8 x i32> %shl215}216 217define <8 x i32> @test_srld_2(<8 x i32> %InVec) {218; CHECK-LABEL: test_srld_2:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0221; CHECK-NEXT: ret{{[l|q]}}222entry:223 %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>224 ret <8 x i32> %shl225}226 227define <8 x i32> @test_srld_3(<8 x i32> %InVec) {228; CHECK-LABEL: test_srld_3:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: vpsrld $31, %ymm0, %ymm0231; CHECK-NEXT: ret{{[l|q]}}232entry:233 %shl = lshr <8 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>234 ret <8 x i32> %shl235}236 237define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {238; CHECK-LABEL: test_srlq_1:239; CHECK: # %bb.0: # %entry240; CHECK-NEXT: ret{{[l|q]}}241entry:242 %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>243 ret <4 x i64> %shl244}245 246define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {247; CHECK-LABEL: test_srlq_2:248; CHECK: # %bb.0: # %entry249; CHECK-NEXT: vpsrlq $1, %ymm0, %ymm0250; CHECK-NEXT: ret{{[l|q]}}251entry:252 %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>253 ret <4 x i64> %shl254}255 256define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {257; CHECK-LABEL: test_srlq_3:258; CHECK: # %bb.0: # %entry259; CHECK-NEXT: vpsrlq $63, %ymm0, %ymm0260; CHECK-NEXT: ret{{[l|q]}}261entry:262 %shl = lshr <4 x i64> %InVec, <i64 63, i64 63, i64 63, i64 63>263 ret <4 x i64> %shl264}265 266define <4 x i32> @srl_trunc_and_v4i64(<4 x i32> %x, <4 x i64> %y) nounwind {267; X86-SLOW-LABEL: srl_trunc_and_v4i64:268; X86-SLOW: # %bb.0:269; X86-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2270; X86-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]271; X86-SLOW-NEXT: vbroadcastss {{.*#+}} xmm2 = [8,8,8,8]272; X86-SLOW-NEXT: vandps %xmm2, %xmm1, %xmm1273; X86-SLOW-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0274; X86-SLOW-NEXT: vzeroupper275; X86-SLOW-NEXT: retl276;277; X86-FAST-ALL-LABEL: srl_trunc_and_v4i64:278; X86-FAST-ALL: # %bb.0:279; X86-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,2,4,6,0,0,0,0]280; X86-FAST-ALL-NEXT: vpermd %ymm1, %ymm2, %ymm1281; X86-FAST-ALL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [8,8,8,8]282; X86-FAST-ALL-NEXT: vpand %xmm2, %xmm1, %xmm1283; X86-FAST-ALL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0284; X86-FAST-ALL-NEXT: vzeroupper285; X86-FAST-ALL-NEXT: retl286;287; X86-FAST-PERLANE-LABEL: srl_trunc_and_v4i64:288; X86-FAST-PERLANE: # %bb.0:289; X86-FAST-PERLANE-NEXT: vextractf128 $1, %ymm1, %xmm2290; X86-FAST-PERLANE-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]291; X86-FAST-PERLANE-NEXT: vbroadcastss {{.*#+}} xmm2 = [8,8,8,8]292; X86-FAST-PERLANE-NEXT: vandps %xmm2, %xmm1, %xmm1293; X86-FAST-PERLANE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0294; X86-FAST-PERLANE-NEXT: vzeroupper295; X86-FAST-PERLANE-NEXT: retl296;297; X64-SLOW-LABEL: srl_trunc_and_v4i64:298; X64-SLOW: # %bb.0:299; X64-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2300; X64-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]301; X64-SLOW-NEXT: vbroadcastss {{.*#+}} xmm2 = [8,8,8,8]302; X64-SLOW-NEXT: vandps %xmm2, %xmm1, %xmm1303; X64-SLOW-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0304; X64-SLOW-NEXT: vzeroupper305; X64-SLOW-NEXT: retq306;307; X64-FAST-ALL-LABEL: srl_trunc_and_v4i64:308; X64-FAST-ALL: # %bb.0:309; X64-FAST-ALL-NEXT: vpmovsxbd {{.*#+}} ymm2 = [0,2,4,6,0,0,0,0]310; X64-FAST-ALL-NEXT: vpermd %ymm1, %ymm2, %ymm1311; X64-FAST-ALL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [8,8,8,8]312; X64-FAST-ALL-NEXT: vpand %xmm2, %xmm1, %xmm1313; X64-FAST-ALL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0314; X64-FAST-ALL-NEXT: vzeroupper315; X64-FAST-ALL-NEXT: retq316;317; X64-FAST-PERLANE-LABEL: srl_trunc_and_v4i64:318; X64-FAST-PERLANE: # %bb.0:319; X64-FAST-PERLANE-NEXT: vextractf128 $1, %ymm1, %xmm2320; X64-FAST-PERLANE-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]321; X64-FAST-PERLANE-NEXT: vbroadcastss {{.*#+}} xmm2 = [8,8,8,8]322; X64-FAST-PERLANE-NEXT: vandps %xmm2, %xmm1, %xmm1323; X64-FAST-PERLANE-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0324; X64-FAST-PERLANE-NEXT: vzeroupper325; X64-FAST-PERLANE-NEXT: retq326 %and = and <4 x i64> %y, <i64 8, i64 8, i64 8, i64 8>327 %trunc = trunc <4 x i64> %and to <4 x i32>328 %sra = lshr <4 x i32> %x, %trunc329 ret <4 x i32> %sra330}331 332;333; Vectorized byte shifts334;335 336define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {337; CHECK-LABEL: shl_8i16:338; CHECK: # %bb.0:339; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero340; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero341; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0342; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]343; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]344; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0345; CHECK-NEXT: vzeroupper346; CHECK-NEXT: ret{{[l|q]}}347 %shl = shl <8 x i16> %r, %a348 ret <8 x i16> %shl349}350 351define <16 x i16> @shl_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {352; CHECK-LABEL: shl_16i16:353; CHECK: # %bb.0:354; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2355; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]356; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]357; CHECK-NEXT: vpsllvd %ymm3, %ymm4, %ymm3358; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3359; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]360; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]361; CHECK-NEXT: vpsllvd %ymm1, %ymm0, %ymm0362; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0363; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0364; CHECK-NEXT: ret{{[l|q]}}365 %shl = shl <16 x i16> %r, %a366 ret <16 x i16> %shl367}368 369define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {370; X86-LABEL: shl_32i8:371; X86: # %bb.0:372; X86-NEXT: vpsllw $5, %ymm1, %ymm1373; X86-NEXT: vpsllw $4, %ymm0, %ymm2374; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2375; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0376; X86-NEXT: vpsllw $2, %ymm0, %ymm2377; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2378; X86-NEXT: vpaddb %ymm1, %ymm1, %ymm1379; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0380; X86-NEXT: vpaddb %ymm0, %ymm0, %ymm2381; X86-NEXT: vpaddb %ymm1, %ymm1, %ymm1382; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0383; X86-NEXT: retl384;385; X64-LABEL: shl_32i8:386; X64: # %bb.0:387; X64-NEXT: vpsllw $5, %ymm1, %ymm1388; X64-NEXT: vpsllw $4, %ymm0, %ymm2389; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2390; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0391; X64-NEXT: vpsllw $2, %ymm0, %ymm2392; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2393; X64-NEXT: vpaddb %ymm1, %ymm1, %ymm1394; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0395; X64-NEXT: vpaddb %ymm0, %ymm0, %ymm2396; X64-NEXT: vpaddb %ymm1, %ymm1, %ymm1397; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0398; X64-NEXT: retq399 %shl = shl <32 x i8> %r, %a400 ret <32 x i8> %shl401}402 403define <8 x i16> @ashr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {404; CHECK-LABEL: ashr_8i16:405; CHECK: # %bb.0:406; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero407; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0408; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0409; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1410; CHECK-NEXT: vpackssdw %xmm1, %xmm0, %xmm0411; CHECK-NEXT: vzeroupper412; CHECK-NEXT: ret{{[l|q]}}413 %ashr = ashr <8 x i16> %r, %a414 ret <8 x i16> %ashr415}416 417define <16 x i16> @ashr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {418; CHECK-LABEL: ashr_16i16:419; CHECK: # %bb.0:420; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2421; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]422; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]423; CHECK-NEXT: vpsravd %ymm3, %ymm4, %ymm3424; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3425; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]426; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]427; CHECK-NEXT: vpsravd %ymm1, %ymm0, %ymm0428; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0429; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0430; CHECK-NEXT: ret{{[l|q]}}431 %ashr = ashr <16 x i16> %r, %a432 ret <16 x i16> %ashr433}434 435define <32 x i8> @ashr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {436; CHECK-LABEL: ashr_32i8:437; CHECK: # %bb.0:438; CHECK-NEXT: vpsllw $5, %ymm1, %ymm1439; CHECK-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]440; CHECK-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]441; CHECK-NEXT: vpsraw $4, %ymm3, %ymm4442; CHECK-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3443; CHECK-NEXT: vpsraw $2, %ymm3, %ymm4444; CHECK-NEXT: vpaddw %ymm2, %ymm2, %ymm5445; CHECK-NEXT: vpblendvb %ymm5, %ymm4, %ymm3, %ymm3446; CHECK-NEXT: vpsraw $1, %ymm3, %ymm4447; CHECK-NEXT: vpsllw $2, %ymm2, %ymm2448; CHECK-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2449; CHECK-NEXT: vpsrlw $8, %ymm2, %ymm2450; CHECK-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]451; CHECK-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]452; CHECK-NEXT: vpsraw $4, %ymm0, %ymm3453; CHECK-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0454; CHECK-NEXT: vpsraw $2, %ymm0, %ymm3455; CHECK-NEXT: vpaddw %ymm1, %ymm1, %ymm4456; CHECK-NEXT: vpblendvb %ymm4, %ymm3, %ymm0, %ymm0457; CHECK-NEXT: vpsraw $1, %ymm0, %ymm3458; CHECK-NEXT: vpsllw $2, %ymm1, %ymm1459; CHECK-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0460; CHECK-NEXT: vpsrlw $8, %ymm0, %ymm0461; CHECK-NEXT: vpackuswb %ymm2, %ymm0, %ymm0462; CHECK-NEXT: ret{{[l|q]}}463 %ashr = ashr <32 x i8> %r, %a464 ret <32 x i8> %ashr465}466 467define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind {468; CHECK-LABEL: lshr_8i16:469; CHECK: # %bb.0:470; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero471; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero472; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0473; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1474; CHECK-NEXT: vpackusdw %xmm1, %xmm0, %xmm0475; CHECK-NEXT: vzeroupper476; CHECK-NEXT: ret{{[l|q]}}477 %lshr = lshr <8 x i16> %r, %a478 ret <8 x i16> %lshr479}480 481define <16 x i16> @lshr_16i16(<16 x i16> %r, <16 x i16> %a) nounwind {482; CHECK-LABEL: lshr_16i16:483; CHECK: # %bb.0:484; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2485; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]486; CHECK-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]487; CHECK-NEXT: vpsrlvd %ymm3, %ymm4, %ymm3488; CHECK-NEXT: vpsrld $16, %ymm3, %ymm3489; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]490; CHECK-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]491; CHECK-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0492; CHECK-NEXT: vpsrld $16, %ymm0, %ymm0493; CHECK-NEXT: vpackusdw %ymm3, %ymm0, %ymm0494; CHECK-NEXT: ret{{[l|q]}}495 %lshr = lshr <16 x i16> %r, %a496 ret <16 x i16> %lshr497}498 499define <32 x i8> @lshr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {500; X86-LABEL: lshr_32i8:501; X86: # %bb.0:502; X86-NEXT: vpsllw $5, %ymm1, %ymm1503; X86-NEXT: vpsrlw $4, %ymm0, %ymm2504; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2505; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0506; X86-NEXT: vpsrlw $2, %ymm0, %ymm2507; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2508; X86-NEXT: vpaddb %ymm1, %ymm1, %ymm1509; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0510; X86-NEXT: vpsrlw $1, %ymm0, %ymm2511; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2512; X86-NEXT: vpaddb %ymm1, %ymm1, %ymm1513; X86-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0514; X86-NEXT: retl515;516; X64-LABEL: lshr_32i8:517; X64: # %bb.0:518; X64-NEXT: vpsllw $5, %ymm1, %ymm1519; X64-NEXT: vpsrlw $4, %ymm0, %ymm2520; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2521; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0522; X64-NEXT: vpsrlw $2, %ymm0, %ymm2523; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2524; X64-NEXT: vpaddb %ymm1, %ymm1, %ymm1525; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0526; X64-NEXT: vpsrlw $1, %ymm0, %ymm2527; X64-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2528; X64-NEXT: vpaddb %ymm1, %ymm1, %ymm1529; X64-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0530; X64-NEXT: retq531 %lshr = lshr <32 x i8> %r, %a532 ret <32 x i8> %lshr533}534