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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512F3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512BW5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512DQ6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512bw,+avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=SKX7 8define <8 x double> @addpd512(<8 x double> %y, <8 x double> %x) {9; CHECK-LABEL: addpd512:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm012; CHECK-NEXT: retq13entry:14 %add.i = fadd <8 x double> %x, %y15 ret <8 x double> %add.i16}17 18define <8 x double> @addpd512fold(<8 x double> %y) {19; CHECK-LABEL: addpd512fold:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm022; CHECK-NEXT: retq23entry:24 %add.i = fadd <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.800000e+00, double 2.300000e+00, double 1.200000e+00>25 ret <8 x double> %add.i26}27 28define <16 x float> @addps512(<16 x float> %y, <16 x float> %x) {29; CHECK-LABEL: addps512:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm032; CHECK-NEXT: retq33entry:34 %add.i = fadd <16 x float> %x, %y35 ret <16 x float> %add.i36}37 38define <16 x float> @addps512fold(<16 x float> %y) {39; CHECK-LABEL: addps512fold:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm042; CHECK-NEXT: retq43entry:44 %add.i = fadd <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 4.500000e+00, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>45 ret <16 x float> %add.i46}47 48define <8 x double> @subpd512(<8 x double> %y, <8 x double> %x) {49; CHECK-LABEL: subpd512:50; CHECK: # %bb.0: # %entry51; CHECK-NEXT: vsubpd %zmm0, %zmm1, %zmm052; CHECK-NEXT: retq53entry:54 %sub.i = fsub <8 x double> %x, %y55 ret <8 x double> %sub.i56}57 58define <8 x double> @subpd512fold(<8 x double> %y, ptr %x) {59; CHECK-LABEL: subpd512fold:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsubpd (%rdi), %zmm0, %zmm062; CHECK-NEXT: retq63entry:64 %tmp2 = load <8 x double>, ptr %x, align 865 %sub.i = fsub <8 x double> %y, %tmp266 ret <8 x double> %sub.i67}68 69define <16 x float> @subps512(<16 x float> %y, <16 x float> %x) {70; CHECK-LABEL: subps512:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsubps %zmm0, %zmm1, %zmm073; CHECK-NEXT: retq74entry:75 %sub.i = fsub <16 x float> %x, %y76 ret <16 x float> %sub.i77}78 79define <16 x float> @subps512fold(<16 x float> %y, ptr %x) {80; CHECK-LABEL: subps512fold:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: vsubps (%rdi), %zmm0, %zmm083; CHECK-NEXT: retq84entry:85 %tmp2 = load <16 x float>, ptr %x, align 486 %sub.i = fsub <16 x float> %y, %tmp287 ret <16 x float> %sub.i88}89 90define <8 x i64> @imulq512(<8 x i64> %y, <8 x i64> %x) {91; AVX512F-LABEL: imulq512:92; AVX512F: # %bb.0:93; AVX512F-NEXT: vpsrlq $32, %zmm1, %zmm294; AVX512F-NEXT: vpmuludq %zmm0, %zmm2, %zmm295; AVX512F-NEXT: vpsrlq $32, %zmm0, %zmm396; AVX512F-NEXT: vpmuludq %zmm3, %zmm1, %zmm397; AVX512F-NEXT: vpaddq %zmm2, %zmm3, %zmm298; AVX512F-NEXT: vpsllq $32, %zmm2, %zmm299; AVX512F-NEXT: vpmuludq %zmm0, %zmm1, %zmm0100; AVX512F-NEXT: vpaddq %zmm2, %zmm0, %zmm0101; AVX512F-NEXT: retq102;103; AVX512VL-LABEL: imulq512:104; AVX512VL: # %bb.0:105; AVX512VL-NEXT: vpsrlq $32, %zmm1, %zmm2106; AVX512VL-NEXT: vpmuludq %zmm0, %zmm2, %zmm2107; AVX512VL-NEXT: vpsrlq $32, %zmm0, %zmm3108; AVX512VL-NEXT: vpmuludq %zmm3, %zmm1, %zmm3109; AVX512VL-NEXT: vpaddq %zmm2, %zmm3, %zmm2110; AVX512VL-NEXT: vpsllq $32, %zmm2, %zmm2111; AVX512VL-NEXT: vpmuludq %zmm0, %zmm1, %zmm0112; AVX512VL-NEXT: vpaddq %zmm2, %zmm0, %zmm0113; AVX512VL-NEXT: retq114;115; AVX512BW-LABEL: imulq512:116; AVX512BW: # %bb.0:117; AVX512BW-NEXT: vpsrlq $32, %zmm1, %zmm2118; AVX512BW-NEXT: vpmuludq %zmm0, %zmm2, %zmm2119; AVX512BW-NEXT: vpsrlq $32, %zmm0, %zmm3120; AVX512BW-NEXT: vpmuludq %zmm3, %zmm1, %zmm3121; AVX512BW-NEXT: vpaddq %zmm2, %zmm3, %zmm2122; AVX512BW-NEXT: vpsllq $32, %zmm2, %zmm2123; AVX512BW-NEXT: vpmuludq %zmm0, %zmm1, %zmm0124; AVX512BW-NEXT: vpaddq %zmm2, %zmm0, %zmm0125; AVX512BW-NEXT: retq126;127; AVX512DQ-LABEL: imulq512:128; AVX512DQ: # %bb.0:129; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0130; AVX512DQ-NEXT: retq131;132; SKX-LABEL: imulq512:133; SKX: # %bb.0:134; SKX-NEXT: vpmullq %zmm0, %zmm1, %zmm0135; SKX-NEXT: retq136 %z = mul <8 x i64>%x, %y137 ret <8 x i64>%z138}139 140define <4 x i64> @imulq256(<4 x i64> %y, <4 x i64> %x) {141; AVX512F-LABEL: imulq256:142; AVX512F: # %bb.0:143; AVX512F-NEXT: vpsrlq $32, %ymm1, %ymm2144; AVX512F-NEXT: vpmuludq %ymm0, %ymm2, %ymm2145; AVX512F-NEXT: vpsrlq $32, %ymm0, %ymm3146; AVX512F-NEXT: vpmuludq %ymm3, %ymm1, %ymm3147; AVX512F-NEXT: vpaddq %ymm2, %ymm3, %ymm2148; AVX512F-NEXT: vpsllq $32, %ymm2, %ymm2149; AVX512F-NEXT: vpmuludq %ymm0, %ymm1, %ymm0150; AVX512F-NEXT: vpaddq %ymm2, %ymm0, %ymm0151; AVX512F-NEXT: retq152;153; AVX512VL-LABEL: imulq256:154; AVX512VL: # %bb.0:155; AVX512VL-NEXT: vpsrlq $32, %ymm1, %ymm2156; AVX512VL-NEXT: vpmuludq %ymm0, %ymm2, %ymm2157; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm3158; AVX512VL-NEXT: vpmuludq %ymm3, %ymm1, %ymm3159; AVX512VL-NEXT: vpaddq %ymm2, %ymm3, %ymm2160; AVX512VL-NEXT: vpsllq $32, %ymm2, %ymm2161; AVX512VL-NEXT: vpmuludq %ymm0, %ymm1, %ymm0162; AVX512VL-NEXT: vpaddq %ymm2, %ymm0, %ymm0163; AVX512VL-NEXT: retq164;165; AVX512BW-LABEL: imulq256:166; AVX512BW: # %bb.0:167; AVX512BW-NEXT: vpsrlq $32, %ymm1, %ymm2168; AVX512BW-NEXT: vpmuludq %ymm0, %ymm2, %ymm2169; AVX512BW-NEXT: vpsrlq $32, %ymm0, %ymm3170; AVX512BW-NEXT: vpmuludq %ymm3, %ymm1, %ymm3171; AVX512BW-NEXT: vpaddq %ymm2, %ymm3, %ymm2172; AVX512BW-NEXT: vpsllq $32, %ymm2, %ymm2173; AVX512BW-NEXT: vpmuludq %ymm0, %ymm1, %ymm0174; AVX512BW-NEXT: vpaddq %ymm2, %ymm0, %ymm0175; AVX512BW-NEXT: retq176;177; AVX512DQ-LABEL: imulq256:178; AVX512DQ: # %bb.0:179; AVX512DQ-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1180; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0181; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0182; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0183; AVX512DQ-NEXT: retq184;185; SKX-LABEL: imulq256:186; SKX: # %bb.0:187; SKX-NEXT: vpmullq %ymm0, %ymm1, %ymm0188; SKX-NEXT: retq189 %z = mul <4 x i64>%x, %y190 ret <4 x i64>%z191}192 193define <4 x i64> @imulq256_bcast(<4 x i64> %x) {194; AVX512F-LABEL: imulq256_bcast:195; AVX512F: # %bb.0:196; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1337,1337,1337,1337]197; AVX512F-NEXT: vpmuludq %ymm1, %ymm0, %ymm2198; AVX512F-NEXT: vpsrlq $32, %ymm0, %ymm0199; AVX512F-NEXT: vpmuludq %ymm1, %ymm0, %ymm0200; AVX512F-NEXT: vpsllq $32, %ymm0, %ymm0201; AVX512F-NEXT: vpaddq %ymm0, %ymm2, %ymm0202; AVX512F-NEXT: retq203;204; AVX512VL-LABEL: imulq256_bcast:205; AVX512VL: # %bb.0:206; AVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1337,1337,1337,1337]207; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm2208; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm0209; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0210; AVX512VL-NEXT: vpsllq $32, %ymm0, %ymm0211; AVX512VL-NEXT: vpaddq %ymm0, %ymm2, %ymm0212; AVX512VL-NEXT: retq213;214; AVX512BW-LABEL: imulq256_bcast:215; AVX512BW: # %bb.0:216; AVX512BW-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1337,1337,1337,1337]217; AVX512BW-NEXT: vpmuludq %ymm1, %ymm0, %ymm2218; AVX512BW-NEXT: vpsrlq $32, %ymm0, %ymm0219; AVX512BW-NEXT: vpmuludq %ymm1, %ymm0, %ymm0220; AVX512BW-NEXT: vpsllq $32, %ymm0, %ymm0221; AVX512BW-NEXT: vpaddq %ymm0, %ymm2, %ymm0222; AVX512BW-NEXT: retq223;224; AVX512DQ-LABEL: imulq256_bcast:225; AVX512DQ: # %bb.0:226; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0227; AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0228; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0229; AVX512DQ-NEXT: retq230;231; SKX-LABEL: imulq256_bcast:232; SKX: # %bb.0:233; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0234; SKX-NEXT: retq235 %z = mul <4 x i64> %x, <i64 1337, i64 1337, i64 1337, i64 1337>236 ret <4 x i64>%z237}238 239define <2 x i64> @imulq128(<2 x i64> %y, <2 x i64> %x) {240; AVX512F-LABEL: imulq128:241; AVX512F: # %bb.0:242; AVX512F-NEXT: vpsrlq $32, %xmm1, %xmm2243; AVX512F-NEXT: vpmuludq %xmm0, %xmm2, %xmm2244; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm3245; AVX512F-NEXT: vpmuludq %xmm3, %xmm1, %xmm3246; AVX512F-NEXT: vpaddq %xmm2, %xmm3, %xmm2247; AVX512F-NEXT: vpsllq $32, %xmm2, %xmm2248; AVX512F-NEXT: vpmuludq %xmm0, %xmm1, %xmm0249; AVX512F-NEXT: vpaddq %xmm2, %xmm0, %xmm0250; AVX512F-NEXT: retq251;252; AVX512VL-LABEL: imulq128:253; AVX512VL: # %bb.0:254; AVX512VL-NEXT: vpsrlq $32, %xmm1, %xmm2255; AVX512VL-NEXT: vpmuludq %xmm0, %xmm2, %xmm2256; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm3257; AVX512VL-NEXT: vpmuludq %xmm3, %xmm1, %xmm3258; AVX512VL-NEXT: vpaddq %xmm2, %xmm3, %xmm2259; AVX512VL-NEXT: vpsllq $32, %xmm2, %xmm2260; AVX512VL-NEXT: vpmuludq %xmm0, %xmm1, %xmm0261; AVX512VL-NEXT: vpaddq %xmm2, %xmm0, %xmm0262; AVX512VL-NEXT: retq263;264; AVX512BW-LABEL: imulq128:265; AVX512BW: # %bb.0:266; AVX512BW-NEXT: vpsrlq $32, %xmm1, %xmm2267; AVX512BW-NEXT: vpmuludq %xmm0, %xmm2, %xmm2268; AVX512BW-NEXT: vpsrlq $32, %xmm0, %xmm3269; AVX512BW-NEXT: vpmuludq %xmm3, %xmm1, %xmm3270; AVX512BW-NEXT: vpaddq %xmm2, %xmm3, %xmm2271; AVX512BW-NEXT: vpsllq $32, %xmm2, %xmm2272; AVX512BW-NEXT: vpmuludq %xmm0, %xmm1, %xmm0273; AVX512BW-NEXT: vpaddq %xmm2, %xmm0, %xmm0274; AVX512BW-NEXT: retq275;276; AVX512DQ-LABEL: imulq128:277; AVX512DQ: # %bb.0:278; AVX512DQ-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1279; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0280; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0281; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0282; AVX512DQ-NEXT: vzeroupper283; AVX512DQ-NEXT: retq284;285; SKX-LABEL: imulq128:286; SKX: # %bb.0:287; SKX-NEXT: vpmullq %xmm0, %xmm1, %xmm0288; SKX-NEXT: retq289 %z = mul <2 x i64>%x, %y290 ret <2 x i64>%z291}292 293define <2 x i64> @imulq128_bcast(<2 x i64> %x) {294; AVX512F-LABEL: imulq128_bcast:295; AVX512F: # %bb.0:296; AVX512F-NEXT: vpmovsxwq {{.*#+}} xmm1 = [8086,8086]297; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm2298; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0299; AVX512F-NEXT: vpmuludq %xmm1, %xmm0, %xmm0300; AVX512F-NEXT: vpsllq $32, %xmm0, %xmm0301; AVX512F-NEXT: vpaddq %xmm0, %xmm2, %xmm0302; AVX512F-NEXT: retq303;304; AVX512VL-LABEL: imulq128_bcast:305; AVX512VL: # %bb.0:306; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]307; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2308; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0309; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0310; AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0311; AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0312; AVX512VL-NEXT: retq313;314; AVX512BW-LABEL: imulq128_bcast:315; AVX512BW: # %bb.0:316; AVX512BW-NEXT: vpmovsxwq {{.*#+}} xmm1 = [8086,8086]317; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm2318; AVX512BW-NEXT: vpsrlq $32, %xmm0, %xmm0319; AVX512BW-NEXT: vpmuludq %xmm1, %xmm0, %xmm0320; AVX512BW-NEXT: vpsllq $32, %xmm0, %xmm0321; AVX512BW-NEXT: vpaddq %xmm0, %xmm2, %xmm0322; AVX512BW-NEXT: retq323;324; AVX512DQ-LABEL: imulq128_bcast:325; AVX512DQ: # %bb.0:326; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0327; AVX512DQ-NEXT: vpmovsxwq {{.*#+}} xmm1 = [8086,8086]328; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0329; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0330; AVX512DQ-NEXT: vzeroupper331; AVX512DQ-NEXT: retq332;333; SKX-LABEL: imulq128_bcast:334; SKX: # %bb.0:335; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0336; SKX-NEXT: retq337 %z = mul <2 x i64> %x, <i64 8086, i64 8086>338 ret <2 x i64>%z339}340 341define <8 x double> @mulpd512(<8 x double> %y, <8 x double> %x) {342; CHECK-LABEL: mulpd512:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: vmulpd %zmm0, %zmm1, %zmm0345; CHECK-NEXT: retq346entry:347 %mul.i = fmul <8 x double> %x, %y348 ret <8 x double> %mul.i349}350 351define <8 x double> @mulpd512fold(<8 x double> %y) {352; CHECK-LABEL: mulpd512fold:353; CHECK: # %bb.0: # %entry354; CHECK-NEXT: vmulpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0355; CHECK-NEXT: retq356entry:357 %mul.i = fmul <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>358 ret <8 x double> %mul.i359}360 361define <16 x float> @mulps512(<16 x float> %y, <16 x float> %x) {362; CHECK-LABEL: mulps512:363; CHECK: # %bb.0: # %entry364; CHECK-NEXT: vmulps %zmm0, %zmm1, %zmm0365; CHECK-NEXT: retq366entry:367 %mul.i = fmul <16 x float> %x, %y368 ret <16 x float> %mul.i369}370 371define <16 x float> @mulps512fold(<16 x float> %y) {372; CHECK-LABEL: mulps512fold:373; CHECK: # %bb.0: # %entry374; CHECK-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0375; CHECK-NEXT: retq376entry:377 %mul.i = fmul <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>378 ret <16 x float> %mul.i379}380 381define <8 x double> @divpd512(<8 x double> %y, <8 x double> %x) {382; CHECK-LABEL: divpd512:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vdivpd %zmm0, %zmm1, %zmm0385; CHECK-NEXT: retq386entry:387 %div.i = fdiv <8 x double> %x, %y388 ret <8 x double> %div.i389}390 391define <8 x double> @divpd512fold(<8 x double> %y) {392; CHECK-LABEL: divpd512fold:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vdivpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0395; CHECK-NEXT: retq396entry:397 %div.i = fdiv <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>398 ret <8 x double> %div.i399}400 401define <16 x float> @divps512(<16 x float> %y, <16 x float> %x) {402; CHECK-LABEL: divps512:403; CHECK: # %bb.0: # %entry404; CHECK-NEXT: vdivps %zmm0, %zmm1, %zmm0405; CHECK-NEXT: retq406entry:407 %div.i = fdiv <16 x float> %x, %y408 ret <16 x float> %div.i409}410 411define <16 x float> @divps512fold(<16 x float> %y) {412; CHECK-LABEL: divps512fold:413; CHECK: # %bb.0: # %entry414; CHECK-NEXT: vdivps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0415; CHECK-NEXT: retq416entry:417 %div.i = fdiv <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000>418 ret <16 x float> %div.i419}420 421define <8 x i64> @vpaddq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {422; CHECK-LABEL: vpaddq_test:423; CHECK: # %bb.0:424; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0425; CHECK-NEXT: retq426 %x = add <8 x i64> %i, %j427 ret <8 x i64> %x428}429 430define <8 x i64> @vpaddq_fold_test(<8 x i64> %i, ptr %j) nounwind {431; CHECK-LABEL: vpaddq_fold_test:432; CHECK: # %bb.0:433; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0434; CHECK-NEXT: retq435 %tmp = load <8 x i64>, ptr %j, align 4436 %x = add <8 x i64> %i, %tmp437 ret <8 x i64> %x438}439 440define <8 x i64> @vpaddq_broadcast_test(<8 x i64> %i) nounwind {441; CHECK-LABEL: vpaddq_broadcast_test:442; CHECK: # %bb.0:443; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0444; CHECK-NEXT: retq445 %x = add <8 x i64> %i, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>446 ret <8 x i64> %x447}448 449define <8 x i64> @vpaddq_broadcast2_test(<8 x i64> %i, ptr %j) nounwind {450; CHECK-LABEL: vpaddq_broadcast2_test:451; CHECK: # %bb.0:452; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0453; CHECK-NEXT: retq454 %tmp = load i64, ptr %j455 %j.0 = insertelement <8 x i64> undef, i64 %tmp, i32 0456 %j.1 = insertelement <8 x i64> %j.0, i64 %tmp, i32 1457 %j.2 = insertelement <8 x i64> %j.1, i64 %tmp, i32 2458 %j.3 = insertelement <8 x i64> %j.2, i64 %tmp, i32 3459 %j.4 = insertelement <8 x i64> %j.3, i64 %tmp, i32 4460 %j.5 = insertelement <8 x i64> %j.4, i64 %tmp, i32 5461 %j.6 = insertelement <8 x i64> %j.5, i64 %tmp, i32 6462 %j.7 = insertelement <8 x i64> %j.6, i64 %tmp, i32 7463 %x = add <8 x i64> %i, %j.7464 ret <8 x i64> %x465}466 467define <16 x i32> @vpaddd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {468; CHECK-LABEL: vpaddd_test:469; CHECK: # %bb.0:470; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0471; CHECK-NEXT: retq472 %x = add <16 x i32> %i, %j473 ret <16 x i32> %x474}475 476define <16 x i32> @vpaddd_fold_test(<16 x i32> %i, ptr %j) nounwind {477; CHECK-LABEL: vpaddd_fold_test:478; CHECK: # %bb.0:479; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0480; CHECK-NEXT: retq481 %tmp = load <16 x i32>, ptr %j, align 4482 %x = add <16 x i32> %i, %tmp483 ret <16 x i32> %x484}485 486define <16 x i32> @vpaddd_broadcast_test(<16 x i32> %i) nounwind {487; CHECK-LABEL: vpaddd_broadcast_test:488; CHECK: # %bb.0:489; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0490; CHECK-NEXT: retq491 %x = add <16 x i32> %i, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>492 ret <16 x i32> %x493}494 495define <16 x i32> @vpaddd_mask_test(<16 x i32> %i, <16 x i32> %j, <16 x i32> %mask1) nounwind readnone {496; CHECK-LABEL: vpaddd_mask_test:497; CHECK: # %bb.0:498; CHECK-NEXT: vptestmd %zmm2, %zmm2, %k1499; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0 {%k1}500; CHECK-NEXT: retq501 %mask = icmp ne <16 x i32> %mask1, zeroinitializer502 %x = add <16 x i32> %i, %j503 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i504 ret <16 x i32> %r505}506 507define <16 x i32> @vpaddd_maskz_test(<16 x i32> %i, <16 x i32> %j, <16 x i32> %mask1) nounwind readnone {508; CHECK-LABEL: vpaddd_maskz_test:509; CHECK: # %bb.0:510; CHECK-NEXT: vptestmd %zmm2, %zmm2, %k1511; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0 {%k1} {z}512; CHECK-NEXT: retq513 %mask = icmp ne <16 x i32> %mask1, zeroinitializer514 %x = add <16 x i32> %i, %j515 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer516 ret <16 x i32> %r517}518 519define <16 x i32> @vpaddd_mask_fold_test(<16 x i32> %i, ptr %j.ptr, <16 x i32> %mask1) nounwind readnone {520; CHECK-LABEL: vpaddd_mask_fold_test:521; CHECK: # %bb.0:522; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1523; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0 {%k1}524; CHECK-NEXT: retq525 %mask = icmp ne <16 x i32> %mask1, zeroinitializer526 %j = load <16 x i32>, ptr %j.ptr527 %x = add <16 x i32> %i, %j528 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i529 ret <16 x i32> %r530}531 532define <16 x i32> @vpaddd_mask_broadcast_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {533; CHECK-LABEL: vpaddd_mask_broadcast_test:534; CHECK: # %bb.0:535; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1536; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 {%k1}537; CHECK-NEXT: retq538 %mask = icmp ne <16 x i32> %mask1, zeroinitializer539 %x = add <16 x i32> %i, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>540 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i541 ret <16 x i32> %r542}543 544define <16 x i32> @vpaddd_maskz_fold_test(<16 x i32> %i, ptr %j.ptr, <16 x i32> %mask1) nounwind readnone {545; CHECK-LABEL: vpaddd_maskz_fold_test:546; CHECK: # %bb.0:547; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1548; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0 {%k1} {z}549; CHECK-NEXT: retq550 %mask = icmp ne <16 x i32> %mask1, zeroinitializer551 %j = load <16 x i32>, ptr %j.ptr552 %x = add <16 x i32> %i, %j553 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer554 ret <16 x i32> %r555}556 557define <16 x i32> @vpaddd_maskz_broadcast_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {558; CHECK-LABEL: vpaddd_maskz_broadcast_test:559; CHECK: # %bb.0:560; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1561; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 {%k1} {z}562; CHECK-NEXT: retq563 %mask = icmp ne <16 x i32> %mask1, zeroinitializer564 %x = add <16 x i32> %i, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>565 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer566 ret <16 x i32> %r567}568 569define <8 x i64> @vpsubq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {570; CHECK-LABEL: vpsubq_test:571; CHECK: # %bb.0:572; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0573; CHECK-NEXT: retq574 %x = sub <8 x i64> %i, %j575 ret <8 x i64> %x576}577 578define <16 x i32> @vpsubd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {579; CHECK-LABEL: vpsubd_test:580; CHECK: # %bb.0:581; CHECK-NEXT: vpsubd %zmm1, %zmm0, %zmm0582; CHECK-NEXT: retq583 %x = sub <16 x i32> %i, %j584 ret <16 x i32> %x585}586 587define <16 x i32> @vpmulld_test(<16 x i32> %i, <16 x i32> %j) {588; CHECK-LABEL: vpmulld_test:589; CHECK: # %bb.0:590; CHECK-NEXT: vpmulld %zmm1, %zmm0, %zmm0591; CHECK-NEXT: retq592 %x = mul <16 x i32> %i, %j593 ret <16 x i32> %x594}595 596declare float @sqrtf(float) readnone597define float @sqrtA(float %a) nounwind uwtable readnone ssp {598; CHECK-LABEL: sqrtA:599; CHECK: # %bb.0: # %entry600; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0601; CHECK-NEXT: retq602entry:603 %conv1 = tail call float @sqrtf(float %a) nounwind readnone604 ret float %conv1605}606 607declare double @sqrt(double) readnone608define double @sqrtB(double %a) nounwind uwtable readnone ssp {609; CHECK-LABEL: sqrtB:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0612; CHECK-NEXT: retq613entry:614 %call = tail call double @sqrt(double %a) nounwind readnone615 ret double %call616}617 618declare float @llvm.sqrt.f32(float)619define float @sqrtC(float %a) nounwind {620; CHECK-LABEL: sqrtC:621; CHECK: # %bb.0:622; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0623; CHECK-NEXT: retq624 %b = call float @llvm.sqrt.f32(float %a)625 ret float %b626}627 628declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)629define <16 x float> @sqrtD(<16 x float> %a) nounwind {630; CHECK-LABEL: sqrtD:631; CHECK: # %bb.0:632; CHECK-NEXT: vsqrtps %zmm0, %zmm0633; CHECK-NEXT: retq634 %b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)635 ret <16 x float> %b636}637 638declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)639define <8 x double> @sqrtE(<8 x double> %a) nounwind {640; CHECK-LABEL: sqrtE:641; CHECK: # %bb.0:642; CHECK-NEXT: vsqrtpd %zmm0, %zmm0643; CHECK-NEXT: retq644 %b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)645 ret <8 x double> %b646}647 648define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {649; CHECK-LABEL: fadd_broadcast:650; CHECK: # %bb.0:651; CHECK-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0652; CHECK-NEXT: retq653 %b = fadd <16 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>654 ret <16 x float> %b655}656 657define <8 x i64> @addq_broadcast(<8 x i64> %a) nounwind {658; CHECK-LABEL: addq_broadcast:659; CHECK: # %bb.0:660; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0661; CHECK-NEXT: retq662 %b = add <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>663 ret <8 x i64> %b664}665 666define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {667; AVX512F-LABEL: orq_broadcast:668; AVX512F: # %bb.0:669; AVX512F-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0670; AVX512F-NEXT: retq671;672; AVX512VL-LABEL: orq_broadcast:673; AVX512VL: # %bb.0:674; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0675; AVX512VL-NEXT: retq676;677; AVX512BW-LABEL: orq_broadcast:678; AVX512BW: # %bb.0:679; AVX512BW-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0680; AVX512BW-NEXT: retq681;682; AVX512DQ-LABEL: orq_broadcast:683; AVX512DQ: # %bb.0:684; AVX512DQ-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0685; AVX512DQ-NEXT: retq686;687; SKX-LABEL: orq_broadcast:688; SKX: # %bb.0:689; SKX-NEXT: vorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0690; SKX-NEXT: retq691 %b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>692 ret <8 x i64> %b693}694 695define <16 x i32> @andd512fold(<16 x i32> %y, ptr %x) {696; AVX512F-LABEL: andd512fold:697; AVX512F: # %bb.0: # %entry698; AVX512F-NEXT: vpandd (%rdi), %zmm0, %zmm0699; AVX512F-NEXT: retq700;701; AVX512VL-LABEL: andd512fold:702; AVX512VL: # %bb.0: # %entry703; AVX512VL-NEXT: vpandd (%rdi), %zmm0, %zmm0704; AVX512VL-NEXT: retq705;706; AVX512BW-LABEL: andd512fold:707; AVX512BW: # %bb.0: # %entry708; AVX512BW-NEXT: vpandd (%rdi), %zmm0, %zmm0709; AVX512BW-NEXT: retq710;711; AVX512DQ-LABEL: andd512fold:712; AVX512DQ: # %bb.0: # %entry713; AVX512DQ-NEXT: vandps (%rdi), %zmm0, %zmm0714; AVX512DQ-NEXT: retq715;716; SKX-LABEL: andd512fold:717; SKX: # %bb.0: # %entry718; SKX-NEXT: vandps (%rdi), %zmm0, %zmm0719; SKX-NEXT: retq720entry:721 %a = load <16 x i32>, ptr %x, align 4722 %b = and <16 x i32> %y, %a723 ret <16 x i32> %b724}725 726define <8 x i64> @andqbrst(<8 x i64> %p1, ptr %ap) {727; AVX512F-LABEL: andqbrst:728; AVX512F: # %bb.0: # %entry729; AVX512F-NEXT: vpandq (%rdi){1to8}, %zmm0, %zmm0730; AVX512F-NEXT: retq731;732; AVX512VL-LABEL: andqbrst:733; AVX512VL: # %bb.0: # %entry734; AVX512VL-NEXT: vpandq (%rdi){1to8}, %zmm0, %zmm0735; AVX512VL-NEXT: retq736;737; AVX512BW-LABEL: andqbrst:738; AVX512BW: # %bb.0: # %entry739; AVX512BW-NEXT: vpandq (%rdi){1to8}, %zmm0, %zmm0740; AVX512BW-NEXT: retq741;742; AVX512DQ-LABEL: andqbrst:743; AVX512DQ: # %bb.0: # %entry744; AVX512DQ-NEXT: vandpd (%rdi){1to8}, %zmm0, %zmm0745; AVX512DQ-NEXT: retq746;747; SKX-LABEL: andqbrst:748; SKX: # %bb.0: # %entry749; SKX-NEXT: vandpd (%rdi){1to8}, %zmm0, %zmm0750; SKX-NEXT: retq751entry:752 %a = load i64, ptr %ap, align 8753 %b = insertelement <8 x i64> undef, i64 %a, i32 0754 %c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer755 %d = and <8 x i64> %p1, %c756 ret <8 x i64>%d757}758 759define <16 x float> @test_mask_vaddps(<16 x float> %dst, <16 x float> %i,760; CHECK-LABEL: test_mask_vaddps:761; CHECK: # %bb.0:762; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1763; CHECK-NEXT: vaddps %zmm2, %zmm1, %zmm0 {%k1}764; CHECK-NEXT: retq765 <16 x float> %j, <16 x i32> %mask1)766 nounwind readnone {767 %mask = icmp ne <16 x i32> %mask1, zeroinitializer768 %x = fadd <16 x float> %i, %j769 %r = select <16 x i1> %mask, <16 x float> %x, <16 x float> %dst770 ret <16 x float> %r771}772 773define <16 x float> @test_mask_vmulps(<16 x float> %dst, <16 x float> %i,774; CHECK-LABEL: test_mask_vmulps:775; CHECK: # %bb.0:776; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1777; CHECK-NEXT: vmulps %zmm2, %zmm1, %zmm0 {%k1}778; CHECK-NEXT: retq779 <16 x float> %j, <16 x i32> %mask1)780 nounwind readnone {781 %mask = icmp ne <16 x i32> %mask1, zeroinitializer782 %x = fmul <16 x float> %i, %j783 %r = select <16 x i1> %mask, <16 x float> %x, <16 x float> %dst784 ret <16 x float> %r785}786 787define <16 x float> @test_mask_vminps(<16 x float> %dst, <16 x float> %i,788; CHECK-LABEL: test_mask_vminps:789; CHECK: # %bb.0:790; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1791; CHECK-NEXT: vminps %zmm2, %zmm1, %zmm0 {%k1}792; CHECK-NEXT: retq793 <16 x float> %j, <16 x i32> %mask1)794 nounwind readnone {795 %mask = icmp ne <16 x i32> %mask1, zeroinitializer796 %cmp_res = fcmp olt <16 x float> %i, %j797 %min = select <16 x i1> %cmp_res, <16 x float> %i, <16 x float> %j798 %r = select <16 x i1> %mask, <16 x float> %min, <16 x float> %dst799 ret <16 x float> %r800}801 802define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i,803; AVX512F-LABEL: test_mask_vminpd:804; AVX512F: # %bb.0:805; AVX512F-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3806; AVX512F-NEXT: vptestmd %zmm3, %zmm3, %k1807; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}808; AVX512F-NEXT: retq809;810; AVX512VL-LABEL: test_mask_vminpd:811; AVX512VL: # %bb.0:812; AVX512VL-NEXT: vptestmd %ymm3, %ymm3, %k1813; AVX512VL-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}814; AVX512VL-NEXT: retq815;816; AVX512BW-LABEL: test_mask_vminpd:817; AVX512BW: # %bb.0:818; AVX512BW-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3819; AVX512BW-NEXT: vptestmd %zmm3, %zmm3, %k1820; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}821; AVX512BW-NEXT: retq822;823; AVX512DQ-LABEL: test_mask_vminpd:824; AVX512DQ: # %bb.0:825; AVX512DQ-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3826; AVX512DQ-NEXT: vptestmd %zmm3, %zmm3, %k1827; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}828; AVX512DQ-NEXT: retq829;830; SKX-LABEL: test_mask_vminpd:831; SKX: # %bb.0:832; SKX-NEXT: vptestmd %ymm3, %ymm3, %k1833; SKX-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1}834; SKX-NEXT: retq835 <8 x double> %j, <8 x i32> %mask1)836 nounwind readnone {837 %mask = icmp ne <8 x i32> %mask1, zeroinitializer838 %cmp_res = fcmp olt <8 x double> %i, %j839 %min = select <8 x i1> %cmp_res, <8 x double> %i, <8 x double> %j840 %r = select <8 x i1> %mask, <8 x double> %min, <8 x double> %dst841 ret <8 x double> %r842}843 844define <16 x float> @test_mask_vmaxps(<16 x float> %dst, <16 x float> %i,845; CHECK-LABEL: test_mask_vmaxps:846; CHECK: # %bb.0:847; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1848; CHECK-NEXT: vmaxps %zmm2, %zmm1, %zmm0 {%k1}849; CHECK-NEXT: retq850 <16 x float> %j, <16 x i32> %mask1)851 nounwind readnone {852 %mask = icmp ne <16 x i32> %mask1, zeroinitializer853 %cmp_res = fcmp ogt <16 x float> %i, %j854 %max = select <16 x i1> %cmp_res, <16 x float> %i, <16 x float> %j855 %r = select <16 x i1> %mask, <16 x float> %max, <16 x float> %dst856 ret <16 x float> %r857}858 859define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i,860; AVX512F-LABEL: test_mask_vmaxpd:861; AVX512F: # %bb.0:862; AVX512F-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3863; AVX512F-NEXT: vptestmd %zmm3, %zmm3, %k1864; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}865; AVX512F-NEXT: retq866;867; AVX512VL-LABEL: test_mask_vmaxpd:868; AVX512VL: # %bb.0:869; AVX512VL-NEXT: vptestmd %ymm3, %ymm3, %k1870; AVX512VL-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}871; AVX512VL-NEXT: retq872;873; AVX512BW-LABEL: test_mask_vmaxpd:874; AVX512BW: # %bb.0:875; AVX512BW-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3876; AVX512BW-NEXT: vptestmd %zmm3, %zmm3, %k1877; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}878; AVX512BW-NEXT: retq879;880; AVX512DQ-LABEL: test_mask_vmaxpd:881; AVX512DQ: # %bb.0:882; AVX512DQ-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3883; AVX512DQ-NEXT: vptestmd %zmm3, %zmm3, %k1884; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}885; AVX512DQ-NEXT: retq886;887; SKX-LABEL: test_mask_vmaxpd:888; SKX: # %bb.0:889; SKX-NEXT: vptestmd %ymm3, %ymm3, %k1890; SKX-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1}891; SKX-NEXT: retq892 <8 x double> %j, <8 x i32> %mask1)893 nounwind readnone {894 %mask = icmp ne <8 x i32> %mask1, zeroinitializer895 %cmp_res = fcmp ogt <8 x double> %i, %j896 %max = select <8 x i1> %cmp_res, <8 x double> %i, <8 x double> %j897 %r = select <8 x i1> %mask, <8 x double> %max, <8 x double> %dst898 ret <8 x double> %r899}900 901define <16 x float> @test_mask_vsubps(<16 x float> %dst, <16 x float> %i,902; CHECK-LABEL: test_mask_vsubps:903; CHECK: # %bb.0:904; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1905; CHECK-NEXT: vsubps %zmm2, %zmm1, %zmm0 {%k1}906; CHECK-NEXT: retq907 <16 x float> %j, <16 x i32> %mask1)908 nounwind readnone {909 %mask = icmp ne <16 x i32> %mask1, zeroinitializer910 %x = fsub <16 x float> %i, %j911 %r = select <16 x i1> %mask, <16 x float> %x, <16 x float> %dst912 ret <16 x float> %r913}914 915define <16 x float> @test_mask_vdivps(<16 x float> %dst, <16 x float> %i,916; CHECK-LABEL: test_mask_vdivps:917; CHECK: # %bb.0:918; CHECK-NEXT: vptestmd %zmm3, %zmm3, %k1919; CHECK-NEXT: vdivps %zmm2, %zmm1, %zmm0 {%k1}920; CHECK-NEXT: retq921 <16 x float> %j, <16 x i32> %mask1)922 nounwind readnone {923 %mask = icmp ne <16 x i32> %mask1, zeroinitializer924 %x = fdiv <16 x float> %i, %j925 %r = select <16 x i1> %mask, <16 x float> %x, <16 x float> %dst926 ret <16 x float> %r927}928 929define <8 x double> @test_mask_vaddpd(<8 x double> %dst, <8 x double> %i,930; CHECK-LABEL: test_mask_vaddpd:931; CHECK: # %bb.0:932; CHECK-NEXT: vptestmq %zmm3, %zmm3, %k1933; CHECK-NEXT: vaddpd %zmm2, %zmm1, %zmm0 {%k1}934; CHECK-NEXT: retq935 <8 x double> %j, <8 x i64> %mask1)936 nounwind readnone {937 %mask = icmp ne <8 x i64> %mask1, zeroinitializer938 %x = fadd <8 x double> %i, %j939 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> %dst940 ret <8 x double> %r941}942 943define <8 x double> @test_maskz_vaddpd(<8 x double> %i, <8 x double> %j,944; CHECK-LABEL: test_maskz_vaddpd:945; CHECK: # %bb.0:946; CHECK-NEXT: vptestmq %zmm2, %zmm2, %k1947; CHECK-NEXT: vaddpd %zmm1, %zmm0, %zmm0 {%k1} {z}948; CHECK-NEXT: retq949 <8 x i64> %mask1) nounwind readnone {950 %mask = icmp ne <8 x i64> %mask1, zeroinitializer951 %x = fadd <8 x double> %i, %j952 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> zeroinitializer953 ret <8 x double> %r954}955 956define <8 x double> @test_mask_fold_vaddpd(<8 x double> %dst, <8 x double> %i,957; CHECK-LABEL: test_mask_fold_vaddpd:958; CHECK: # %bb.0:959; CHECK-NEXT: vptestmq %zmm2, %zmm2, %k1960; CHECK-NEXT: vaddpd (%rdi), %zmm1, %zmm0 {%k1}961; CHECK-NEXT: retq962 ptr %j, <8 x i64> %mask1)963 nounwind {964 %mask = icmp ne <8 x i64> %mask1, zeroinitializer965 %tmp = load <8 x double>, ptr %j, align 8966 %x = fadd <8 x double> %i, %tmp967 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> %dst968 ret <8 x double> %r969}970 971define <8 x double> @test_maskz_fold_vaddpd(<8 x double> %i, ptr %j,972; CHECK-LABEL: test_maskz_fold_vaddpd:973; CHECK: # %bb.0:974; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1975; CHECK-NEXT: vaddpd (%rdi), %zmm0, %zmm0 {%k1} {z}976; CHECK-NEXT: retq977 <8 x i64> %mask1) nounwind {978 %mask = icmp ne <8 x i64> %mask1, zeroinitializer979 %tmp = load <8 x double>, ptr %j, align 8980 %x = fadd <8 x double> %i, %tmp981 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> zeroinitializer982 ret <8 x double> %r983}984 985define <8 x double> @test_broadcast_vaddpd(<8 x double> %i, ptr %j) nounwind {986; CHECK-LABEL: test_broadcast_vaddpd:987; CHECK: # %bb.0:988; CHECK-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0989; CHECK-NEXT: retq990 %tmp = load double, ptr %j991 %b = insertelement <8 x double> undef, double %tmp, i32 0992 %c = shufflevector <8 x double> %b, <8 x double> undef,993 <8 x i32> zeroinitializer994 %x = fadd <8 x double> %c, %i995 ret <8 x double> %x996}997 998define <8 x double> @test_mask_broadcast_vaddpd(<8 x double> %dst, <8 x double> %i,999; CHECK-LABEL: test_mask_broadcast_vaddpd:1000; CHECK: # %bb.0:1001; CHECK-NEXT: vmovapd %zmm1, %zmm01002; CHECK-NEXT: vptestmq %zmm2, %zmm2, %k11003; CHECK-NEXT: vaddpd (%rdi){1to8}, %zmm1, %zmm0 {%k1}1004; CHECK-NEXT: retq1005 ptr %j, <8 x i64> %mask1) nounwind {1006 %mask = icmp ne <8 x i64> %mask1, zeroinitializer1007 %tmp = load double, ptr %j1008 %b = insertelement <8 x double> undef, double %tmp, i32 01009 %c = shufflevector <8 x double> %b, <8 x double> undef,1010 <8 x i32> zeroinitializer1011 %x = fadd <8 x double> %c, %i1012 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> %i1013 ret <8 x double> %r1014}1015 1016define <8 x double> @test_maskz_broadcast_vaddpd(<8 x double> %i, ptr %j,1017; CHECK-LABEL: test_maskz_broadcast_vaddpd:1018; CHECK: # %bb.0:1019; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k11020; CHECK-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z}1021; CHECK-NEXT: retq1022 <8 x i64> %mask1) nounwind {1023 %mask = icmp ne <8 x i64> %mask1, zeroinitializer1024 %tmp = load double, ptr %j1025 %b = insertelement <8 x double> undef, double %tmp, i32 01026 %c = shufflevector <8 x double> %b, <8 x double> undef,1027 <8 x i32> zeroinitializer1028 %x = fadd <8 x double> %c, %i1029 %r = select <8 x i1> %mask, <8 x double> %x, <8 x double> zeroinitializer1030 ret <8 x double> %r1031}1032 1033define <16 x float> @test_fxor(<16 x float> %a) {1034; AVX512F-LABEL: test_fxor:1035; AVX512F: # %bb.0:1036; AVX512F-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01037; AVX512F-NEXT: retq1038;1039; AVX512VL-LABEL: test_fxor:1040; AVX512VL: # %bb.0:1041; AVX512VL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01042; AVX512VL-NEXT: retq1043;1044; AVX512BW-LABEL: test_fxor:1045; AVX512BW: # %bb.0:1046; AVX512BW-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01047; AVX512BW-NEXT: retq1048;1049; AVX512DQ-LABEL: test_fxor:1050; AVX512DQ: # %bb.0:1051; AVX512DQ-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01052; AVX512DQ-NEXT: retq1053;1054; SKX-LABEL: test_fxor:1055; SKX: # %bb.0:1056; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01057; SKX-NEXT: retq1058 1059 %res = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a1060 ret <16 x float>%res1061}1062 1063define <8 x float> @test_fxor_8f32(<8 x float> %a) {1064; AVX512F-LABEL: test_fxor_8f32:1065; AVX512F: # %bb.0:1066; AVX512F-NEXT: vbroadcastss {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]1067; AVX512F-NEXT: vxorps %ymm1, %ymm0, %ymm01068; AVX512F-NEXT: retq1069;1070; AVX512VL-LABEL: test_fxor_8f32:1071; AVX512VL: # %bb.0:1072; AVX512VL-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm01073; AVX512VL-NEXT: retq1074;1075; AVX512BW-LABEL: test_fxor_8f32:1076; AVX512BW: # %bb.0:1077; AVX512BW-NEXT: vbroadcastss {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]1078; AVX512BW-NEXT: vxorps %ymm1, %ymm0, %ymm01079; AVX512BW-NEXT: retq1080;1081; AVX512DQ-LABEL: test_fxor_8f32:1082; AVX512DQ: # %bb.0:1083; AVX512DQ-NEXT: vbroadcastss {{.*#+}} ymm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]1084; AVX512DQ-NEXT: vxorps %ymm1, %ymm0, %ymm01085; AVX512DQ-NEXT: retq1086;1087; SKX-LABEL: test_fxor_8f32:1088; SKX: # %bb.0:1089; SKX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm01090; SKX-NEXT: retq1091 %res = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a1092 ret <8 x float>%res1093}1094 1095define <8 x double> @fabs_v8f64(<8 x double> %p)1096; AVX512F-LABEL: fabs_v8f64:1097; AVX512F: # %bb.0:1098; AVX512F-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm01099; AVX512F-NEXT: retq1100;1101; AVX512VL-LABEL: fabs_v8f64:1102; AVX512VL: # %bb.0:1103; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm01104; AVX512VL-NEXT: retq1105;1106; AVX512BW-LABEL: fabs_v8f64:1107; AVX512BW: # %bb.0:1108; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm01109; AVX512BW-NEXT: retq1110;1111; AVX512DQ-LABEL: fabs_v8f64:1112; AVX512DQ: # %bb.0:1113; AVX512DQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm01114; AVX512DQ-NEXT: retq1115;1116; SKX-LABEL: fabs_v8f64:1117; SKX: # %bb.0:1118; SKX-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm01119; SKX-NEXT: retq1120{1121 %t = call <8 x double> @llvm.fabs.v8f64(<8 x double> %p)1122 ret <8 x double> %t1123}1124declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p)1125 1126define <16 x float> @fabs_v16f32(<16 x float> %p)1127; AVX512F-LABEL: fabs_v16f32:1128; AVX512F: # %bb.0:1129; AVX512F-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01130; AVX512F-NEXT: retq1131;1132; AVX512VL-LABEL: fabs_v16f32:1133; AVX512VL: # %bb.0:1134; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01135; AVX512VL-NEXT: retq1136;1137; AVX512BW-LABEL: fabs_v16f32:1138; AVX512BW: # %bb.0:1139; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01140; AVX512BW-NEXT: retq1141;1142; AVX512DQ-LABEL: fabs_v16f32:1143; AVX512DQ: # %bb.0:1144; AVX512DQ-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01145; AVX512DQ-NEXT: retq1146;1147; SKX-LABEL: fabs_v16f32:1148; SKX: # %bb.0:1149; SKX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm01150; SKX-NEXT: retq1151{1152 %t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)1153 ret <16 x float> %t1154}1155declare <16 x float> @llvm.fabs.v16f32(<16 x float> %p)1156 1157define <16 x i32> @masked_inc_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {1158; CHECK-LABEL: masked_inc_test:1159; CHECK: # %bb.0:1160; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k11161; CHECK-NEXT: vpternlogd {{.*#+}} zmm1 = -11162; CHECK-NEXT: vpsubd %zmm1, %zmm0, %zmm0 {%k1}1163; CHECK-NEXT: retq1164 %mask = icmp ne <16 x i32> %mask1, zeroinitializer1165 %x = add <16 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1166 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i1167 ret <16 x i32> %r1168}1169 1170define <16 x i32> @masked_dec_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {1171; CHECK-LABEL: masked_dec_test:1172; CHECK: # %bb.0:1173; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k11174; CHECK-NEXT: vpternlogd {{.*#+}} zmm1 = -11175; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0 {%k1}1176; CHECK-NEXT: retq1177 %mask = icmp ne <16 x i32> %mask1, zeroinitializer1178 %x = sub <16 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>1179 %r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i1180 ret <16 x i32> %r1181}1182