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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=KNL3; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=SKX4 5define double @test1(double %a, double %b) nounwind {6; ALL-LABEL: test1:7; ALL: ## %bb.0:8; ALL-NEXT: vucomisd %xmm1, %xmm09; ALL-NEXT: jne LBB0_110; ALL-NEXT: jnp LBB0_211; ALL-NEXT: LBB0_1: ## %l112; ALL-NEXT: vsubsd %xmm1, %xmm0, %xmm013; ALL-NEXT: retq14; ALL-NEXT: LBB0_2: ## %l215; ALL-NEXT: vaddsd %xmm1, %xmm0, %xmm016; ALL-NEXT: retq17 %tobool = fcmp une double %a, %b18 br i1 %tobool, label %l1, label %l219 20l1:21 %c = fsub double %a, %b22 ret double %c23l2:24 %c1 = fadd double %a, %b25 ret double %c126}27 28define float @test2(float %a, float %b) nounwind {29; ALL-LABEL: test2:30; ALL: ## %bb.0:31; ALL-NEXT: vucomiss %xmm0, %xmm132; ALL-NEXT: jbe LBB1_233; ALL-NEXT: ## %bb.1: ## %l134; ALL-NEXT: vsubss %xmm1, %xmm0, %xmm035; ALL-NEXT: retq36; ALL-NEXT: LBB1_2: ## %l237; ALL-NEXT: vaddss %xmm1, %xmm0, %xmm038; ALL-NEXT: retq39 %tobool = fcmp olt float %a, %b40 br i1 %tobool, label %l1, label %l241 42l1:43 %c = fsub float %a, %b44 ret float %c45l2:46 %c1 = fadd float %a, %b47 ret float %c148}49 50define i32 @test3(float %a, float %b) {51; ALL-LABEL: test3:52; ALL: ## %bb.0:53; ALL-NEXT: vcmpeqss %xmm1, %xmm0, %k054; ALL-NEXT: kmovw %k0, %eax55; ALL-NEXT: retq56 57 %cmp10.i = fcmp oeq float %a, %b58 %conv11.i = zext i1 %cmp10.i to i3259 ret i32 %conv11.i60}61 62define float @test5(float %p) #0 {63; ALL-LABEL: test5:64; ALL: ## %bb.0: ## %entry65; ALL-NEXT: vxorps %xmm1, %xmm1, %xmm166; ALL-NEXT: vucomiss %xmm1, %xmm067; ALL-NEXT: jne LBB3_168; ALL-NEXT: jp LBB3_169; ALL-NEXT: ## %bb.2: ## %return70; ALL-NEXT: retq71; ALL-NEXT: LBB3_1: ## %if.end72; ALL-NEXT: vcmpltss %xmm0, %xmm1, %k173; ALL-NEXT: vmovss {{.*#+}} xmm0 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0]74; ALL-NEXT: vmovss {{.*#+}} xmm0 {%k1} = [1.0E+0,0.0E+0,0.0E+0,0.0E+0]75; ALL-NEXT: retq76entry:77 %cmp = fcmp oeq float %p, 0.000000e+0078 br i1 %cmp, label %return, label %if.end79 80if.end: ; preds = %entry81 %cmp1 = fcmp ogt float %p, 0.000000e+0082 %cond = select i1 %cmp1, float 1.000000e+00, float -1.000000e+0083 br label %return84 85return: ; preds = %if.end, %entry86 %retval.0 = phi float [ %cond, %if.end ], [ %p, %entry ]87 ret float %retval.088}89 90define i32 @test6(i32 %a, i32 %b) {91; ALL-LABEL: test6:92; ALL: ## %bb.0:93; ALL-NEXT: xorl %eax, %eax94; ALL-NEXT: cmpl %esi, %edi95; ALL-NEXT: sete %al96; ALL-NEXT: retq97 %cmp = icmp eq i32 %a, %b98 %res = zext i1 %cmp to i3299 ret i32 %res100}101 102define i32 @test7(double %x, double %y) #2 {103; ALL-LABEL: test7:104; ALL: ## %bb.0: ## %entry105; ALL-NEXT: xorl %eax, %eax106; ALL-NEXT: vucomisd %xmm1, %xmm0107; ALL-NEXT: setne %al108; ALL-NEXT: retq109entry:110 %0 = fcmp one double %x, %y111 %or = zext i1 %0 to i32112 ret i32 %or113}114 115define i32 @test8(i32 %a1, i32 %a2, i32 %a3) {116; ALL-LABEL: test8:117; ALL: ## %bb.0:118; ALL-NEXT: notl %edi119; ALL-NEXT: addl $-2147483648, %esi ## imm = 0x80000000120; ALL-NEXT: testl %edx, %edx121; ALL-NEXT: movl $1, %eax122; ALL-NEXT: cmovel %eax, %edx123; ALL-NEXT: orl %edi, %esi124; ALL-NEXT: cmovnel %edx, %eax125; ALL-NEXT: retq126 %tmp1 = icmp eq i32 %a1, -1127 %tmp2 = icmp eq i32 %a2, -2147483648128 %tmp3 = and i1 %tmp1, %tmp2129 %tmp4 = icmp eq i32 %a3, 0130 %tmp5 = or i1 %tmp3, %tmp4131 %res = select i1 %tmp5, i32 1, i32 %a3132 ret i32 %res133}134 135define i32 @test9(i64 %a) {136; ALL-LABEL: test9:137; ALL: ## %bb.0:138; ALL-NEXT: testb $1, %dil139; ALL-NEXT: jne LBB7_2140; ALL-NEXT: ## %bb.1: ## %A141; ALL-NEXT: movl $6, %eax142; ALL-NEXT: retq143; ALL-NEXT: LBB7_2: ## %B144; ALL-NEXT: movl $7, %eax145; ALL-NEXT: retq146 %b = and i64 %a, 1147 %cmp10.i = icmp eq i64 %b, 0148 br i1 %cmp10.i, label %A, label %B149A:150 ret i32 6151B:152 ret i32 7153}154 155define i32 @test10(i64 %b, i64 %c, i1 %d) {156; ALL-LABEL: test10:157; ALL: ## %bb.0:158; ALL-NEXT: cmpq %rsi, %rdi159; ALL-NEXT: sete %al160; ALL-NEXT: notb %dl161; ALL-NEXT: testb %al, %dl162; ALL-NEXT: je LBB8_1163; ALL-NEXT: ## %bb.2: ## %if.end.i164; ALL-NEXT: movl $6, %eax165; ALL-NEXT: retq166; ALL-NEXT: LBB8_1: ## %if.then.i167; ALL-NEXT: movl $5, %eax168; ALL-NEXT: retq169 170 %cmp8.i = icmp eq i64 %b, %c171 %or1 = or i1 %d, %cmp8.i172 %xor1 = xor i1 %d, %or1173 br i1 %xor1, label %if.end.i, label %if.then.i174 175if.then.i:176 ret i32 5177 178if.end.i:179 ret i32 6180}181 182; This test previously caused an infinite loop in legalize vector ops. Due to183; CSE triggering on the call to UpdateNodeOperands and the resulting node not184; being passed to LowerOperation. The add is needed to force the zext into a185; sext on that path. The shuffle keeps the zext alive. The xor somehow186; influences the zext to be visited before the sext exposing the CSE opportunity187; for the sext since zext of setcc is custom legalized to a sext and shift.188define <8 x i32> @legalize_loop(<8 x double> %arg) {189; KNL-LABEL: legalize_loop:190; KNL: ## %bb.0:191; KNL-NEXT: vxorpd %xmm1, %xmm1, %xmm1192; KNL-NEXT: vcmpnltpd %zmm0, %zmm1, %k1193; KNL-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1194; KNL-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[3,2,1,0,7,6,5,4]195; KNL-NEXT: vpsrld $31, %ymm1, %ymm1196; KNL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,0,1]197; KNL-NEXT: vpsubd %ymm0, %ymm1, %ymm0198; KNL-NEXT: retq199;200; SKX-LABEL: legalize_loop:201; SKX: ## %bb.0:202; SKX-NEXT: vxorpd %xmm1, %xmm1, %xmm1203; SKX-NEXT: vcmpnltpd %zmm0, %zmm1, %k0204; SKX-NEXT: vpmovm2d %k0, %ymm0205; SKX-NEXT: vpshufd {{.*#+}} ymm1 = ymm0[3,2,1,0,7,6,5,4]206; SKX-NEXT: vpsrld $31, %ymm1, %ymm1207; SKX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,0,1]208; SKX-NEXT: vpsubd %ymm0, %ymm1, %ymm0209; SKX-NEXT: retq210 %tmp = fcmp ogt <8 x double> %arg, zeroinitializer211 %tmp1 = xor <8 x i1> %tmp, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>212 %tmp2 = zext <8 x i1> %tmp1 to <8 x i32>213 %tmp3 = shufflevector <8 x i32> %tmp2, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>214 %tmp4 = add <8 x i32> %tmp2, %tmp3215 ret <8 x i32> %tmp4216}217