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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -O2 -mattr=avx512f -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK643; RUN: llc < %s -O2 -mattr=avx512f -mtriple=i386-unknown | FileCheck %s --check-prefix=CHECK324; RUN: llc < %s -O2 -mattr=avx512vl -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK645; RUN: llc < %s -O2 -mattr=avx512vl -mtriple=i386-unknown | FileCheck %s --check-prefix=CHECK326 7define <4 x float> @test_mm_mask_move_ss(<4 x float> %__W, i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {8; CHECK64-LABEL: test_mm_mask_move_ss:9; CHECK64: # %bb.0: # %entry10; CHECK64-NEXT: kmovw %edi, %k111; CHECK64-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}12; CHECK64-NEXT: retq13;14; CHECK32-LABEL: test_mm_mask_move_ss:15; CHECK32: # %bb.0: # %entry16; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %eax17; CHECK32-NEXT: kmovw %eax, %k118; CHECK32-NEXT: vmovss %xmm2, %xmm1, %xmm0 {%k1}19; CHECK32-NEXT: retl20entry:21 %0 = and i8 %__U, 122 %tobool.i = icmp ne i8 %0, 023 %__B.elt.i = extractelement <4 x float> %__B, i32 024 %__W.elt.i = extractelement <4 x float> %__W, i32 025 %vecext1.i = select i1 %tobool.i, float %__B.elt.i, float %__W.elt.i26 %vecins.i = insertelement <4 x float> %__A, float %vecext1.i, i32 027 ret <4 x float> %vecins.i28}29 30define <4 x float> @test_mm_maskz_move_ss(i8 zeroext %__U, <4 x float> %__A, <4 x float> %__B) local_unnamed_addr #0 {31; CHECK64-LABEL: test_mm_maskz_move_ss:32; CHECK64: # %bb.0: # %entry33; CHECK64-NEXT: kmovw %edi, %k134; CHECK64-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}35; CHECK64-NEXT: retq36;37; CHECK32-LABEL: test_mm_maskz_move_ss:38; CHECK32: # %bb.0: # %entry39; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %eax40; CHECK32-NEXT: kmovw %eax, %k141; CHECK32-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} {z}42; CHECK32-NEXT: retl43entry:44 %0 = and i8 %__U, 145 %tobool.i = icmp ne i8 %0, 046 %vecext.i = extractelement <4 x float> %__B, i32 047 %cond.i = select i1 %tobool.i, float %vecext.i, float 0.000000e+0048 %vecins.i = insertelement <4 x float> %__A, float %cond.i, i32 049 ret <4 x float> %vecins.i50}51 52define <2 x double> @test_mm_mask_move_sd(<2 x double> %__W, i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {53; CHECK64-LABEL: test_mm_mask_move_sd:54; CHECK64: # %bb.0: # %entry55; CHECK64-NEXT: kmovw %edi, %k156; CHECK64-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}57; CHECK64-NEXT: retq58;59; CHECK32-LABEL: test_mm_mask_move_sd:60; CHECK32: # %bb.0: # %entry61; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %eax62; CHECK32-NEXT: kmovw %eax, %k163; CHECK32-NEXT: vmovsd %xmm2, %xmm1, %xmm0 {%k1}64; CHECK32-NEXT: retl65entry:66 %0 = and i8 %__U, 167 %tobool.i = icmp ne i8 %0, 068 %__B.elt.i = extractelement <2 x double> %__B, i32 069 %__W.elt.i = extractelement <2 x double> %__W, i32 070 %vecext1.i = select i1 %tobool.i, double %__B.elt.i, double %__W.elt.i71 %vecins.i = insertelement <2 x double> %__A, double %vecext1.i, i32 072 ret <2 x double> %vecins.i73}74 75define <2 x double> @test_mm_maskz_move_sd(i8 zeroext %__U, <2 x double> %__A, <2 x double> %__B) local_unnamed_addr #0 {76; CHECK64-LABEL: test_mm_maskz_move_sd:77; CHECK64: # %bb.0: # %entry78; CHECK64-NEXT: kmovw %edi, %k179; CHECK64-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}80; CHECK64-NEXT: retq81;82; CHECK32-LABEL: test_mm_maskz_move_sd:83; CHECK32: # %bb.0: # %entry84; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %eax85; CHECK32-NEXT: kmovw %eax, %k186; CHECK32-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} {z}87; CHECK32-NEXT: retl88entry:89 %0 = and i8 %__U, 190 %tobool.i = icmp ne i8 %0, 091 %vecext.i = extractelement <2 x double> %__B, i32 092 %cond.i = select i1 %tobool.i, double %vecext.i, double 0.000000e+0093 %vecins.i = insertelement <2 x double> %__A, double %cond.i, i32 094 ret <2 x double> %vecins.i95}96 97define void @test_mm_mask_store_ss(ptr %__W, i8 zeroext %__U, <4 x float> %__A) local_unnamed_addr #1 {98; CHECK64-LABEL: test_mm_mask_store_ss:99; CHECK64: # %bb.0: # %entry100; CHECK64-NEXT: kmovw %esi, %k1101; CHECK64-NEXT: vmovss %xmm0, (%rdi) {%k1}102; CHECK64-NEXT: retq103;104; CHECK32-LABEL: test_mm_mask_store_ss:105; CHECK32: # %bb.0: # %entry106; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax107; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx108; CHECK32-NEXT: kmovw %ecx, %k1109; CHECK32-NEXT: vmovss %xmm0, (%eax) {%k1}110; CHECK32-NEXT: retl111entry:112 %shuffle.i.i = shufflevector <4 x float> %__A, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>113 %0 = and i8 %__U, 1114 %conv2.i = zext i8 %0 to i16115 %1 = bitcast i16 %conv2.i to <16 x i1>116 tail call void @llvm.masked.store.v16f32.p0(<16 x float> %shuffle.i.i, ptr %__W, i32 16, <16 x i1> %1) #5117 ret void118}119 120define void @test_mm_mask_store_sd(ptr %__W, i8 zeroext %__U, <2 x double> %__A) local_unnamed_addr #1 {121; CHECK64-LABEL: test_mm_mask_store_sd:122; CHECK64: # %bb.0: # %entry123; CHECK64-NEXT: kmovw %esi, %k1124; CHECK64-NEXT: vmovsd %xmm0, (%rdi) {%k1}125; CHECK64-NEXT: retq126;127; CHECK32-LABEL: test_mm_mask_store_sd:128; CHECK32: # %bb.0: # %entry129; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax130; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx131; CHECK32-NEXT: kmovw %ecx, %k1132; CHECK32-NEXT: vmovsd %xmm0, (%eax) {%k1}133; CHECK32-NEXT: retl134entry:135 %shuffle.i.i = shufflevector <2 x double> %__A, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>136 %0 = and i8 %__U, 1137 %1 = bitcast i8 %0 to <8 x i1>138 tail call void @llvm.masked.store.v8f64.p0(<8 x double> %shuffle.i.i, ptr %__W, i32 16, <8 x i1> %1) #5139 ret void140}141 142define <4 x float> @test_mm_mask_load_ss(<4 x float> %__A, i8 zeroext %__U, ptr %__W) local_unnamed_addr #2 {143; CHECK64-LABEL: test_mm_mask_load_ss:144; CHECK64: # %bb.0: # %entry145; CHECK64-NEXT: kmovw %edi, %k1146; CHECK64-NEXT: vmovss {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero147; CHECK64-NEXT: retq148;149; CHECK32-LABEL: test_mm_mask_load_ss:150; CHECK32: # %bb.0: # %entry151; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax152; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx153; CHECK32-NEXT: kmovw %ecx, %k1154; CHECK32-NEXT: vmovss {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero155; CHECK32-NEXT: retl156entry:157 %shuffle.i = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>158 %shuffle.i.i = shufflevector <4 x float> %shuffle.i, <4 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>159 %0 = and i8 %__U, 1160 %conv2.i = zext i8 %0 to i16161 %1 = bitcast i16 %conv2.i to <16 x i1>162 %2 = tail call <16 x float> @llvm.masked.load.v16f32.p0(ptr %__W, i32 16, <16 x i1> %1, <16 x float> %shuffle.i.i) #5163 %shuffle4.i = shufflevector <16 x float> %2, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>164 ret <4 x float> %shuffle4.i165}166 167define <2 x double> @test_mm_mask_load_sd(<2 x double> %__A, i8 zeroext %__U, ptr %__W) local_unnamed_addr #2 {168; CHECK64-LABEL: test_mm_mask_load_sd:169; CHECK64: # %bb.0: # %entry170; CHECK64-NEXT: kmovw %edi, %k1171; CHECK64-NEXT: vmovsd {{.*#+}} xmm0 {%k1} = mem[0],zero172; CHECK64-NEXT: retq173;174; CHECK32-LABEL: test_mm_mask_load_sd:175; CHECK32: # %bb.0: # %entry176; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax177; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx178; CHECK32-NEXT: kmovw %ecx, %k1179; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 {%k1} = mem[0],zero180; CHECK32-NEXT: retl181entry:182 %shuffle5.i = insertelement <2 x double> %__A, double 0.000000e+00, i32 1183 %shuffle.i.i = shufflevector <2 x double> %shuffle5.i, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>184 %0 = and i8 %__U, 1185 %1 = bitcast i8 %0 to <8 x i1>186 %2 = tail call <8 x double> @llvm.masked.load.v8f64.p0(ptr %__W, i32 16, <8 x i1> %1, <8 x double> %shuffle.i.i) #5187 %shuffle3.i = shufflevector <8 x double> %2, <8 x double> undef, <2 x i32> <i32 0, i32 1>188 ret <2 x double> %shuffle3.i189}190 191define <4 x float> @test_mm_maskz_load_ss(i8 zeroext %__U, ptr %__W) local_unnamed_addr #2 {192; CHECK64-LABEL: test_mm_maskz_load_ss:193; CHECK64: # %bb.0: # %entry194; CHECK64-NEXT: kmovw %edi, %k1195; CHECK64-NEXT: vmovss {{.*#+}} xmm0 {%k1} {z} = mem[0],zero,zero,zero196; CHECK64-NEXT: retq197;198; CHECK32-LABEL: test_mm_maskz_load_ss:199; CHECK32: # %bb.0: # %entry200; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax201; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx202; CHECK32-NEXT: kmovw %ecx, %k1203; CHECK32-NEXT: vmovss {{.*#+}} xmm0 {%k1} {z} = mem[0],zero,zero,zero204; CHECK32-NEXT: retl205entry:206 %0 = and i8 %__U, 1207 %conv2.i = zext i8 %0 to i16208 %1 = bitcast i16 %conv2.i to <16 x i1>209 %2 = tail call <16 x float> @llvm.masked.load.v16f32.p0(ptr %__W, i32 16, <16 x i1> %1, <16 x float> zeroinitializer) #5210 %shuffle.i = shufflevector <16 x float> %2, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>211 ret <4 x float> %shuffle.i212}213 214define <2 x double> @test_mm_maskz_load_sd(i8 zeroext %__U, ptr %__W) local_unnamed_addr #2 {215; CHECK64-LABEL: test_mm_maskz_load_sd:216; CHECK64: # %bb.0: # %entry217; CHECK64-NEXT: kmovw %edi, %k1218; CHECK64-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = mem[0],zero219; CHECK64-NEXT: retq220;221; CHECK32-LABEL: test_mm_maskz_load_sd:222; CHECK32: # %bb.0: # %entry223; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax224; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx225; CHECK32-NEXT: kmovw %ecx, %k1226; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = mem[0],zero227; CHECK32-NEXT: retl228entry:229 %0 = and i8 %__U, 1230 %1 = bitcast i8 %0 to <8 x i1>231 %2 = tail call <8 x double> @llvm.masked.load.v8f64.p0(ptr %__W, i32 16, <8 x i1> %1, <8 x double> zeroinitializer) #5232 %shuffle.i = shufflevector <8 x double> %2, <8 x double> undef, <2 x i32> <i32 0, i32 1>233 ret <2 x double> %shuffle.i234}235 236; The tests below match clang's newer codegen that uses 128-bit masked load/stores.237 238define void @test_mm_mask_store_ss_2(ptr %__P, i8 zeroext %__U, <4 x float> %__A) {239; CHECK64-LABEL: test_mm_mask_store_ss_2:240; CHECK64: # %bb.0: # %entry241; CHECK64-NEXT: kmovw %esi, %k1242; CHECK64-NEXT: vmovss %xmm0, (%rdi) {%k1}243; CHECK64-NEXT: retq244;245; CHECK32-LABEL: test_mm_mask_store_ss_2:246; CHECK32: # %bb.0: # %entry247; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax248; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx249; CHECK32-NEXT: kmovw %ecx, %k1250; CHECK32-NEXT: vmovss %xmm0, (%eax) {%k1}251; CHECK32-NEXT: retl252entry:253 %0 = and i8 %__U, 1254 %1 = bitcast i8 %0 to <8 x i1>255 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>256 tail call void @llvm.masked.store.v4f32.p0(<4 x float> %__A, ptr %__P, i32 1, <4 x i1> %extract.i)257 ret void258}259 260define void @test_mm_mask_store_sd_2(ptr %__P, i8 zeroext %__U, <2 x double> %__A) {261; CHECK64-LABEL: test_mm_mask_store_sd_2:262; CHECK64: # %bb.0: # %entry263; CHECK64-NEXT: kmovw %esi, %k1264; CHECK64-NEXT: vmovsd %xmm0, (%rdi) {%k1}265; CHECK64-NEXT: retq266;267; CHECK32-LABEL: test_mm_mask_store_sd_2:268; CHECK32: # %bb.0: # %entry269; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax270; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx271; CHECK32-NEXT: kmovw %ecx, %k1272; CHECK32-NEXT: vmovsd %xmm0, (%eax) {%k1}273; CHECK32-NEXT: retl274entry:275 %0 = and i8 %__U, 1276 %1 = bitcast i8 %0 to <8 x i1>277 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> <i32 0, i32 1>278 tail call void @llvm.masked.store.v2f64.p0(<2 x double> %__A, ptr %__P, i32 1, <2 x i1> %extract.i)279 ret void280}281 282define <4 x float> @test_mm_mask_load_ss_2(<4 x float> %__A, i8 zeroext %__U, ptr readonly %__W) {283; CHECK64-LABEL: test_mm_mask_load_ss_2:284; CHECK64: # %bb.0: # %entry285; CHECK64-NEXT: kmovw %edi, %k1286; CHECK64-NEXT: vmovss {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero287; CHECK64-NEXT: retq288;289; CHECK32-LABEL: test_mm_mask_load_ss_2:290; CHECK32: # %bb.0: # %entry291; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax292; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx293; CHECK32-NEXT: kmovw %ecx, %k1294; CHECK32-NEXT: vmovss {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero295; CHECK32-NEXT: retl296entry:297 %shuffle.i = shufflevector <4 x float> %__A, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 4>298 %0 = and i8 %__U, 1299 %1 = bitcast i8 %0 to <8 x i1>300 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>301 %2 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %__W, i32 1, <4 x i1> %extract.i, <4 x float> %shuffle.i)302 ret <4 x float> %2303}304 305define <4 x float> @test_mm_maskz_load_ss_2(i8 zeroext %__U, ptr readonly %__W) {306; CHECK64-LABEL: test_mm_maskz_load_ss_2:307; CHECK64: # %bb.0: # %entry308; CHECK64-NEXT: kmovw %edi, %k1309; CHECK64-NEXT: vmovss {{.*#+}} xmm0 {%k1} {z} = mem[0],zero,zero,zero310; CHECK64-NEXT: retq311;312; CHECK32-LABEL: test_mm_maskz_load_ss_2:313; CHECK32: # %bb.0: # %entry314; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax315; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx316; CHECK32-NEXT: kmovw %ecx, %k1317; CHECK32-NEXT: vmovss {{.*#+}} xmm0 {%k1} {z} = mem[0],zero,zero,zero318; CHECK32-NEXT: retl319entry:320 %0 = and i8 %__U, 1321 %1 = bitcast i8 %0 to <8 x i1>322 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>323 %2 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %__W, i32 1, <4 x i1> %extract.i, <4 x float> zeroinitializer)324 ret <4 x float> %2325}326 327define <2 x double> @test_mm_mask_load_sd_2(<2 x double> %__A, i8 zeroext %__U, ptr readonly %__W) {328; CHECK64-LABEL: test_mm_mask_load_sd_2:329; CHECK64: # %bb.0: # %entry330; CHECK64-NEXT: kmovw %edi, %k1331; CHECK64-NEXT: vmovsd {{.*#+}} xmm0 {%k1} = mem[0],zero332; CHECK64-NEXT: retq333;334; CHECK32-LABEL: test_mm_mask_load_sd_2:335; CHECK32: # %bb.0: # %entry336; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax337; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx338; CHECK32-NEXT: kmovw %ecx, %k1339; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 {%k1} = mem[0],zero340; CHECK32-NEXT: retl341entry:342 %shuffle3.i = insertelement <2 x double> %__A, double 0.000000e+00, i32 1343 %0 = and i8 %__U, 1344 %1 = bitcast i8 %0 to <8 x i1>345 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> <i32 0, i32 1>346 %2 = tail call <2 x double> @llvm.masked.load.v2f64.p0(ptr %__W, i32 1, <2 x i1> %extract.i, <2 x double> %shuffle3.i)347 ret <2 x double> %2348}349 350define <2 x double> @test_mm_maskz_load_sd_2(i8 zeroext %__U, ptr readonly %__W) {351; CHECK64-LABEL: test_mm_maskz_load_sd_2:352; CHECK64: # %bb.0: # %entry353; CHECK64-NEXT: kmovw %edi, %k1354; CHECK64-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = mem[0],zero355; CHECK64-NEXT: retq356;357; CHECK32-LABEL: test_mm_maskz_load_sd_2:358; CHECK32: # %bb.0: # %entry359; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax360; CHECK32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx361; CHECK32-NEXT: kmovw %ecx, %k1362; CHECK32-NEXT: vmovsd {{.*#+}} xmm0 {%k1} {z} = mem[0],zero363; CHECK32-NEXT: retl364entry:365 %0 = and i8 %__U, 1366 %1 = bitcast i8 %0 to <8 x i1>367 %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <2 x i32> <i32 0, i32 1>368 %2 = tail call <2 x double> @llvm.masked.load.v2f64.p0(ptr %__W, i32 1, <2 x i1> %extract.i, <2 x double> zeroinitializer)369 ret <2 x double> %2370}371 372 373declare void @llvm.masked.store.v16f32.p0(<16 x float>, ptr, i32, <16 x i1>) #3374 375declare void @llvm.masked.store.v8f64.p0(<8 x double>, ptr, i32, <8 x i1>) #3376 377declare <16 x float> @llvm.masked.load.v16f32.p0(ptr, i32, <16 x i1>, <16 x float>) #4378 379declare <8 x double> @llvm.masked.load.v8f64.p0(ptr, i32, <8 x i1>, <8 x double>) #4380 381declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>)382 383declare void @llvm.masked.store.v2f64.p0(<2 x double>, ptr, i32, <2 x i1>)384 385declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32, <4 x i1>, <4 x float>)386 387declare <2 x double> @llvm.masked.load.v2f64.p0(ptr, i32, <2 x i1>, <2 x double>)388