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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512bw,avx512vl < %s | FileCheck %s3 4; Skylake-avx512 target supports masked load/store for i8 and i16 vectors5 6define <16 x i8> @test_mask_load_16xi8(<16 x i1> %mask, ptr %addr, <16 x i8> %val) {7; CHECK-LABEL: test_mask_load_16xi8:8; CHECK: ## %bb.0:9; CHECK-NEXT: vpsllw $7, %xmm0, %xmm010; CHECK-NEXT: vpmovb2m %xmm0, %k111; CHECK-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1} {z}12; CHECK-NEXT: retq13 %res = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %addr, i32 4, <16 x i1>%mask, <16 x i8> undef)14 ret <16 x i8> %res15}16declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32, <16 x i1>, <16 x i8>)17 18define <32 x i8> @test_mask_load_32xi8(<32 x i1> %mask, ptr %addr, <32 x i8> %val) {19; CHECK-LABEL: test_mask_load_32xi8:20; CHECK: ## %bb.0:21; CHECK-NEXT: vpsllw $7, %ymm0, %ymm022; CHECK-NEXT: vpmovb2m %ymm0, %k123; CHECK-NEXT: vpblendmb (%rdi), %ymm1, %ymm0 {%k1}24; CHECK-NEXT: retq25 %res = call <32 x i8> @llvm.masked.load.v32i8.p0(ptr %addr, i32 4, <32 x i1>%mask, <32 x i8> %val)26 ret <32 x i8> %res27}28declare <32 x i8> @llvm.masked.load.v32i8.p0(ptr, i32, <32 x i1>, <32 x i8>)29 30define <64 x i8> @test_mask_load_64xi8(<64 x i1> %mask, ptr %addr, <64 x i8> %val) {31; CHECK-LABEL: test_mask_load_64xi8:32; CHECK: ## %bb.0:33; CHECK-NEXT: vpsllw $7, %zmm0, %zmm034; CHECK-NEXT: vpmovb2m %zmm0, %k135; CHECK-NEXT: vpblendmb (%rdi), %zmm1, %zmm0 {%k1}36; CHECK-NEXT: retq37 %res = call <64 x i8> @llvm.masked.load.v64i8.p0(ptr %addr, i32 4, <64 x i1>%mask, <64 x i8> %val)38 ret <64 x i8> %res39}40declare <64 x i8> @llvm.masked.load.v64i8.p0(ptr, i32, <64 x i1>, <64 x i8>)41 42define <8 x i16> @test_mask_load_8xi16(<8 x i1> %mask, ptr %addr, <8 x i16> %val) {43; CHECK-LABEL: test_mask_load_8xi16:44; CHECK: ## %bb.0:45; CHECK-NEXT: vpsllw $15, %xmm0, %xmm046; CHECK-NEXT: vpmovw2m %xmm0, %k147; CHECK-NEXT: vmovdqu16 (%rdi), %xmm0 {%k1} {z}48; CHECK-NEXT: retq49 %res = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr, i32 4, <8 x i1>%mask, <8 x i16> undef)50 ret <8 x i16> %res51}52declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32, <8 x i1>, <8 x i16>)53 54define <16 x i16> @test_mask_load_16xi16(<16 x i1> %mask, ptr %addr, <16 x i16> %val) {55; CHECK-LABEL: test_mask_load_16xi16:56; CHECK: ## %bb.0:57; CHECK-NEXT: vpsllw $7, %xmm0, %xmm058; CHECK-NEXT: vpmovb2m %xmm0, %k159; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z}60; CHECK-NEXT: retq61 %res = call <16 x i16> @llvm.masked.load.v16i16.p0(ptr %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer)62 ret <16 x i16> %res63}64declare <16 x i16> @llvm.masked.load.v16i16.p0(ptr, i32, <16 x i1>, <16 x i16>)65 66define <32 x i16> @test_mask_load_32xi16(<32 x i1> %mask, ptr %addr, <32 x i16> %val) {67; CHECK-LABEL: test_mask_load_32xi16:68; CHECK: ## %bb.0:69; CHECK-NEXT: vpsllw $7, %ymm0, %ymm070; CHECK-NEXT: vpmovb2m %ymm0, %k171; CHECK-NEXT: vpblendmw (%rdi), %zmm1, %zmm0 {%k1}72; CHECK-NEXT: retq73 %res = call <32 x i16> @llvm.masked.load.v32i16.p0(ptr %addr, i32 4, <32 x i1>%mask, <32 x i16> %val)74 ret <32 x i16> %res75}76declare <32 x i16> @llvm.masked.load.v32i16.p0(ptr, i32, <32 x i1>, <32 x i16>)77 78define void @test_mask_store_16xi8(<16 x i1> %mask, ptr %addr, <16 x i8> %val) {79; CHECK-LABEL: test_mask_store_16xi8:80; CHECK: ## %bb.0:81; CHECK-NEXT: vpsllw $7, %xmm0, %xmm082; CHECK-NEXT: vpmovb2m %xmm0, %k183; CHECK-NEXT: vmovdqu8 %xmm1, (%rdi) {%k1}84; CHECK-NEXT: retq85 call void @llvm.masked.store.v16i8.p0(<16 x i8> %val, ptr %addr, i32 4, <16 x i1>%mask)86 ret void87}88declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32, <16 x i1>)89 90define void @test_mask_store_32xi8(<32 x i1> %mask, ptr %addr, <32 x i8> %val) {91; CHECK-LABEL: test_mask_store_32xi8:92; CHECK: ## %bb.0:93; CHECK-NEXT: vpsllw $7, %ymm0, %ymm094; CHECK-NEXT: vpmovb2m %ymm0, %k195; CHECK-NEXT: vmovdqu8 %ymm1, (%rdi) {%k1}96; CHECK-NEXT: vzeroupper97; CHECK-NEXT: retq98 call void @llvm.masked.store.v32i8.p0(<32 x i8> %val, ptr %addr, i32 4, <32 x i1>%mask)99 ret void100}101declare void @llvm.masked.store.v32i8.p0(<32 x i8>, ptr, i32, <32 x i1>)102 103define void @test_mask_store_64xi8(<64 x i1> %mask, ptr %addr, <64 x i8> %val) {104; CHECK-LABEL: test_mask_store_64xi8:105; CHECK: ## %bb.0:106; CHECK-NEXT: vpsllw $7, %zmm0, %zmm0107; CHECK-NEXT: vpmovb2m %zmm0, %k1108; CHECK-NEXT: vmovdqu8 %zmm1, (%rdi) {%k1}109; CHECK-NEXT: vzeroupper110; CHECK-NEXT: retq111 call void @llvm.masked.store.v64i8.p0(<64 x i8> %val, ptr %addr, i32 4, <64 x i1>%mask)112 ret void113}114declare void @llvm.masked.store.v64i8.p0(<64 x i8>, ptr, i32, <64 x i1>)115 116define void @test_mask_store_8xi16(<8 x i1> %mask, ptr %addr, <8 x i16> %val) {117; CHECK-LABEL: test_mask_store_8xi16:118; CHECK: ## %bb.0:119; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0120; CHECK-NEXT: vpmovw2m %xmm0, %k1121; CHECK-NEXT: vmovdqu16 %xmm1, (%rdi) {%k1}122; CHECK-NEXT: retq123 call void @llvm.masked.store.v8i16.p0(<8 x i16> %val, ptr %addr, i32 4, <8 x i1>%mask)124 ret void125}126declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32, <8 x i1>)127 128define void @test_mask_store_16xi16(<16 x i1> %mask, ptr %addr, <16 x i16> %val) {129; CHECK-LABEL: test_mask_store_16xi16:130; CHECK: ## %bb.0:131; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0132; CHECK-NEXT: vpmovb2m %xmm0, %k1133; CHECK-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}134; CHECK-NEXT: vzeroupper135; CHECK-NEXT: retq136 call void @llvm.masked.store.v16i16.p0(<16 x i16> %val, ptr %addr, i32 4, <16 x i1>%mask)137 ret void138}139declare void @llvm.masked.store.v16i16.p0(<16 x i16>, ptr, i32, <16 x i1>)140 141define void @test_mask_store_32xi16(<32 x i1> %mask, ptr %addr, <32 x i16> %val) {142; CHECK-LABEL: test_mask_store_32xi16:143; CHECK: ## %bb.0:144; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0145; CHECK-NEXT: vpmovb2m %ymm0, %k1146; CHECK-NEXT: vmovdqu16 %zmm1, (%rdi) {%k1}147; CHECK-NEXT: vzeroupper148; CHECK-NEXT: retq149 call void @llvm.masked.store.v32i16.p0(<32 x i16> %val, ptr %addr, i32 4, <32 x i1>%mask)150 ret void151}152 153declare void @llvm.masked.store.v32i16.p0(<32 x i16>, ptr, i32, <32 x i1>)154 155; Make sure we scalarize masked loads of f16.156define <16 x half> @test_mask_load_16xf16(<16 x i1> %mask, ptr %addr) {157; CHECK-LABEL: test_mask_load_16xf16:158; CHECK: ## %bb.0:159; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0160; CHECK-NEXT: vpmovb2m %xmm0, %k1161; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z}162; CHECK-NEXT: retq163 %res = call <16 x half> @llvm.masked.load.v16f16(ptr %addr, i32 4, <16 x i1>%mask, <16 x half> zeroinitializer)164 ret <16 x half> %res165}166declare <16 x half> @llvm.masked.load.v16f16(ptr, i32, <16 x i1>, <16 x half>)167 168; Make sure we scalarize masked stores of f16.169define void @test_mask_store_16xf16(<16 x i1> %mask, ptr %addr, <16 x half> %val) {170; CHECK-LABEL: test_mask_store_16xf16:171; CHECK: ## %bb.0:172; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0173; CHECK-NEXT: vpmovb2m %xmm0, %k1174; CHECK-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}175; CHECK-NEXT: vzeroupper176; CHECK-NEXT: retq177 call void @llvm.masked.store.v16f16.p0(<16 x half> %val, ptr %addr, i32 4, <16 x i1>%mask)178 ret void179}180declare void @llvm.masked.store.v16f16.p0(<16 x half>, ptr, i32, <16 x i1>)181