494 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s3 4define i32 @test1(float %x) {5; CHECK-LABEL: test1:6; CHECK: ## %bb.0:7; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]8; CHECK-NEXT: retq ## encoding: [0xc3]9 %res = bitcast float %x to i3210 ret i32 %res11}12 13define <4 x i32> @test2(i32 %x) {14; CHECK-LABEL: test2:15; CHECK: ## %bb.0:16; CHECK-NEXT: vmovd %edi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc7]17; CHECK-NEXT: retq ## encoding: [0xc3]18 %res = insertelement <4 x i32>undef, i32 %x, i32 019 ret <4 x i32>%res20}21 22define <2 x i64> @test3(i64 %x) {23; CHECK-LABEL: test3:24; CHECK: ## %bb.0:25; CHECK-NEXT: vmovq %rdi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x6e,0xc7]26; CHECK-NEXT: retq ## encoding: [0xc3]27 %res = insertelement <2 x i64>undef, i64 %x, i32 028 ret <2 x i64>%res29}30 31define <4 x i32> @test4(ptr %x) {32; CHECK-LABEL: test4:33; CHECK: ## %bb.0:34; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero35; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]36; CHECK-NEXT: retq ## encoding: [0xc3]37 %y = load i32, ptr %x38 %res = insertelement <4 x i32>undef, i32 %y, i32 039 ret <4 x i32>%res40}41 42define void @test5(float %x, ptr %y) {43; CHECK-LABEL: test5:44; CHECK: ## %bb.0:45; CHECK-NEXT: vmovss %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x11,0x07]46; CHECK-NEXT: retq ## encoding: [0xc3]47 store float %x, ptr %y, align 448 ret void49}50 51define void @test6(double %x, ptr %y) {52; CHECK-LABEL: test6:53; CHECK: ## %bb.0:54; CHECK-NEXT: vmovsd %xmm0, (%rdi) ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x11,0x07]55; CHECK-NEXT: retq ## encoding: [0xc3]56 store double %x, ptr %y, align 857 ret void58}59 60define float @test7(ptr %x) {61; CHECK-LABEL: test7:62; CHECK: ## %bb.0:63; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero64; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]65; CHECK-NEXT: retq ## encoding: [0xc3]66 %y = load i32, ptr %x67 %res = bitcast i32 %y to float68 ret float %res69}70 71define i32 @test8(<4 x i32> %x) {72; CHECK-LABEL: test8:73; CHECK: ## %bb.0:74; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]75; CHECK-NEXT: retq ## encoding: [0xc3]76 %res = extractelement <4 x i32> %x, i32 077 ret i32 %res78}79 80define i64 @test9(<2 x i64> %x) {81; CHECK-LABEL: test9:82; CHECK: ## %bb.0:83; CHECK-NEXT: vmovq %xmm0, %rax ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x7e,0xc0]84; CHECK-NEXT: retq ## encoding: [0xc3]85 %res = extractelement <2 x i64> %x, i32 086 ret i64 %res87}88 89define <4 x i32> @test10(ptr %x) {90; CHECK-LABEL: test10:91; CHECK: ## %bb.0:92; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero93; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]94; CHECK-NEXT: retq ## encoding: [0xc3]95 %y = load i32, ptr %x, align 496 %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 097 ret <4 x i32>%res98}99 100define <4 x float> @test11(ptr %x) {101; CHECK-LABEL: test11:102; CHECK: ## %bb.0:103; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero104; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]105; CHECK-NEXT: retq ## encoding: [0xc3]106 %y = load float, ptr %x, align 4107 %res = insertelement <4 x float>zeroinitializer, float %y, i32 0108 ret <4 x float>%res109}110 111define <2 x double> @test12(ptr %x) {112; CHECK-LABEL: test12:113; CHECK: ## %bb.0:114; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero115; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x10,0x07]116; CHECK-NEXT: retq ## encoding: [0xc3]117 %y = load double, ptr %x, align 8118 %res = insertelement <2 x double>zeroinitializer, double %y, i32 0119 ret <2 x double>%res120}121 122define <2 x i64> @test13(i64 %x) {123; CHECK-LABEL: test13:124; CHECK: ## %bb.0:125; CHECK-NEXT: vmovq %rdi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xf9,0x6e,0xc7]126; CHECK-NEXT: retq ## encoding: [0xc3]127 %res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0128 ret <2 x i64>%res129}130 131define <4 x i32> @test14(i32 %x) {132; CHECK-LABEL: test14:133; CHECK: ## %bb.0:134; CHECK-NEXT: vmovd %edi, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6e,0xc7]135; CHECK-NEXT: retq ## encoding: [0xc3]136 %res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0137 ret <4 x i32>%res138}139 140define <4 x i32> @test15(ptr %x) {141; CHECK-LABEL: test15:142; CHECK: ## %bb.0:143; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero144; CHECK-NEXT: ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x07]145; CHECK-NEXT: retq ## encoding: [0xc3]146 %y = load i32, ptr %x, align 4147 %res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0148 ret <4 x i32>%res149}150 151define <16 x i32> @test16(ptr %addr) {152; CHECK-LABEL: test16:153; CHECK: ## %bb.0:154; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]155; CHECK-NEXT: retq ## encoding: [0xc3]156 %res = load <16 x i32>, ptr %addr, align 1157 ret <16 x i32>%res158}159 160define <16 x i32> @test17(ptr %addr) {161; CHECK-LABEL: test17:162; CHECK: ## %bb.0:163; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]164; CHECK-NEXT: retq ## encoding: [0xc3]165 %res = load <16 x i32>, ptr %addr, align 64166 ret <16 x i32>%res167}168 169define void @test18(ptr %addr, <8 x i64> %data) {170; CHECK-LABEL: test18:171; CHECK: ## %bb.0:172; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]173; CHECK-NEXT: retq ## encoding: [0xc3]174 store <8 x i64>%data, ptr %addr, align 64175 ret void176}177 178define void @test19(ptr %addr, <16 x i32> %data) {179; CHECK-LABEL: test19:180; CHECK: ## %bb.0:181; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]182; CHECK-NEXT: retq ## encoding: [0xc3]183 store <16 x i32>%data, ptr %addr, align 1184 ret void185}186 187define void @test20(ptr %addr, <16 x i32> %data) {188; CHECK-LABEL: test20:189; CHECK: ## %bb.0:190; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]191; CHECK-NEXT: retq ## encoding: [0xc3]192 store <16 x i32>%data, ptr %addr, align 64193 ret void194}195 196define <8 x i64> @test21(ptr %addr) {197; CHECK-LABEL: test21:198; CHECK: ## %bb.0:199; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]200; CHECK-NEXT: retq ## encoding: [0xc3]201 %res = load <8 x i64>, ptr %addr, align 64202 ret <8 x i64>%res203}204 205define void @test22(ptr %addr, <8 x i64> %data) {206; CHECK-LABEL: test22:207; CHECK: ## %bb.0:208; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]209; CHECK-NEXT: retq ## encoding: [0xc3]210 store <8 x i64>%data, ptr %addr, align 1211 ret void212}213 214define <8 x i64> @test23(ptr %addr) {215; CHECK-LABEL: test23:216; CHECK: ## %bb.0:217; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]218; CHECK-NEXT: retq ## encoding: [0xc3]219 %res = load <8 x i64>, ptr %addr, align 1220 ret <8 x i64>%res221}222 223define void @test24(ptr %addr, <8 x double> %data) {224; CHECK-LABEL: test24:225; CHECK: ## %bb.0:226; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]227; CHECK-NEXT: retq ## encoding: [0xc3]228 store <8 x double>%data, ptr %addr, align 64229 ret void230}231 232define <8 x double> @test25(ptr %addr) {233; CHECK-LABEL: test25:234; CHECK: ## %bb.0:235; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]236; CHECK-NEXT: retq ## encoding: [0xc3]237 %res = load <8 x double>, ptr %addr, align 64238 ret <8 x double>%res239}240 241define void @test26(ptr %addr, <16 x float> %data) {242; CHECK-LABEL: test26:243; CHECK: ## %bb.0:244; CHECK-NEXT: vmovaps %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x29,0x07]245; CHECK-NEXT: retq ## encoding: [0xc3]246 store <16 x float>%data, ptr %addr, align 64247 ret void248}249 250define <16 x float> @test27(ptr %addr) {251; CHECK-LABEL: test27:252; CHECK: ## %bb.0:253; CHECK-NEXT: vmovaps (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0x07]254; CHECK-NEXT: retq ## encoding: [0xc3]255 %res = load <16 x float>, ptr %addr, align 64256 ret <16 x float>%res257}258 259define void @test28(ptr %addr, <8 x double> %data) {260; CHECK-LABEL: test28:261; CHECK: ## %bb.0:262; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]263; CHECK-NEXT: retq ## encoding: [0xc3]264 store <8 x double>%data, ptr %addr, align 1265 ret void266}267 268define <8 x double> @test29(ptr %addr) {269; CHECK-LABEL: test29:270; CHECK: ## %bb.0:271; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]272; CHECK-NEXT: retq ## encoding: [0xc3]273 %res = load <8 x double>, ptr %addr, align 1274 ret <8 x double>%res275}276 277define void @test30(ptr %addr, <16 x float> %data) {278; CHECK-LABEL: test30:279; CHECK: ## %bb.0:280; CHECK-NEXT: vmovups %zmm0, (%rdi) ## encoding: [0x62,0xf1,0x7c,0x48,0x11,0x07]281; CHECK-NEXT: retq ## encoding: [0xc3]282 store <16 x float>%data, ptr %addr, align 1283 ret void284}285 286define <16 x float> @test31(ptr %addr) {287; CHECK-LABEL: test31:288; CHECK: ## %bb.0:289; CHECK-NEXT: vmovups (%rdi), %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x10,0x07]290; CHECK-NEXT: retq ## encoding: [0xc3]291 %res = load <16 x float>, ptr %addr, align 1292 ret <16 x float>%res293}294 295define <16 x i32> @test32(ptr %addr, <16 x i32> %old, <16 x i32> %mask1) {296; CHECK-LABEL: test32:297; CHECK: ## %bb.0:298; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1 ## encoding: [0x62,0xf2,0x75,0x48,0x27,0xc9]299; CHECK-NEXT: vmovdqa32 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x49,0x6f,0x07]300; CHECK-NEXT: retq ## encoding: [0xc3]301 %mask = icmp ne <16 x i32> %mask1, zeroinitializer302 %r = load <16 x i32>, ptr %addr, align 64303 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old304 ret <16 x i32>%res305}306 307define <16 x i32> @test33(ptr %addr, <16 x i32> %old, <16 x i32> %mask1) {308; CHECK-LABEL: test33:309; CHECK: ## %bb.0:310; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1 ## encoding: [0x62,0xf2,0x75,0x48,0x27,0xc9]311; CHECK-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7e,0x49,0x6f,0x07]312; CHECK-NEXT: retq ## encoding: [0xc3]313 %mask = icmp ne <16 x i32> %mask1, zeroinitializer314 %r = load <16 x i32>, ptr %addr, align 1315 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> %old316 ret <16 x i32>%res317}318 319define <16 x i32> @test34(ptr %addr, <16 x i32> %mask1) {320; CHECK-LABEL: test34:321; CHECK: ## %bb.0:322; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k1 ## encoding: [0x62,0xf2,0x7d,0x48,0x27,0xc8]323; CHECK-NEXT: vmovdqa32 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xc9,0x6f,0x07]324; CHECK-NEXT: retq ## encoding: [0xc3]325 %mask = icmp ne <16 x i32> %mask1, zeroinitializer326 %r = load <16 x i32>, ptr %addr, align 64327 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer328 ret <16 x i32>%res329}330 331define <16 x i32> @test35(ptr %addr, <16 x i32> %mask1) {332; CHECK-LABEL: test35:333; CHECK: ## %bb.0:334; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k1 ## encoding: [0x62,0xf2,0x7d,0x48,0x27,0xc8]335; CHECK-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7e,0xc9,0x6f,0x07]336; CHECK-NEXT: retq ## encoding: [0xc3]337 %mask = icmp ne <16 x i32> %mask1, zeroinitializer338 %r = load <16 x i32>, ptr %addr, align 1339 %res = select <16 x i1> %mask, <16 x i32> %r, <16 x i32> zeroinitializer340 ret <16 x i32>%res341}342 343define <8 x i64> @test36(ptr %addr, <8 x i64> %old, <8 x i64> %mask1) {344; CHECK-LABEL: test36:345; CHECK: ## %bb.0:346; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 ## encoding: [0x62,0xf2,0xf5,0x48,0x27,0xc9]347; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x6f,0x07]348; CHECK-NEXT: retq ## encoding: [0xc3]349 %mask = icmp ne <8 x i64> %mask1, zeroinitializer350 %r = load <8 x i64>, ptr %addr, align 64351 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old352 ret <8 x i64>%res353}354 355define <8 x i64> @test37(ptr %addr, <8 x i64> %old, <8 x i64> %mask1) {356; CHECK-LABEL: test37:357; CHECK: ## %bb.0:358; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 ## encoding: [0x62,0xf2,0xf5,0x48,0x27,0xc9]359; CHECK-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfe,0x49,0x6f,0x07]360; CHECK-NEXT: retq ## encoding: [0xc3]361 %mask = icmp ne <8 x i64> %mask1, zeroinitializer362 %r = load <8 x i64>, ptr %addr, align 1363 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> %old364 ret <8 x i64>%res365}366 367define <8 x i64> @test38(ptr %addr, <8 x i64> %mask1) {368; CHECK-LABEL: test38:369; CHECK: ## %bb.0:370; CHECK-NEXT: vptestmq %zmm0, %zmm0, %k1 ## encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc8]371; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x6f,0x07]372; CHECK-NEXT: retq ## encoding: [0xc3]373 %mask = icmp ne <8 x i64> %mask1, zeroinitializer374 %r = load <8 x i64>, ptr %addr, align 64375 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer376 ret <8 x i64>%res377}378 379define <8 x i64> @test39(ptr %addr, <8 x i64> %mask1) {380; CHECK-LABEL: test39:381; CHECK: ## %bb.0:382; CHECK-NEXT: vptestmq %zmm0, %zmm0, %k1 ## encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc8]383; CHECK-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfe,0xc9,0x6f,0x07]384; CHECK-NEXT: retq ## encoding: [0xc3]385 %mask = icmp ne <8 x i64> %mask1, zeroinitializer386 %r = load <8 x i64>, ptr %addr, align 1387 %res = select <8 x i1> %mask, <8 x i64> %r, <8 x i64> zeroinitializer388 ret <8 x i64>%res389}390 391define <16 x float> @test40(ptr %addr, <16 x float> %old, <16 x float> %mask1) {392; CHECK-LABEL: test40:393; CHECK: ## %bb.0:394; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2]395; CHECK-NEXT: vcmpneq_oqps %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0x74,0x48,0xc2,0xca,0x0c]396; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x28,0x07]397; CHECK-NEXT: retq ## encoding: [0xc3]398 %mask = fcmp one <16 x float> %mask1, zeroinitializer399 %r = load <16 x float>, ptr %addr, align 64400 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old401 ret <16 x float>%res402}403 404define <16 x float> @test41(ptr %addr, <16 x float> %old, <16 x float> %mask1) {405; CHECK-LABEL: test41:406; CHECK: ## %bb.0:407; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2]408; CHECK-NEXT: vcmpneq_oqps %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0x74,0x48,0xc2,0xca,0x0c]409; CHECK-NEXT: vmovups (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0x7c,0x49,0x10,0x07]410; CHECK-NEXT: retq ## encoding: [0xc3]411 %mask = fcmp one <16 x float> %mask1, zeroinitializer412 %r = load <16 x float>, ptr %addr, align 1413 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> %old414 ret <16 x float>%res415}416 417define <16 x float> @test42(ptr %addr, <16 x float> %mask1) {418; CHECK-LABEL: test42:419; CHECK: ## %bb.0:420; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x57,0xc9]421; CHECK-NEXT: vcmpneq_oqps %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0x7c,0x48,0xc2,0xc9,0x0c]422; CHECK-NEXT: vmovaps (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x28,0x07]423; CHECK-NEXT: retq ## encoding: [0xc3]424 %mask = fcmp one <16 x float> %mask1, zeroinitializer425 %r = load <16 x float>, ptr %addr, align 64426 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer427 ret <16 x float>%res428}429 430define <16 x float> @test43(ptr %addr, <16 x float> %mask1) {431; CHECK-LABEL: test43:432; CHECK: ## %bb.0:433; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x57,0xc9]434; CHECK-NEXT: vcmpneq_oqps %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0x7c,0x48,0xc2,0xc9,0x0c]435; CHECK-NEXT: vmovups (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xc9,0x10,0x07]436; CHECK-NEXT: retq ## encoding: [0xc3]437 %mask = fcmp one <16 x float> %mask1, zeroinitializer438 %r = load <16 x float>, ptr %addr, align 1439 %res = select <16 x i1> %mask, <16 x float> %r, <16 x float> zeroinitializer440 ret <16 x float>%res441}442 443define <8 x double> @test44(ptr %addr, <8 x double> %old, <8 x double> %mask1) {444; CHECK-LABEL: test44:445; CHECK: ## %bb.0:446; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0x57,0xd2]447; CHECK-NEXT: vcmpneq_oqpd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0xf5,0x48,0xc2,0xca,0x0c]448; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x28,0x07]449; CHECK-NEXT: retq ## encoding: [0xc3]450 %mask = fcmp one <8 x double> %mask1, zeroinitializer451 %r = load <8 x double>, ptr %addr, align 64452 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old453 ret <8 x double>%res454}455 456define <8 x double> @test45(ptr %addr, <8 x double> %old, <8 x double> %mask1) {457; CHECK-LABEL: test45:458; CHECK: ## %bb.0:459; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe9,0x57,0xd2]460; CHECK-NEXT: vcmpneq_oqpd %zmm2, %zmm1, %k1 ## encoding: [0x62,0xf1,0xf5,0x48,0xc2,0xca,0x0c]461; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1} ## encoding: [0x62,0xf1,0xfd,0x49,0x10,0x07]462; CHECK-NEXT: retq ## encoding: [0xc3]463 %mask = fcmp one <8 x double> %mask1, zeroinitializer464 %r = load <8 x double>, ptr %addr, align 1465 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> %old466 ret <8 x double>%res467}468 469define <8 x double> @test46(ptr %addr, <8 x double> %mask1) {470; CHECK-LABEL: test46:471; CHECK: ## %bb.0:472; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]473; CHECK-NEXT: vcmpneq_oqpd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc9,0x0c]474; CHECK-NEXT: vmovapd (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x28,0x07]475; CHECK-NEXT: retq ## encoding: [0xc3]476 %mask = fcmp one <8 x double> %mask1, zeroinitializer477 %r = load <8 x double>, ptr %addr, align 64478 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer479 ret <8 x double>%res480}481 482define <8 x double> @test47(ptr %addr, <8 x double> %mask1) {483; CHECK-LABEL: test47:484; CHECK: ## %bb.0:485; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ## encoding: [0xc5,0xf1,0x57,0xc9]486; CHECK-NEXT: vcmpneq_oqpd %zmm1, %zmm0, %k1 ## encoding: [0x62,0xf1,0xfd,0x48,0xc2,0xc9,0x0c]487; CHECK-NEXT: vmovupd (%rdi), %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xc9,0x10,0x07]488; CHECK-NEXT: retq ## encoding: [0xc3]489 %mask = fcmp one <8 x double> %mask1, zeroinitializer490 %r = load <8 x double>, ptr %addr, align 1491 %res = select <8 x i1> %mask, <8 x double> %r, <8 x double> zeroinitializer492 ret <8 x double>%res493}494