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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512f,+avx512vl %s -o - | FileCheck %s3 4; FIXME: 128-bit shuffles of 256-bit vectors cases should be fixed by PR343595 6define <8 x float> @test_8xfloat_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2) {7; CHECK-LABEL: test_8xfloat_shuff_mask0:8; CHECK: # %bb.0:9; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]10; CHECK-NEXT: retq11 %res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>12 ret <8 x float> %res13}14define <8 x float> @test_8xfloat_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %vec3, <8 x float> %mask) {15; CHECK-LABEL: test_8xfloat_masked_shuff_mask0:16; CHECK: # %bb.0:17; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm418; CHECK-NEXT: vcmpeqps %ymm4, %ymm3, %k119; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[0,1,2,3]20; CHECK-NEXT: vmovaps %ymm2, %ymm021; CHECK-NEXT: retq22 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>23 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer24 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec325 ret <8 x float> %res26}27 28define <8 x float> @test_8xfloat_zero_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %mask) {29; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mask0:30; CHECK: # %bb.0:31; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm332; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k133; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[0,1,2,3]34; CHECK-NEXT: retq35 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>36 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer37 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer38 ret <8 x float> %res39}40define <8 x float> @test_8xfloat_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %vec3, <8 x float> %mask) {41; CHECK-LABEL: test_8xfloat_masked_shuff_mask1:42; CHECK: # %bb.0:43; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm444; CHECK-NEXT: vcmpeqps %ymm4, %ymm3, %k145; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[0,1,2,3]46; CHECK-NEXT: vmovaps %ymm2, %ymm047; CHECK-NEXT: retq48 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>49 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer50 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec351 ret <8 x float> %res52}53 54define <8 x float> @test_8xfloat_zero_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %mask) {55; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mask1:56; CHECK: # %bb.0:57; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm358; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k159; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[0,1,2,3]60; CHECK-NEXT: retq61 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>62 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer63 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer64 ret <8 x float> %res65}66define <8 x float> @test_8xfloat_masked_shuff_mask2(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %vec3, <8 x float> %mask) {67; CHECK-LABEL: test_8xfloat_masked_shuff_mask2:68; CHECK: # %bb.0:69; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm470; CHECK-NEXT: vcmpeqps %ymm4, %ymm3, %k171; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[4,5,6,7]72; CHECK-NEXT: vmovaps %ymm2, %ymm073; CHECK-NEXT: retq74 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>75 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer76 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec377 ret <8 x float> %res78}79 80define <8 x float> @test_8xfloat_zero_masked_shuff_mask2(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %mask) {81; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mask2:82; CHECK: # %bb.0:83; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm384; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k185; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[4,5,6,7]86; CHECK-NEXT: retq87 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>88 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer89 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer90 ret <8 x float> %res91}92define <8 x float> @test_8xfloat_shuff_mask3(<8 x float> %vec1, <8 x float> %vec2) {93; CHECK-LABEL: test_8xfloat_shuff_mask3:94; CHECK: # %bb.0:95; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]96; CHECK-NEXT: retq97 %res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>98 ret <8 x float> %res99}100define <8 x float> @test_8xfloat_masked_shuff_mask3(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %vec3, <8 x float> %mask) {101; CHECK-LABEL: test_8xfloat_masked_shuff_mask3:102; CHECK: # %bb.0:103; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4104; CHECK-NEXT: vcmpeqps %ymm4, %ymm3, %k1105; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[0,1,2,3]106; CHECK-NEXT: vmovaps %ymm2, %ymm0107; CHECK-NEXT: retq108 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>109 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer110 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3111 ret <8 x float> %res112}113 114define <8 x float> @test_8xfloat_zero_masked_shuff_mask3(<8 x float> %vec1, <8 x float> %vec2, <8 x float> %mask) {115; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mask3:116; CHECK: # %bb.0:117; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3118; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k1119; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[0,1,2,3]120; CHECK-NEXT: retq121 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>122 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer123 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer124 ret <8 x float> %res125}126define <8 x float> @test_8xfloat_shuff_mem_mask0(<8 x float> %vec1, ptr %vec2p) {127; CHECK-LABEL: test_8xfloat_shuff_mem_mask0:128; CHECK: # %bb.0:129; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]130; CHECK-NEXT: retq131 %vec2 = load <8 x float>, ptr %vec2p132 %res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>133 ret <8 x float> %res134}135define <8 x float> @test_8xfloat_masked_shuff_mem_mask0(<8 x float> %vec1, ptr %vec2p, <8 x float> %vec3, <8 x float> %mask) {136; CHECK-LABEL: test_8xfloat_masked_shuff_mem_mask0:137; CHECK: # %bb.0:138; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3139; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k1140; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[4,5,6,7]141; CHECK-NEXT: vmovaps %ymm1, %ymm0142; CHECK-NEXT: retq143 %vec2 = load <8 x float>, ptr %vec2p144 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>145 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer146 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3147 ret <8 x float> %res148}149 150define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask0(<8 x float> %vec1, ptr %vec2p, <8 x float> %mask) {151; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mem_mask0:152; CHECK: # %bb.0:153; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2154; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1155; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[4,5,6,7]156; CHECK-NEXT: retq157 %vec2 = load <8 x float>, ptr %vec2p158 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>159 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer160 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer161 ret <8 x float> %res162}163 164define <8 x float> @test_8xfloat_masked_shuff_mem_mask1(<8 x float> %vec1, ptr %vec2p, <8 x float> %vec3, <8 x float> %mask) {165; CHECK-LABEL: test_8xfloat_masked_shuff_mem_mask1:166; CHECK: # %bb.0:167; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3168; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k1169; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[4,5,6,7]170; CHECK-NEXT: vmovaps %ymm1, %ymm0171; CHECK-NEXT: retq172 %vec2 = load <8 x float>, ptr %vec2p173 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>174 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer175 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3176 ret <8 x float> %res177}178 179define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask1(<8 x float> %vec1, ptr %vec2p, <8 x float> %mask) {180; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mem_mask1:181; CHECK: # %bb.0:182; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2183; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1184; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[4,5,6,7]185; CHECK-NEXT: retq186 %vec2 = load <8 x float>, ptr %vec2p187 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>188 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer189 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer190 ret <8 x float> %res191}192 193define <8 x float> @test_8xfloat_masked_shuff_mem_mask2(<8 x float> %vec1, ptr %vec2p, <8 x float> %vec3, <8 x float> %mask) {194; CHECK-LABEL: test_8xfloat_masked_shuff_mem_mask2:195; CHECK: # %bb.0:196; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3197; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k1198; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[0,1,2,3]199; CHECK-NEXT: vmovaps %ymm1, %ymm0200; CHECK-NEXT: retq201 %vec2 = load <8 x float>, ptr %vec2p202 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>203 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer204 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3205 ret <8 x float> %res206}207 208define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask2(<8 x float> %vec1, ptr %vec2p, <8 x float> %mask) {209; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mem_mask2:210; CHECK: # %bb.0:211; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2212; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1213; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[0,1,2,3]214; CHECK-NEXT: retq215 %vec2 = load <8 x float>, ptr %vec2p216 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>217 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer218 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer219 ret <8 x float> %res220}221 222define <8 x float> @test_8xfloat_shuff_mem_mask3(<8 x float> %vec1, ptr %vec2p) {223; CHECK-LABEL: test_8xfloat_shuff_mem_mask3:224; CHECK: # %bb.0:225; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1]226; CHECK-NEXT: retq227 %vec2 = load <8 x float>, ptr %vec2p228 %res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>229 ret <8 x float> %res230}231define <8 x float> @test_8xfloat_masked_shuff_mem_mask3(<8 x float> %vec1, ptr %vec2p, <8 x float> %vec3, <8 x float> %mask) {232; CHECK-LABEL: test_8xfloat_masked_shuff_mem_mask3:233; CHECK: # %bb.0:234; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3235; CHECK-NEXT: vcmpeqps %ymm3, %ymm2, %k1236; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[0,1,2,3]237; CHECK-NEXT: vmovaps %ymm1, %ymm0238; CHECK-NEXT: retq239 %vec2 = load <8 x float>, ptr %vec2p240 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>241 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer242 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> %vec3243 ret <8 x float> %res244}245 246define <8 x float> @test_8xfloat_zero_masked_shuff_mem_mask3(<8 x float> %vec1, ptr %vec2p, <8 x float> %mask) {247; CHECK-LABEL: test_8xfloat_zero_masked_shuff_mem_mask3:248; CHECK: # %bb.0:249; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2250; CHECK-NEXT: vcmpeqps %ymm2, %ymm1, %k1251; CHECK-NEXT: vshuff32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[0,1,2,3]252; CHECK-NEXT: retq253 %vec2 = load <8 x float>, ptr %vec2p254 %shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>255 %cmp = fcmp oeq <8 x float> %mask, zeroinitializer256 %res = select <8 x i1> %cmp, <8 x float> %shuf, <8 x float> zeroinitializer257 ret <8 x float> %res258}259 260define <16 x float> @test_16xfloat_shuff_mask0(<16 x float> %vec1, <16 x float> %vec2) {261; CHECK-LABEL: test_16xfloat_shuff_mask0:262; CHECK: # %bb.0:263; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,0,1],zmm1[2,3,6,7]264; CHECK-NEXT: retq265 %res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>266 ret <16 x float> %res267}268define <16 x float> @test_16xfloat_masked_shuff_mask0(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %vec3, <16 x float> %mask) {269; CHECK-LABEL: test_16xfloat_masked_shuff_mask0:270; CHECK: # %bb.0:271; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4272; CHECK-NEXT: vcmpeqps %zmm4, %zmm3, %k1273; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 {%k1} = zmm0[12,13,14,15,0,1,2,3],zmm1[4,5,6,7,12,13,14,15]274; CHECK-NEXT: vmovaps %zmm2, %zmm0275; CHECK-NEXT: retq276 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>277 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer278 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3279 ret <16 x float> %res280}281 282define <16 x float> @test_16xfloat_zero_masked_shuff_mask0(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %mask) {283; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mask0:284; CHECK: # %bb.0:285; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3286; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1287; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[12,13,14,15,0,1,2,3],zmm1[4,5,6,7,12,13,14,15]288; CHECK-NEXT: retq289 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>290 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer291 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer292 ret <16 x float> %res293}294define <16 x float> @test_16xfloat_masked_shuff_mask1(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %vec3, <16 x float> %mask) {295; CHECK-LABEL: test_16xfloat_masked_shuff_mask1:296; CHECK: # %bb.0:297; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4298; CHECK-NEXT: vcmpeqps %zmm4, %zmm3, %k1299; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 {%k1} = zmm0[0,1,2,3,8,9,10,11],zmm1[0,1,2,3,12,13,14,15]300; CHECK-NEXT: vmovaps %zmm2, %zmm0301; CHECK-NEXT: retq302 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 28, i32 29, i32 30, i32 31>303 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer304 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3305 ret <16 x float> %res306}307 308define <16 x float> @test_16xfloat_zero_masked_shuff_mask1(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %mask) {309; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mask1:310; CHECK: # %bb.0:311; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3312; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1313; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[0,1,2,3,8,9,10,11],zmm1[0,1,2,3,12,13,14,15]314; CHECK-NEXT: retq315 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 28, i32 29, i32 30, i32 31>316 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer317 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer318 ret <16 x float> %res319}320define <16 x float> @test_16xfloat_masked_shuff_mask2(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %vec3, <16 x float> %mask) {321; CHECK-LABEL: test_16xfloat_masked_shuff_mask2:322; CHECK: # %bb.0:323; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4324; CHECK-NEXT: vcmpeqps %zmm4, %zmm3, %k1325; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 {%k1} = zmm0[12,13,14,15,4,5,6,7],zmm1[0,1,2,3,4,5,6,7]326; CHECK-NEXT: vmovaps %zmm2, %zmm0327; CHECK-NEXT: retq328 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>329 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer330 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3331 ret <16 x float> %res332}333 334define <16 x float> @test_16xfloat_zero_masked_shuff_mask2(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %mask) {335; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mask2:336; CHECK: # %bb.0:337; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3338; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1339; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[12,13,14,15,4,5,6,7],zmm1[0,1,2,3,4,5,6,7]340; CHECK-NEXT: retq341 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>342 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer343 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer344 ret <16 x float> %res345}346define <16 x float> @test_16xfloat_shuff_mask3(<16 x float> %vec1, <16 x float> %vec2) {347; CHECK-LABEL: test_16xfloat_shuff_mask3:348; CHECK: # %bb.0:349; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,6,7],zmm1[0,1,4,5]350; CHECK-NEXT: retq351 %res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>352 ret <16 x float> %res353}354define <16 x float> @test_16xfloat_masked_shuff_mask3(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %vec3, <16 x float> %mask) {355; CHECK-LABEL: test_16xfloat_masked_shuff_mask3:356; CHECK: # %bb.0:357; CHECK-NEXT: vxorps %xmm4, %xmm4, %xmm4358; CHECK-NEXT: vcmpeqps %zmm4, %zmm3, %k1359; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm2 {%k1} = zmm0[8,9,10,11,12,13,14,15],zmm1[0,1,2,3,8,9,10,11]360; CHECK-NEXT: vmovaps %zmm2, %zmm0361; CHECK-NEXT: retq362 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>363 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer364 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3365 ret <16 x float> %res366}367 368define <16 x float> @test_16xfloat_zero_masked_shuff_mask3(<16 x float> %vec1, <16 x float> %vec2, <16 x float> %mask) {369; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mask3:370; CHECK: # %bb.0:371; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3372; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1373; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[8,9,10,11,12,13,14,15],zmm1[0,1,2,3,8,9,10,11]374; CHECK-NEXT: retq375 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>376 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer377 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer378 ret <16 x float> %res379}380define <16 x float> @test_16xfloat_shuff_mem_mask0(<16 x float> %vec1, ptr %vec2p) {381; CHECK-LABEL: test_16xfloat_shuff_mem_mask0:382; CHECK: # %bb.0:383; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,4,5],mem[4,5,2,3]384; CHECK-NEXT: retq385 %vec2 = load <16 x float>, ptr %vec2p386 %res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>387 ret <16 x float> %res388}389define <16 x float> @test_16xfloat_masked_shuff_mem_mask0(<16 x float> %vec1, ptr %vec2p, <16 x float> %vec3, <16 x float> %mask) {390; CHECK-LABEL: test_16xfloat_masked_shuff_mem_mask0:391; CHECK: # %bb.0:392; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3393; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1394; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 {%k1} = zmm0[12,13,14,15,8,9,10,11],mem[8,9,10,11,4,5,6,7]395; CHECK-NEXT: vmovaps %zmm1, %zmm0396; CHECK-NEXT: retq397 %vec2 = load <16 x float>, ptr %vec2p398 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>399 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer400 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3401 ret <16 x float> %res402}403 404define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask0(<16 x float> %vec1, ptr %vec2p, <16 x float> %mask) {405; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mem_mask0:406; CHECK: # %bb.0:407; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2408; CHECK-NEXT: vcmpeqps %zmm2, %zmm1, %k1409; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[12,13,14,15,8,9,10,11],mem[8,9,10,11,4,5,6,7]410; CHECK-NEXT: retq411 %vec2 = load <16 x float>, ptr %vec2p412 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>413 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer414 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer415 ret <16 x float> %res416}417 418define <16 x float> @test_16xfloat_masked_shuff_mem_mask1(<16 x float> %vec1, ptr %vec2p, <16 x float> %vec3, <16 x float> %mask) {419; CHECK-LABEL: test_16xfloat_masked_shuff_mem_mask1:420; CHECK: # %bb.0:421; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3422; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1423; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 {%k1} = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,4,5,6,7]424; CHECK-NEXT: vmovaps %zmm1, %zmm0425; CHECK-NEXT: retq426 %vec2 = load <16 x float>, ptr %vec2p427 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>428 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer429 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3430 ret <16 x float> %res431}432 433define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask1(<16 x float> %vec1, ptr %vec2p, <16 x float> %mask) {434; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mem_mask1:435; CHECK: # %bb.0:436; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2437; CHECK-NEXT: vcmpeqps %zmm2, %zmm1, %k1438; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,4,5,6,7]439; CHECK-NEXT: retq440 %vec2 = load <16 x float>, ptr %vec2p441 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>442 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer443 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer444 ret <16 x float> %res445}446 447define <16 x float> @test_16xfloat_masked_shuff_mem_mask2(<16 x float> %vec1, ptr %vec2p, <16 x float> %vec3, <16 x float> %mask) {448; CHECK-LABEL: test_16xfloat_masked_shuff_mem_mask2:449; CHECK: # %bb.0:450; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3451; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1452; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 {%k1} = zmm0[0,1,2,3,0,1,2,3],mem[8,9,10,11,8,9,10,11]453; CHECK-NEXT: vmovaps %zmm1, %zmm0454; CHECK-NEXT: retq455 %vec2 = load <16 x float>, ptr %vec2p456 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 24, i32 25, i32 26, i32 27>457 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer458 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3459 ret <16 x float> %res460}461 462define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask2(<16 x float> %vec1, ptr %vec2p, <16 x float> %mask) {463; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mem_mask2:464; CHECK: # %bb.0:465; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2466; CHECK-NEXT: vcmpeqps %zmm2, %zmm1, %k1467; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[0,1,2,3,0,1,2,3],mem[8,9,10,11,8,9,10,11]468; CHECK-NEXT: retq469 %vec2 = load <16 x float>, ptr %vec2p470 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 24, i32 25, i32 26, i32 27>471 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer472 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer473 ret <16 x float> %res474}475 476define <16 x float> @test_16xfloat_shuff_mem_mask3(<16 x float> %vec1, ptr %vec2p) {477; CHECK-LABEL: test_16xfloat_shuff_mem_mask3:478; CHECK: # %bb.0:479; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[6,7,6,7]480; CHECK-NEXT: retq481 %vec2 = load <16 x float>, ptr %vec2p482 %res = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>483 ret <16 x float> %res484}485define <16 x float> @test_16xfloat_masked_shuff_mem_mask3(<16 x float> %vec1, ptr %vec2p, <16 x float> %vec3, <16 x float> %mask) {486; CHECK-LABEL: test_16xfloat_masked_shuff_mem_mask3:487; CHECK: # %bb.0:488; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3489; CHECK-NEXT: vcmpeqps %zmm3, %zmm2, %k1490; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm1 {%k1} = zmm0[4,5,6,7,0,1,2,3],mem[12,13,14,15,12,13,14,15]491; CHECK-NEXT: vmovaps %zmm1, %zmm0492; CHECK-NEXT: retq493 %vec2 = load <16 x float>, ptr %vec2p494 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>495 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer496 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> %vec3497 ret <16 x float> %res498}499 500define <16 x float> @test_16xfloat_zero_masked_shuff_mem_mask3(<16 x float> %vec1, ptr %vec2p, <16 x float> %mask) {501; CHECK-LABEL: test_16xfloat_zero_masked_shuff_mem_mask3:502; CHECK: # %bb.0:503; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2504; CHECK-NEXT: vcmpeqps %zmm2, %zmm1, %k1505; CHECK-NEXT: vshuff32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,0,1,2,3],mem[12,13,14,15,12,13,14,15]506; CHECK-NEXT: retq507 %vec2 = load <16 x float>, ptr %vec2p508 %shuf = shufflevector <16 x float> %vec1, <16 x float> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>509 %cmp = fcmp oeq <16 x float> %mask, zeroinitializer510 %res = select <16 x i1> %cmp, <16 x float> %shuf, <16 x float> zeroinitializer511 ret <16 x float> %res512}513 514define <4 x double> @test_4xdouble_shuff_mask0(<4 x double> %vec1, <4 x double> %vec2) {515; CHECK-LABEL: test_4xdouble_shuff_mask0:516; CHECK: # %bb.0:517; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]518; CHECK-NEXT: retq519 %res = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>520 ret <4 x double> %res521}522define <4 x double> @test_4xdouble_masked_shuff_mask0(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %vec3, <4 x double> %mask) {523; CHECK-LABEL: test_4xdouble_masked_shuff_mask0:524; CHECK: # %bb.0:525; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4526; CHECK-NEXT: vcmpeqpd %ymm4, %ymm3, %k1527; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[0,1]528; CHECK-NEXT: vmovapd %ymm2, %ymm0529; CHECK-NEXT: retq530 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>531 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer532 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3533 ret <4 x double> %res534}535 536define <4 x double> @test_4xdouble_zero_masked_shuff_mask0(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %mask) {537; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mask0:538; CHECK: # %bb.0:539; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3540; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1541; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[0,1]542; CHECK-NEXT: retq543 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>544 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer545 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer546 ret <4 x double> %res547}548define <4 x double> @test_4xdouble_masked_shuff_mask1(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %vec3, <4 x double> %mask) {549; CHECK-LABEL: test_4xdouble_masked_shuff_mask1:550; CHECK: # %bb.0:551; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4552; CHECK-NEXT: vcmpeqpd %ymm4, %ymm3, %k1553; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[0,1]554; CHECK-NEXT: vmovapd %ymm2, %ymm0555; CHECK-NEXT: retq556 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>557 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer558 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3559 ret <4 x double> %res560}561 562define <4 x double> @test_4xdouble_zero_masked_shuff_mask1(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %mask) {563; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mask1:564; CHECK: # %bb.0:565; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3566; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1567; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[0,1]568; CHECK-NEXT: retq569 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>570 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer571 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer572 ret <4 x double> %res573}574define <4 x double> @test_4xdouble_masked_shuff_mask2(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %vec3, <4 x double> %mask) {575; CHECK-LABEL: test_4xdouble_masked_shuff_mask2:576; CHECK: # %bb.0:577; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4578; CHECK-NEXT: vcmpeqpd %ymm4, %ymm3, %k1579; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[2,3]580; CHECK-NEXT: vmovapd %ymm2, %ymm0581; CHECK-NEXT: retq582 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>583 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer584 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3585 ret <4 x double> %res586}587 588define <4 x double> @test_4xdouble_zero_masked_shuff_mask2(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %mask) {589; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mask2:590; CHECK: # %bb.0:591; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3592; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1593; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[2,3]594; CHECK-NEXT: retq595 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>596 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer597 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer598 ret <4 x double> %res599}600define <4 x double> @test_4xdouble_shuff_mask3(<4 x double> %vec1, <4 x double> %vec2) {601; CHECK-LABEL: test_4xdouble_shuff_mask3:602; CHECK: # %bb.0:603; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]604; CHECK-NEXT: retq605 %res = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>606 ret <4 x double> %res607}608define <4 x double> @test_4xdouble_masked_shuff_mask3(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %vec3, <4 x double> %mask) {609; CHECK-LABEL: test_4xdouble_masked_shuff_mask3:610; CHECK: # %bb.0:611; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4612; CHECK-NEXT: vcmpeqpd %ymm4, %ymm3, %k1613; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[2,3]614; CHECK-NEXT: vmovapd %ymm2, %ymm0615; CHECK-NEXT: retq616 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>617 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer618 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3619 ret <4 x double> %res620}621 622define <4 x double> @test_4xdouble_zero_masked_shuff_mask3(<4 x double> %vec1, <4 x double> %vec2, <4 x double> %mask) {623; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mask3:624; CHECK: # %bb.0:625; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3626; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1627; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[2,3]628; CHECK-NEXT: retq629 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>630 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer631 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer632 ret <4 x double> %res633}634define <4 x double> @test_4xdouble_shuff_mem_mask0(<4 x double> %vec1, ptr %vec2p) {635; CHECK-LABEL: test_4xdouble_shuff_mem_mask0:636; CHECK: # %bb.0:637; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]638; CHECK-NEXT: retq639 %vec2 = load <4 x double>, ptr %vec2p640 %res = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>641 ret <4 x double> %res642}643define <4 x double> @test_4xdouble_masked_shuff_mem_mask0(<4 x double> %vec1, ptr %vec2p, <4 x double> %vec3, <4 x double> %mask) {644; CHECK-LABEL: test_4xdouble_masked_shuff_mem_mask0:645; CHECK: # %bb.0:646; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3647; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1648; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[2,3]649; CHECK-NEXT: vmovapd %ymm1, %ymm0650; CHECK-NEXT: retq651 %vec2 = load <4 x double>, ptr %vec2p652 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>653 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer654 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3655 ret <4 x double> %res656}657 658define <4 x double> @test_4xdouble_zero_masked_shuff_mem_mask0(<4 x double> %vec1, ptr %vec2p, <4 x double> %mask) {659; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mem_mask0:660; CHECK: # %bb.0:661; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2662; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1663; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[2,3]664; CHECK-NEXT: retq665 %vec2 = load <4 x double>, ptr %vec2p666 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>667 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer668 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer669 ret <4 x double> %res670}671 672define <4 x double> @test_4xdouble_masked_shuff_mem_mask1(<4 x double> %vec1, ptr %vec2p, <4 x double> %vec3, <4 x double> %mask) {673; CHECK-LABEL: test_4xdouble_masked_shuff_mem_mask1:674; CHECK: # %bb.0:675; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3676; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1677; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[0,1]678; CHECK-NEXT: vmovapd %ymm1, %ymm0679; CHECK-NEXT: retq680 %vec2 = load <4 x double>, ptr %vec2p681 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>682 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer683 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3684 ret <4 x double> %res685}686 687define <4 x double> @test_4xdouble_zero_masked_shuff_mem_mask1(<4 x double> %vec1, ptr %vec2p, <4 x double> %mask) {688; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mem_mask1:689; CHECK: # %bb.0:690; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2691; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1692; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[0,1]693; CHECK-NEXT: retq694 %vec2 = load <4 x double>, ptr %vec2p695 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>696 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer697 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer698 ret <4 x double> %res699}700 701define <4 x double> @test_4xdouble_masked_shuff_mem_mask2(<4 x double> %vec1, ptr %vec2p, <4 x double> %vec3, <4 x double> %mask) {702; CHECK-LABEL: test_4xdouble_masked_shuff_mem_mask2:703; CHECK: # %bb.0:704; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3705; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1706; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[0,1]707; CHECK-NEXT: vmovapd %ymm1, %ymm0708; CHECK-NEXT: retq709 %vec2 = load <4 x double>, ptr %vec2p710 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>711 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer712 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3713 ret <4 x double> %res714}715 716define <4 x double> @test_4xdouble_zero_masked_shuff_mem_mask2(<4 x double> %vec1, ptr %vec2p, <4 x double> %mask) {717; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mem_mask2:718; CHECK: # %bb.0:719; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2720; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1721; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[0,1]722; CHECK-NEXT: retq723 %vec2 = load <4 x double>, ptr %vec2p724 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>725 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer726 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer727 ret <4 x double> %res728}729 730define <4 x double> @test_4xdouble_shuff_mem_mask3(<4 x double> %vec1, ptr %vec2p) {731; CHECK-LABEL: test_4xdouble_shuff_mem_mask3:732; CHECK: # %bb.0:733; CHECK-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]734; CHECK-NEXT: retq735 %vec2 = load <4 x double>, ptr %vec2p736 %res = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>737 ret <4 x double> %res738}739define <4 x double> @test_4xdouble_masked_shuff_mem_mask3(<4 x double> %vec1, ptr %vec2p, <4 x double> %vec3, <4 x double> %mask) {740; CHECK-LABEL: test_4xdouble_masked_shuff_mem_mask3:741; CHECK: # %bb.0:742; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3743; CHECK-NEXT: vcmpeqpd %ymm3, %ymm2, %k1744; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[2,3]745; CHECK-NEXT: vmovapd %ymm1, %ymm0746; CHECK-NEXT: retq747 %vec2 = load <4 x double>, ptr %vec2p748 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>749 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer750 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec3751 ret <4 x double> %res752}753 754define <4 x double> @test_4xdouble_zero_masked_shuff_mem_mask3(<4 x double> %vec1, ptr %vec2p, <4 x double> %mask) {755; CHECK-LABEL: test_4xdouble_zero_masked_shuff_mem_mask3:756; CHECK: # %bb.0:757; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2758; CHECK-NEXT: vcmpeqpd %ymm2, %ymm1, %k1759; CHECK-NEXT: vshuff64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[2,3]760; CHECK-NEXT: retq761 %vec2 = load <4 x double>, ptr %vec2p762 %shuf = shufflevector <4 x double> %vec1, <4 x double> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>763 %cmp = fcmp oeq <4 x double> %mask, zeroinitializer764 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> zeroinitializer765 ret <4 x double> %res766}767 768define <8 x double> @test_8xdouble_shuff_mask0(<8 x double> %vec1, <8 x double> %vec2) {769; CHECK-LABEL: test_8xdouble_shuff_mask0:770; CHECK: # %bb.0:771; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,2,3],zmm1[6,7,0,1]772; CHECK-NEXT: retq773 %res = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 2, i32 3, i32 14, i32 15, i32 8, i32 9>774 ret <8 x double> %res775}776define <8 x double> @test_8xdouble_masked_shuff_mask0(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %vec3, <8 x double> %mask) {777; CHECK-LABEL: test_8xdouble_masked_shuff_mask0:778; CHECK: # %bb.0:779; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4780; CHECK-NEXT: vcmpeqpd %zmm4, %zmm3, %k1781; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 {%k1} = zmm0[6,7,2,3],zmm1[6,7,0,1]782; CHECK-NEXT: vmovapd %zmm2, %zmm0783; CHECK-NEXT: retq784 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 2, i32 3, i32 14, i32 15, i32 8, i32 9>785 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer786 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3787 ret <8 x double> %res788}789 790define <8 x double> @test_8xdouble_zero_masked_shuff_mask0(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %mask) {791; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mask0:792; CHECK: # %bb.0:793; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3794; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1795; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[6,7,2,3],zmm1[6,7,0,1]796; CHECK-NEXT: retq797 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 2, i32 3, i32 14, i32 15, i32 8, i32 9>798 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer799 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer800 ret <8 x double> %res801}802define <8 x double> @test_8xdouble_masked_shuff_mask1(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %vec3, <8 x double> %mask) {803; CHECK-LABEL: test_8xdouble_masked_shuff_mask1:804; CHECK: # %bb.0:805; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4806; CHECK-NEXT: vcmpeqpd %zmm4, %zmm3, %k1807; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 {%k1} = zmm0[0,1,4,5],zmm1[0,1,4,5]808; CHECK-NEXT: vmovapd %zmm2, %zmm0809; CHECK-NEXT: retq810 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>811 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer812 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3813 ret <8 x double> %res814}815 816define <8 x double> @test_8xdouble_zero_masked_shuff_mask1(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %mask) {817; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mask1:818; CHECK: # %bb.0:819; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3820; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1821; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[0,1,4,5],zmm1[0,1,4,5]822; CHECK-NEXT: retq823 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>824 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer825 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer826 ret <8 x double> %res827}828define <8 x double> @test_8xdouble_masked_shuff_mask2(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %vec3, <8 x double> %mask) {829; CHECK-LABEL: test_8xdouble_masked_shuff_mask2:830; CHECK: # %bb.0:831; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4832; CHECK-NEXT: vcmpeqpd %zmm4, %zmm3, %k1833; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 {%k1} = zmm0[6,7,4,5],zmm1[4,5,0,1]834; CHECK-NEXT: vmovapd %zmm2, %zmm0835; CHECK-NEXT: retq836 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 12, i32 13, i32 8, i32 9>837 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer838 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3839 ret <8 x double> %res840}841 842define <8 x double> @test_8xdouble_zero_masked_shuff_mask2(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %mask) {843; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mask2:844; CHECK: # %bb.0:845; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3846; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1847; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[6,7,4,5],zmm1[4,5,0,1]848; CHECK-NEXT: retq849 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 12, i32 13, i32 8, i32 9>850 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer851 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer852 ret <8 x double> %res853}854define <8 x double> @test_8xdouble_shuff_mask3(<8 x double> %vec1, <8 x double> %vec2) {855; CHECK-LABEL: test_8xdouble_shuff_mask3:856; CHECK: # %bb.0:857; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[4,5,4,5],zmm1[4,5,2,3]858; CHECK-NEXT: retq859 %res = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 10, i32 11>860 ret <8 x double> %res861}862define <8 x double> @test_8xdouble_masked_shuff_mask3(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %vec3, <8 x double> %mask) {863; CHECK-LABEL: test_8xdouble_masked_shuff_mask3:864; CHECK: # %bb.0:865; CHECK-NEXT: vxorpd %xmm4, %xmm4, %xmm4866; CHECK-NEXT: vcmpeqpd %zmm4, %zmm3, %k1867; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm2 {%k1} = zmm0[4,5,4,5],zmm1[4,5,2,3]868; CHECK-NEXT: vmovapd %zmm2, %zmm0869; CHECK-NEXT: retq870 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 10, i32 11>871 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer872 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3873 ret <8 x double> %res874}875 876define <8 x double> @test_8xdouble_zero_masked_shuff_mask3(<8 x double> %vec1, <8 x double> %vec2, <8 x double> %mask) {877; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mask3:878; CHECK: # %bb.0:879; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3880; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1881; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,4,5],zmm1[4,5,2,3]882; CHECK-NEXT: retq883 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 10, i32 11>884 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer885 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer886 ret <8 x double> %res887}888define <8 x double> @test_8xdouble_shuff_mem_mask0(<8 x double> %vec1, ptr %vec2p) {889; CHECK-LABEL: test_8xdouble_shuff_mem_mask0:890; CHECK: # %bb.0:891; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[6,7,0,1],mem[0,1,0,1]892; CHECK-NEXT: retq893 %vec2 = load <8 x double>, ptr %vec2p894 %res = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 8, i32 9, i32 8, i32 9>895 ret <8 x double> %res896}897define <8 x double> @test_8xdouble_masked_shuff_mem_mask0(<8 x double> %vec1, ptr %vec2p, <8 x double> %vec3, <8 x double> %mask) {898; CHECK-LABEL: test_8xdouble_masked_shuff_mem_mask0:899; CHECK: # %bb.0:900; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3901; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1902; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 {%k1} = zmm0[6,7,0,1],mem[0,1,0,1]903; CHECK-NEXT: vmovapd %zmm1, %zmm0904; CHECK-NEXT: retq905 %vec2 = load <8 x double>, ptr %vec2p906 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 8, i32 9, i32 8, i32 9>907 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer908 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3909 ret <8 x double> %res910}911 912define <8 x double> @test_8xdouble_zero_masked_shuff_mem_mask0(<8 x double> %vec1, ptr %vec2p, <8 x double> %mask) {913; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mem_mask0:914; CHECK: # %bb.0:915; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2916; CHECK-NEXT: vcmpeqpd %zmm2, %zmm1, %k1917; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[6,7,0,1],mem[0,1,0,1]918; CHECK-NEXT: retq919 %vec2 = load <8 x double>, ptr %vec2p920 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 8, i32 9, i32 8, i32 9>921 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer922 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer923 ret <8 x double> %res924}925 926define <8 x double> @test_8xdouble_masked_shuff_mem_mask1(<8 x double> %vec1, ptr %vec2p, <8 x double> %vec3, <8 x double> %mask) {927; CHECK-LABEL: test_8xdouble_masked_shuff_mem_mask1:928; CHECK: # %bb.0:929; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3930; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1931; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 {%k1} = zmm0[6,7,6,7],mem[0,1,2,3]932; CHECK-NEXT: vmovapd %zmm1, %zmm0933; CHECK-NEXT: retq934 %vec2 = load <8 x double>, ptr %vec2p935 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>936 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer937 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3938 ret <8 x double> %res939}940 941define <8 x double> @test_8xdouble_zero_masked_shuff_mem_mask1(<8 x double> %vec1, ptr %vec2p, <8 x double> %mask) {942; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mem_mask1:943; CHECK: # %bb.0:944; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2945; CHECK-NEXT: vcmpeqpd %zmm2, %zmm1, %k1946; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[6,7,6,7],mem[0,1,2,3]947; CHECK-NEXT: retq948 %vec2 = load <8 x double>, ptr %vec2p949 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 6, i32 7, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>950 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer951 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer952 ret <8 x double> %res953}954 955define <8 x double> @test_8xdouble_masked_shuff_mem_mask2(<8 x double> %vec1, ptr %vec2p, <8 x double> %vec3, <8 x double> %mask) {956; CHECK-LABEL: test_8xdouble_masked_shuff_mem_mask2:957; CHECK: # %bb.0:958; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3959; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1960; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 {%k1} = zmm0[0,1,2,3],mem[0,1,4,5]961; CHECK-NEXT: vmovapd %zmm1, %zmm0962; CHECK-NEXT: retq963 %vec2 = load <8 x double>, ptr %vec2p964 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 12, i32 13>965 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer966 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec3967 ret <8 x double> %res968}969 970define <8 x double> @test_8xdouble_zero_masked_shuff_mem_mask2(<8 x double> %vec1, ptr %vec2p, <8 x double> %mask) {971; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mem_mask2:972; CHECK: # %bb.0:973; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm2974; CHECK-NEXT: vcmpeqpd %zmm2, %zmm1, %k1975; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[0,1,2,3],mem[0,1,4,5]976; CHECK-NEXT: retq977 %vec2 = load <8 x double>, ptr %vec2p978 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 12, i32 13>979 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer980 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer981 ret <8 x double> %res982}983 984define <8 x double> @test_8xdouble_shuff_mem_mask3(<8 x double> %vec1, ptr %vec2p) {985; CHECK-LABEL: test_8xdouble_shuff_mem_mask3:986; CHECK: # %bb.0:987; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[4,5,0,1]988; CHECK-NEXT: retq989 %vec2 = load <8 x double>, ptr %vec2p990 %res = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 12, i32 13, i32 8, i32 9>991 ret <8 x double> %res992}993define <8 x double> @test_8xdouble_masked_shuff_mem_mask3(<8 x double> %vec1, ptr %vec2p, <8 x double> %vec3, <8 x double> %mask) {994; CHECK-LABEL: test_8xdouble_masked_shuff_mem_mask3:995; CHECK: # %bb.0:996; CHECK-NEXT: vxorpd %xmm3, %xmm3, %xmm3997; CHECK-NEXT: vcmpeqpd %zmm3, %zmm2, %k1998; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm1 {%k1} = zmm0[2,3,0,1],mem[4,5,0,1]999; CHECK-NEXT: vmovapd %zmm1, %zmm01000; CHECK-NEXT: retq1001 %vec2 = load <8 x double>, ptr %vec2p1002 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 12, i32 13, i32 8, i32 9>1003 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer1004 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> %vec31005 ret <8 x double> %res1006}1007 1008define <8 x double> @test_8xdouble_zero_masked_shuff_mem_mask3(<8 x double> %vec1, ptr %vec2p, <8 x double> %mask) {1009; CHECK-LABEL: test_8xdouble_zero_masked_shuff_mem_mask3:1010; CHECK: # %bb.0:1011; CHECK-NEXT: vxorpd %xmm2, %xmm2, %xmm21012; CHECK-NEXT: vcmpeqpd %zmm2, %zmm1, %k11013; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[2,3,0,1],mem[4,5,0,1]1014; CHECK-NEXT: retq1015 %vec2 = load <8 x double>, ptr %vec2p1016 %shuf = shufflevector <8 x double> %vec1, <8 x double> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 12, i32 13, i32 8, i32 9>1017 %cmp = fcmp oeq <8 x double> %mask, zeroinitializer1018 %res = select <8 x i1> %cmp, <8 x double> %shuf, <8 x double> zeroinitializer1019 ret <8 x double> %res1020}1021 1022define <8 x i32> @test_8xi32_shuff_mask0(<8 x i32> %vec1, <8 x i32> %vec2) {1023; CHECK-LABEL: test_8xi32_shuff_mask0:1024; CHECK: # %bb.0:1025; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]1026; CHECK-NEXT: retq1027 %res = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1028 ret <8 x i32> %res1029}1030define <8 x i32> @test_8xi32_masked_shuff_mask0(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %vec3, <8 x i32> %mask) {1031; CHECK-LABEL: test_8xi32_masked_shuff_mask0:1032; CHECK: # %bb.0:1033; CHECK-NEXT: vptestnmd %ymm3, %ymm3, %k11034; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[4,5,6,7]1035; CHECK-NEXT: vmovdqa %ymm2, %ymm01036; CHECK-NEXT: retq1037 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1038 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1039 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31040 ret <8 x i32> %res1041}1042 1043define <8 x i32> @test_8xi32_zero_masked_shuff_mask0(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %mask) {1044; CHECK-LABEL: test_8xi32_zero_masked_shuff_mask0:1045; CHECK: # %bb.0:1046; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11047; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[4,5,6,7]1048; CHECK-NEXT: retq1049 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1050 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1051 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1052 ret <8 x i32> %res1053}1054define <8 x i32> @test_8xi32_masked_shuff_mask1(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %vec3, <8 x i32> %mask) {1055; CHECK-LABEL: test_8xi32_masked_shuff_mask1:1056; CHECK: # %bb.0:1057; CHECK-NEXT: vptestnmd %ymm3, %ymm3, %k11058; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[0,1,2,3]1059; CHECK-NEXT: vmovdqa %ymm2, %ymm01060; CHECK-NEXT: retq1061 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1062 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1063 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31064 ret <8 x i32> %res1065}1066 1067define <8 x i32> @test_8xi32_zero_masked_shuff_mask1(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %mask) {1068; CHECK-LABEL: test_8xi32_zero_masked_shuff_mask1:1069; CHECK: # %bb.0:1070; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11071; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[0,1,2,3]1072; CHECK-NEXT: retq1073 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1074 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1075 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1076 ret <8 x i32> %res1077}1078define <8 x i32> @test_8xi32_masked_shuff_mask2(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %vec3, <8 x i32> %mask) {1079; CHECK-LABEL: test_8xi32_masked_shuff_mask2:1080; CHECK: # %bb.0:1081; CHECK-NEXT: vptestnmd %ymm3, %ymm3, %k11082; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[4,5,6,7]1083; CHECK-NEXT: vmovdqa %ymm2, %ymm01084; CHECK-NEXT: retq1085 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1086 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1087 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31088 ret <8 x i32> %res1089}1090 1091define <8 x i32> @test_8xi32_zero_masked_shuff_mask2(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %mask) {1092; CHECK-LABEL: test_8xi32_zero_masked_shuff_mask2:1093; CHECK: # %bb.0:1094; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11095; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[4,5,6,7]1096; CHECK-NEXT: retq1097 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1098 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1099 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1100 ret <8 x i32> %res1101}1102define <8 x i32> @test_8xi32_shuff_mask3(<8 x i32> %vec1, <8 x i32> %vec2) {1103; CHECK-LABEL: test_8xi32_shuff_mask3:1104; CHECK: # %bb.0:1105; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]1106; CHECK-NEXT: retq1107 %res = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1108 ret <8 x i32> %res1109}1110define <8 x i32> @test_8xi32_masked_shuff_mask3(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %vec3, <8 x i32> %mask) {1111; CHECK-LABEL: test_8xi32_masked_shuff_mask3:1112; CHECK: # %bb.0:1113; CHECK-NEXT: vptestnmd %ymm3, %ymm3, %k11114; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm2 {%k1} = ymm0[4,5,6,7],ymm1[0,1,2,3]1115; CHECK-NEXT: vmovdqa %ymm2, %ymm01116; CHECK-NEXT: retq1117 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1118 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1119 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31120 ret <8 x i32> %res1121}1122 1123define <8 x i32> @test_8xi32_zero_masked_shuff_mask3(<8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> %mask) {1124; CHECK-LABEL: test_8xi32_zero_masked_shuff_mask3:1125; CHECK: # %bb.0:1126; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11127; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],ymm1[0,1,2,3]1128; CHECK-NEXT: retq1129 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1130 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1131 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1132 ret <8 x i32> %res1133}1134define <8 x i32> @test_8xi32_shuff_mem_mask0(<8 x i32> %vec1, ptr %vec2p) {1135; CHECK-LABEL: test_8xi32_shuff_mem_mask0:1136; CHECK: # %bb.0:1137; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]1138; CHECK-NEXT: retq1139 %vec2 = load <8 x i32>, ptr %vec2p1140 %res = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1141 ret <8 x i32> %res1142}1143define <8 x i32> @test_8xi32_masked_shuff_mem_mask0(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %vec3, <8 x i32> %mask) {1144; CHECK-LABEL: test_8xi32_masked_shuff_mem_mask0:1145; CHECK: # %bb.0:1146; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11147; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[4,5,6,7]1148; CHECK-NEXT: vmovdqa %ymm1, %ymm01149; CHECK-NEXT: retq1150 %vec2 = load <8 x i32>, ptr %vec2p1151 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1152 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1153 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31154 ret <8 x i32> %res1155}1156 1157define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask0(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %mask) {1158; CHECK-LABEL: test_8xi32_zero_masked_shuff_mem_mask0:1159; CHECK: # %bb.0:1160; CHECK-NEXT: vptestnmd %ymm1, %ymm1, %k11161; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[4,5,6,7]1162; CHECK-NEXT: retq1163 %vec2 = load <8 x i32>, ptr %vec2p1164 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>1165 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1166 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1167 ret <8 x i32> %res1168}1169 1170define <8 x i32> @test_8xi32_masked_shuff_mem_mask1(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %vec3, <8 x i32> %mask) {1171; CHECK-LABEL: test_8xi32_masked_shuff_mem_mask1:1172; CHECK: # %bb.0:1173; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11174; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[0,1,2,3]1175; CHECK-NEXT: vmovdqa %ymm1, %ymm01176; CHECK-NEXT: retq1177 %vec2 = load <8 x i32>, ptr %vec2p1178 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1179 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1180 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31181 ret <8 x i32> %res1182}1183 1184define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask1(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %mask) {1185; CHECK-LABEL: test_8xi32_zero_masked_shuff_mem_mask1:1186; CHECK: # %bb.0:1187; CHECK-NEXT: vptestnmd %ymm1, %ymm1, %k11188; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[0,1,2,3]1189; CHECK-NEXT: retq1190 %vec2 = load <8 x i32>, ptr %vec2p1191 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1192 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1193 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1194 ret <8 x i32> %res1195}1196 1197define <8 x i32> @test_8xi32_masked_shuff_mem_mask2(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %vec3, <8 x i32> %mask) {1198; CHECK-LABEL: test_8xi32_masked_shuff_mem_mask2:1199; CHECK: # %bb.0:1200; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11201; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[0,1,2,3]1202; CHECK-NEXT: vmovdqa %ymm1, %ymm01203; CHECK-NEXT: retq1204 %vec2 = load <8 x i32>, ptr %vec2p1205 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1206 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1207 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31208 ret <8 x i32> %res1209}1210 1211define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask2(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %mask) {1212; CHECK-LABEL: test_8xi32_zero_masked_shuff_mem_mask2:1213; CHECK: # %bb.0:1214; CHECK-NEXT: vptestnmd %ymm1, %ymm1, %k11215; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[0,1,2,3]1216; CHECK-NEXT: retq1217 %vec2 = load <8 x i32>, ptr %vec2p1218 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1219 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1220 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1221 ret <8 x i32> %res1222}1223 1224define <8 x i32> @test_8xi32_shuff_mem_mask3(<8 x i32> %vec1, ptr %vec2p) {1225; CHECK-LABEL: test_8xi32_shuff_mem_mask3:1226; CHECK: # %bb.0:1227; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[0,1]1228; CHECK-NEXT: retq1229 %vec2 = load <8 x i32>, ptr %vec2p1230 %res = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1231 ret <8 x i32> %res1232}1233define <8 x i32> @test_8xi32_masked_shuff_mem_mask3(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %vec3, <8 x i32> %mask) {1234; CHECK-LABEL: test_8xi32_masked_shuff_mem_mask3:1235; CHECK: # %bb.0:1236; CHECK-NEXT: vptestnmd %ymm2, %ymm2, %k11237; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm1 {%k1} = ymm0[4,5,6,7],mem[0,1,2,3]1238; CHECK-NEXT: vmovdqa %ymm1, %ymm01239; CHECK-NEXT: retq1240 %vec2 = load <8 x i32>, ptr %vec2p1241 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1242 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1243 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> %vec31244 ret <8 x i32> %res1245}1246 1247define <8 x i32> @test_8xi32_zero_masked_shuff_mem_mask3(<8 x i32> %vec1, ptr %vec2p, <8 x i32> %mask) {1248; CHECK-LABEL: test_8xi32_zero_masked_shuff_mem_mask3:1249; CHECK: # %bb.0:1250; CHECK-NEXT: vptestnmd %ymm1, %ymm1, %k11251; CHECK-NEXT: vshufi32x4 {{.*#+}} ymm0 {%k1} {z} = ymm0[4,5,6,7],mem[0,1,2,3]1252; CHECK-NEXT: retq1253 %vec2 = load <8 x i32>, ptr %vec2p1254 %shuf = shufflevector <8 x i32> %vec1, <8 x i32> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>1255 %cmp = icmp eq <8 x i32> %mask, zeroinitializer1256 %res = select <8 x i1> %cmp, <8 x i32> %shuf, <8 x i32> zeroinitializer1257 ret <8 x i32> %res1258}1259 1260define <16 x i32> @test_16xi32_shuff_mask0(<16 x i32> %vec1, <16 x i32> %vec2) {1261; CHECK-LABEL: test_16xi32_shuff_mask0:1262; CHECK: # %bb.0:1263; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],zmm1[2,3,6,7]1264; CHECK-NEXT: retq1265 %res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1266 ret <16 x i32> %res1267}1268define <16 x i32> @test_16xi32_masked_shuff_mask0(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %vec3, <16 x i32> %mask) {1269; CHECK-LABEL: test_16xi32_masked_shuff_mask0:1270; CHECK: # %bb.0:1271; CHECK-NEXT: vptestnmd %zmm3, %zmm3, %k11272; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 {%k1} = zmm0[4,5,6,7,4,5,6,7],zmm1[4,5,6,7,12,13,14,15]1273; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01274; CHECK-NEXT: retq1275 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1276 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1277 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31278 ret <16 x i32> %res1279}1280 1281define <16 x i32> @test_16xi32_zero_masked_shuff_mask0(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %mask) {1282; CHECK-LABEL: test_16xi32_zero_masked_shuff_mask0:1283; CHECK: # %bb.0:1284; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11285; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,4,5,6,7],zmm1[4,5,6,7,12,13,14,15]1286; CHECK-NEXT: retq1287 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1288 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1289 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1290 ret <16 x i32> %res1291}1292define <16 x i32> @test_16xi32_masked_shuff_mask1(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %vec3, <16 x i32> %mask) {1293; CHECK-LABEL: test_16xi32_masked_shuff_mask1:1294; CHECK: # %bb.0:1295; CHECK-NEXT: vptestnmd %zmm3, %zmm3, %k11296; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 {%k1} = zmm0[8,9,10,11,8,9,10,11],zmm1[8,9,10,11,4,5,6,7]1297; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01298; CHECK-NEXT: retq1299 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>1300 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1301 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31302 ret <16 x i32> %res1303}1304 1305define <16 x i32> @test_16xi32_zero_masked_shuff_mask1(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %mask) {1306; CHECK-LABEL: test_16xi32_zero_masked_shuff_mask1:1307; CHECK: # %bb.0:1308; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11309; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[8,9,10,11,8,9,10,11],zmm1[8,9,10,11,4,5,6,7]1310; CHECK-NEXT: retq1311 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>1312 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1313 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1314 ret <16 x i32> %res1315}1316define <16 x i32> @test_16xi32_masked_shuff_mask2(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %vec3, <16 x i32> %mask) {1317; CHECK-LABEL: test_16xi32_masked_shuff_mask2:1318; CHECK: # %bb.0:1319; CHECK-NEXT: vptestnmd %zmm3, %zmm3, %k11320; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 {%k1} = zmm0[4,5,6,7,8,9,10,11],zmm1[0,1,2,3,0,1,2,3]1321; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01322; CHECK-NEXT: retq1323 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 16, i32 17, i32 18, i32 19>1324 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1325 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31326 ret <16 x i32> %res1327}1328 1329define <16 x i32> @test_16xi32_zero_masked_shuff_mask2(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %mask) {1330; CHECK-LABEL: test_16xi32_zero_masked_shuff_mask2:1331; CHECK: # %bb.0:1332; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11333; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,8,9,10,11],zmm1[0,1,2,3,0,1,2,3]1334; CHECK-NEXT: retq1335 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19, i32 16, i32 17, i32 18, i32 19>1336 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1337 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1338 ret <16 x i32> %res1339}1340define <16 x i32> @test_16xi32_shuff_mask3(<16 x i32> %vec1, <16 x i32> %vec2) {1341; CHECK-LABEL: test_16xi32_shuff_mask3:1342; CHECK: # %bb.0:1343; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],zmm1[4,5,2,3]1344; CHECK-NEXT: retq1345 %res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>1346 ret <16 x i32> %res1347}1348define <16 x i32> @test_16xi32_masked_shuff_mask3(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %vec3, <16 x i32> %mask) {1349; CHECK-LABEL: test_16xi32_masked_shuff_mask3:1350; CHECK: # %bb.0:1351; CHECK-NEXT: vptestnmd %zmm3, %zmm3, %k11352; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm2 {%k1} = zmm0[4,5,6,7,0,1,2,3],zmm1[8,9,10,11,4,5,6,7]1353; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01354; CHECK-NEXT: retq1355 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>1356 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1357 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31358 ret <16 x i32> %res1359}1360 1361define <16 x i32> @test_16xi32_zero_masked_shuff_mask3(<16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> %mask) {1362; CHECK-LABEL: test_16xi32_zero_masked_shuff_mask3:1363; CHECK: # %bb.0:1364; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11365; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,0,1,2,3],zmm1[8,9,10,11,4,5,6,7]1366; CHECK-NEXT: retq1367 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 24, i32 25, i32 26, i32 27, i32 20, i32 21, i32 22, i32 23>1368 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1369 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1370 ret <16 x i32> %res1371}1372define <16 x i32> @test_16xi32_shuff_mem_mask0(<16 x i32> %vec1, ptr %vec2p) {1373; CHECK-LABEL: test_16xi32_shuff_mem_mask0:1374; CHECK: # %bb.0:1375; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,2,3],mem[4,5,0,1]1376; CHECK-NEXT: retq1377 %vec2 = load <16 x i32>, ptr %vec2p1378 %res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 16, i32 17, i32 18, i32 19>1379 ret <16 x i32> %res1380}1381define <16 x i32> @test_16xi32_masked_shuff_mem_mask0(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %vec3, <16 x i32> %mask) {1382; CHECK-LABEL: test_16xi32_masked_shuff_mem_mask0:1383; CHECK: # %bb.0:1384; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11385; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 {%k1} = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,0,1,2,3]1386; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01387; CHECK-NEXT: retq1388 %vec2 = load <16 x i32>, ptr %vec2p1389 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 16, i32 17, i32 18, i32 19>1390 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1391 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31392 ret <16 x i32> %res1393}1394 1395define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask0(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %mask) {1396; CHECK-LABEL: test_16xi32_zero_masked_shuff_mem_mask0:1397; CHECK: # %bb.0:1398; CHECK-NEXT: vptestnmd %zmm1, %zmm1, %k11399; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[8,9,10,11,4,5,6,7],mem[8,9,10,11,0,1,2,3]1400; CHECK-NEXT: retq1401 %vec2 = load <16 x i32>, ptr %vec2p1402 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 16, i32 17, i32 18, i32 19>1403 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1404 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1405 ret <16 x i32> %res1406}1407 1408define <16 x i32> @test_16xi32_masked_shuff_mem_mask1(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %vec3, <16 x i32> %mask) {1409; CHECK-LABEL: test_16xi32_masked_shuff_mem_mask1:1410; CHECK: # %bb.0:1411; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11412; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 {%k1} = zmm0[4,5,6,7,4,5,6,7],mem[0,1,2,3,8,9,10,11]1413; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01414; CHECK-NEXT: retq1415 %vec2 = load <16 x i32>, ptr %vec2p1416 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>1417 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1418 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31419 ret <16 x i32> %res1420}1421 1422define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask1(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %mask) {1423; CHECK-LABEL: test_16xi32_zero_masked_shuff_mem_mask1:1424; CHECK: # %bb.0:1425; CHECK-NEXT: vptestnmd %zmm1, %zmm1, %k11426; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,4,5,6,7],mem[0,1,2,3,8,9,10,11]1427; CHECK-NEXT: retq1428 %vec2 = load <16 x i32>, ptr %vec2p1429 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 24, i32 25, i32 26, i32 27>1430 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1431 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1432 ret <16 x i32> %res1433}1434 1435define <16 x i32> @test_16xi32_masked_shuff_mem_mask2(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %vec3, <16 x i32> %mask) {1436; CHECK-LABEL: test_16xi32_masked_shuff_mem_mask2:1437; CHECK: # %bb.0:1438; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11439; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 {%k1} = zmm0[4,5,6,7,8,9,10,11],mem[12,13,14,15,12,13,14,15]1440; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01441; CHECK-NEXT: retq1442 %vec2 = load <16 x i32>, ptr %vec2p1443 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>1444 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1445 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31446 ret <16 x i32> %res1447}1448 1449define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask2(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %mask) {1450; CHECK-LABEL: test_16xi32_zero_masked_shuff_mem_mask2:1451; CHECK: # %bb.0:1452; CHECK-NEXT: vptestnmd %zmm1, %zmm1, %k11453; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,8,9,10,11],mem[12,13,14,15,12,13,14,15]1454; CHECK-NEXT: retq1455 %vec2 = load <16 x i32>, ptr %vec2p1456 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>1457 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1458 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1459 ret <16 x i32> %res1460}1461 1462define <16 x i32> @test_16xi32_shuff_mem_mask3(<16 x i32> %vec1, ptr %vec2p) {1463; CHECK-LABEL: test_16xi32_shuff_mem_mask3:1464; CHECK: # %bb.0:1465; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],mem[2,3,6,7]1466; CHECK-NEXT: retq1467 %vec2 = load <16 x i32>, ptr %vec2p1468 %res = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1469 ret <16 x i32> %res1470}1471define <16 x i32> @test_16xi32_masked_shuff_mem_mask3(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %vec3, <16 x i32> %mask) {1472; CHECK-LABEL: test_16xi32_masked_shuff_mem_mask3:1473; CHECK: # %bb.0:1474; CHECK-NEXT: vptestnmd %zmm2, %zmm2, %k11475; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm1 {%k1} = zmm0[4,5,6,7,4,5,6,7],mem[4,5,6,7,12,13,14,15]1476; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01477; CHECK-NEXT: retq1478 %vec2 = load <16 x i32>, ptr %vec2p1479 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1480 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1481 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> %vec31482 ret <16 x i32> %res1483}1484 1485define <16 x i32> @test_16xi32_zero_masked_shuff_mem_mask3(<16 x i32> %vec1, ptr %vec2p, <16 x i32> %mask) {1486; CHECK-LABEL: test_16xi32_zero_masked_shuff_mem_mask3:1487; CHECK: # %bb.0:1488; CHECK-NEXT: vptestnmd %zmm1, %zmm1, %k11489; CHECK-NEXT: vshufi32x4 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,6,7,4,5,6,7],mem[4,5,6,7,12,13,14,15]1490; CHECK-NEXT: retq1491 %vec2 = load <16 x i32>, ptr %vec2p1492 %shuf = shufflevector <16 x i32> %vec1, <16 x i32> %vec2, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31>1493 %cmp = icmp eq <16 x i32> %mask, zeroinitializer1494 %res = select <16 x i1> %cmp, <16 x i32> %shuf, <16 x i32> zeroinitializer1495 ret <16 x i32> %res1496}1497 1498define <4 x i64> @test_4xi64_shuff_mask0(<4 x i64> %vec1, <4 x i64> %vec2) {1499; CHECK-LABEL: test_4xi64_shuff_mask0:1500; CHECK: # %bb.0:1501; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]1502; CHECK-NEXT: retq1503 %res = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1504 ret <4 x i64> %res1505}1506define <4 x i64> @test_4xi64_masked_shuff_mask0(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %vec3, <4 x i64> %mask) {1507; CHECK-LABEL: test_4xi64_masked_shuff_mask0:1508; CHECK: # %bb.0:1509; CHECK-NEXT: vptestnmq %ymm3, %ymm3, %k11510; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[0,1]1511; CHECK-NEXT: vmovdqa %ymm2, %ymm01512; CHECK-NEXT: retq1513 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1514 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1515 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31516 ret <4 x i64> %res1517}1518 1519define <4 x i64> @test_4xi64_zero_masked_shuff_mask0(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %mask) {1520; CHECK-LABEL: test_4xi64_zero_masked_shuff_mask0:1521; CHECK: # %bb.0:1522; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11523; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[0,1]1524; CHECK-NEXT: retq1525 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1526 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1527 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1528 ret <4 x i64> %res1529}1530define <4 x i64> @test_4xi64_masked_shuff_mask1(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %vec3, <4 x i64> %mask) {1531; CHECK-LABEL: test_4xi64_masked_shuff_mask1:1532; CHECK: # %bb.0:1533; CHECK-NEXT: vptestnmq %ymm3, %ymm3, %k11534; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[2,3]1535; CHECK-NEXT: vmovdqa %ymm2, %ymm01536; CHECK-NEXT: retq1537 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1538 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1539 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31540 ret <4 x i64> %res1541}1542 1543define <4 x i64> @test_4xi64_zero_masked_shuff_mask1(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %mask) {1544; CHECK-LABEL: test_4xi64_zero_masked_shuff_mask1:1545; CHECK: # %bb.0:1546; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11547; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[2,3]1548; CHECK-NEXT: retq1549 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1550 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1551 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1552 ret <4 x i64> %res1553}1554define <4 x i64> @test_4xi64_masked_shuff_mask2(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %vec3, <4 x i64> %mask) {1555; CHECK-LABEL: test_4xi64_masked_shuff_mask2:1556; CHECK: # %bb.0:1557; CHECK-NEXT: vptestnmq %ymm3, %ymm3, %k11558; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[0,1]1559; CHECK-NEXT: vmovdqa %ymm2, %ymm01560; CHECK-NEXT: retq1561 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1562 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1563 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31564 ret <4 x i64> %res1565}1566 1567define <4 x i64> @test_4xi64_zero_masked_shuff_mask2(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %mask) {1568; CHECK-LABEL: test_4xi64_zero_masked_shuff_mask2:1569; CHECK: # %bb.0:1570; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11571; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[0,1]1572; CHECK-NEXT: retq1573 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1574 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1575 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1576 ret <4 x i64> %res1577}1578define <4 x i64> @test_4xi64_shuff_mask3(<4 x i64> %vec1, <4 x i64> %vec2) {1579; CHECK-LABEL: test_4xi64_shuff_mask3:1580; CHECK: # %bb.0:1581; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]1582; CHECK-NEXT: retq1583 %res = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1584 ret <4 x i64> %res1585}1586define <4 x i64> @test_4xi64_masked_shuff_mask3(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %vec3, <4 x i64> %mask) {1587; CHECK-LABEL: test_4xi64_masked_shuff_mask3:1588; CHECK: # %bb.0:1589; CHECK-NEXT: vptestnmq %ymm3, %ymm3, %k11590; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm2 {%k1} = ymm0[2,3],ymm1[2,3]1591; CHECK-NEXT: vmovdqa %ymm2, %ymm01592; CHECK-NEXT: retq1593 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1594 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1595 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31596 ret <4 x i64> %res1597}1598 1599define <4 x i64> @test_4xi64_zero_masked_shuff_mask3(<4 x i64> %vec1, <4 x i64> %vec2, <4 x i64> %mask) {1600; CHECK-LABEL: test_4xi64_zero_masked_shuff_mask3:1601; CHECK: # %bb.0:1602; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11603; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],ymm1[2,3]1604; CHECK-NEXT: retq1605 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1606 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1607 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1608 ret <4 x i64> %res1609}1610define <4 x i64> @test_4xi64_shuff_mem_mask0(<4 x i64> %vec1, ptr %vec2p) {1611; CHECK-LABEL: test_4xi64_shuff_mem_mask0:1612; CHECK: # %bb.0:1613; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]1614; CHECK-NEXT: retq1615 %vec2 = load <4 x i64>, ptr %vec2p1616 %res = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1617 ret <4 x i64> %res1618}1619define <4 x i64> @test_4xi64_masked_shuff_mem_mask0(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %vec3, <4 x i64> %mask) {1620; CHECK-LABEL: test_4xi64_masked_shuff_mem_mask0:1621; CHECK: # %bb.0:1622; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11623; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[2,3]1624; CHECK-NEXT: vmovdqa %ymm1, %ymm01625; CHECK-NEXT: retq1626 %vec2 = load <4 x i64>, ptr %vec2p1627 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1628 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1629 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31630 ret <4 x i64> %res1631}1632 1633define <4 x i64> @test_4xi64_zero_masked_shuff_mem_mask0(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %mask) {1634; CHECK-LABEL: test_4xi64_zero_masked_shuff_mem_mask0:1635; CHECK: # %bb.0:1636; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k11637; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[2,3]1638; CHECK-NEXT: retq1639 %vec2 = load <4 x i64>, ptr %vec2p1640 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1641 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1642 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1643 ret <4 x i64> %res1644}1645 1646define <4 x i64> @test_4xi64_masked_shuff_mem_mask1(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %vec3, <4 x i64> %mask) {1647; CHECK-LABEL: test_4xi64_masked_shuff_mem_mask1:1648; CHECK: # %bb.0:1649; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11650; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[0,1]1651; CHECK-NEXT: vmovdqa %ymm1, %ymm01652; CHECK-NEXT: retq1653 %vec2 = load <4 x i64>, ptr %vec2p1654 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1655 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1656 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31657 ret <4 x i64> %res1658}1659 1660define <4 x i64> @test_4xi64_zero_masked_shuff_mem_mask1(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %mask) {1661; CHECK-LABEL: test_4xi64_zero_masked_shuff_mem_mask1:1662; CHECK: # %bb.0:1663; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k11664; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[0,1]1665; CHECK-NEXT: retq1666 %vec2 = load <4 x i64>, ptr %vec2p1667 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1668 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1669 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1670 ret <4 x i64> %res1671}1672 1673define <4 x i64> @test_4xi64_masked_shuff_mem_mask2(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %vec3, <4 x i64> %mask) {1674; CHECK-LABEL: test_4xi64_masked_shuff_mem_mask2:1675; CHECK: # %bb.0:1676; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11677; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[0,1]1678; CHECK-NEXT: vmovdqa %ymm1, %ymm01679; CHECK-NEXT: retq1680 %vec2 = load <4 x i64>, ptr %vec2p1681 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1682 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1683 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31684 ret <4 x i64> %res1685}1686 1687define <4 x i64> @test_4xi64_zero_masked_shuff_mem_mask2(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %mask) {1688; CHECK-LABEL: test_4xi64_zero_masked_shuff_mem_mask2:1689; CHECK: # %bb.0:1690; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k11691; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[0,1]1692; CHECK-NEXT: retq1693 %vec2 = load <4 x i64>, ptr %vec2p1694 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>1695 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1696 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1697 ret <4 x i64> %res1698}1699 1700define <4 x i64> @test_4xi64_shuff_mem_mask3(<4 x i64> %vec1, ptr %vec2p) {1701; CHECK-LABEL: test_4xi64_shuff_mem_mask3:1702; CHECK: # %bb.0:1703; CHECK-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],mem[2,3]1704; CHECK-NEXT: retq1705 %vec2 = load <4 x i64>, ptr %vec2p1706 %res = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1707 ret <4 x i64> %res1708}1709define <4 x i64> @test_4xi64_masked_shuff_mem_mask3(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %vec3, <4 x i64> %mask) {1710; CHECK-LABEL: test_4xi64_masked_shuff_mem_mask3:1711; CHECK: # %bb.0:1712; CHECK-NEXT: vptestnmq %ymm2, %ymm2, %k11713; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm1 {%k1} = ymm0[2,3],mem[2,3]1714; CHECK-NEXT: vmovdqa %ymm1, %ymm01715; CHECK-NEXT: retq1716 %vec2 = load <4 x i64>, ptr %vec2p1717 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1718 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1719 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> %vec31720 ret <4 x i64> %res1721}1722 1723define <4 x i64> @test_4xi64_zero_masked_shuff_mem_mask3(<4 x i64> %vec1, ptr %vec2p, <4 x i64> %mask) {1724; CHECK-LABEL: test_4xi64_zero_masked_shuff_mem_mask3:1725; CHECK: # %bb.0:1726; CHECK-NEXT: vptestnmq %ymm1, %ymm1, %k11727; CHECK-NEXT: vshufi64x2 {{.*#+}} ymm0 {%k1} {z} = ymm0[2,3],mem[2,3]1728; CHECK-NEXT: retq1729 %vec2 = load <4 x i64>, ptr %vec2p1730 %shuf = shufflevector <4 x i64> %vec1, <4 x i64> %vec2, <4 x i32> <i32 2, i32 3, i32 6, i32 7>1731 %cmp = icmp eq <4 x i64> %mask, zeroinitializer1732 %res = select <4 x i1> %cmp, <4 x i64> %shuf, <4 x i64> zeroinitializer1733 ret <4 x i64> %res1734}1735 1736define <8 x i64> @test_8xi64_shuff_mask0(<8 x i64> %vec1, <8 x i64> %vec2) {1737; CHECK-LABEL: test_8xi64_shuff_mask0:1738; CHECK: # %bb.0:1739; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[4,5,4,5],zmm1[4,5,4,5]1740; CHECK-NEXT: retq1741 %res = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 12, i32 13>1742 ret <8 x i64> %res1743}1744define <8 x i64> @test_8xi64_masked_shuff_mask0(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %vec3, <8 x i64> %mask) {1745; CHECK-LABEL: test_8xi64_masked_shuff_mask0:1746; CHECK: # %bb.0:1747; CHECK-NEXT: vptestnmq %zmm3, %zmm3, %k11748; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 {%k1} = zmm0[4,5,4,5],zmm1[4,5,4,5]1749; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01750; CHECK-NEXT: retq1751 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 12, i32 13>1752 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1753 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31754 ret <8 x i64> %res1755}1756 1757define <8 x i64> @test_8xi64_zero_masked_shuff_mask0(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %mask) {1758; CHECK-LABEL: test_8xi64_zero_masked_shuff_mask0:1759; CHECK: # %bb.0:1760; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11761; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,4,5],zmm1[4,5,4,5]1762; CHECK-NEXT: retq1763 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 4, i32 5, i32 4, i32 5, i32 12, i32 13, i32 12, i32 13>1764 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1765 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1766 ret <8 x i64> %res1767}1768define <8 x i64> @test_8xi64_masked_shuff_mask1(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %vec3, <8 x i64> %mask) {1769; CHECK-LABEL: test_8xi64_masked_shuff_mask1:1770; CHECK: # %bb.0:1771; CHECK-NEXT: vptestnmq %zmm3, %zmm3, %k11772; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 {%k1} = zmm0[6,7,4,5],zmm1[2,3,4,5]1773; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01774; CHECK-NEXT: retq1775 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 12, i32 13>1776 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1777 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31778 ret <8 x i64> %res1779}1780 1781define <8 x i64> @test_8xi64_zero_masked_shuff_mask1(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %mask) {1782; CHECK-LABEL: test_8xi64_zero_masked_shuff_mask1:1783; CHECK: # %bb.0:1784; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11785; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[6,7,4,5],zmm1[2,3,4,5]1786; CHECK-NEXT: retq1787 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 12, i32 13>1788 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1789 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1790 ret <8 x i64> %res1791}1792define <8 x i64> @test_8xi64_masked_shuff_mask2(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %vec3, <8 x i64> %mask) {1793; CHECK-LABEL: test_8xi64_masked_shuff_mask2:1794; CHECK: # %bb.0:1795; CHECK-NEXT: vptestnmq %zmm3, %zmm3, %k11796; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 {%k1} = zmm0[0,1,4,5],zmm1[0,1,0,1]1797; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01798; CHECK-NEXT: retq1799 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 8, i32 9>1800 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1801 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31802 ret <8 x i64> %res1803}1804 1805define <8 x i64> @test_8xi64_zero_masked_shuff_mask2(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %mask) {1806; CHECK-LABEL: test_8xi64_zero_masked_shuff_mask2:1807; CHECK: # %bb.0:1808; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11809; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[0,1,4,5],zmm1[0,1,0,1]1810; CHECK-NEXT: retq1811 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 8, i32 9>1812 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1813 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1814 ret <8 x i64> %res1815}1816define <8 x i64> @test_8xi64_shuff_mask3(<8 x i64> %vec1, <8 x i64> %vec2) {1817; CHECK-LABEL: test_8xi64_shuff_mask3:1818; CHECK: # %bb.0:1819; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,6,7],zmm1[4,5,2,3]1820; CHECK-NEXT: retq1821 %res = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 6, i32 7, i32 12, i32 13, i32 10, i32 11>1822 ret <8 x i64> %res1823}1824define <8 x i64> @test_8xi64_masked_shuff_mask3(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %vec3, <8 x i64> %mask) {1825; CHECK-LABEL: test_8xi64_masked_shuff_mask3:1826; CHECK: # %bb.0:1827; CHECK-NEXT: vptestnmq %zmm3, %zmm3, %k11828; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm2 {%k1} = zmm0[2,3,6,7],zmm1[4,5,2,3]1829; CHECK-NEXT: vmovdqa64 %zmm2, %zmm01830; CHECK-NEXT: retq1831 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 6, i32 7, i32 12, i32 13, i32 10, i32 11>1832 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1833 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31834 ret <8 x i64> %res1835}1836 1837define <8 x i64> @test_8xi64_zero_masked_shuff_mask3(<8 x i64> %vec1, <8 x i64> %vec2, <8 x i64> %mask) {1838; CHECK-LABEL: test_8xi64_zero_masked_shuff_mask3:1839; CHECK: # %bb.0:1840; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11841; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[2,3,6,7],zmm1[4,5,2,3]1842; CHECK-NEXT: retq1843 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 6, i32 7, i32 12, i32 13, i32 10, i32 11>1844 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1845 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1846 ret <8 x i64> %res1847}1848define <8 x i64> @test_8xi64_shuff_mem_mask0(<8 x i64> %vec1, ptr %vec2p) {1849; CHECK-LABEL: test_8xi64_shuff_mem_mask0:1850; CHECK: # %bb.0:1851; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,2,3],mem[4,5,2,3]1852; CHECK-NEXT: retq1853 %vec2 = load <8 x i64>, ptr %vec2p1854 %res = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 12, i32 13, i32 10, i32 11>1855 ret <8 x i64> %res1856}1857define <8 x i64> @test_8xi64_masked_shuff_mem_mask0(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %vec3, <8 x i64> %mask) {1858; CHECK-LABEL: test_8xi64_masked_shuff_mem_mask0:1859; CHECK: # %bb.0:1860; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11861; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 {%k1} = zmm0[2,3,2,3],mem[4,5,2,3]1862; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01863; CHECK-NEXT: retq1864 %vec2 = load <8 x i64>, ptr %vec2p1865 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 12, i32 13, i32 10, i32 11>1866 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1867 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31868 ret <8 x i64> %res1869}1870 1871define <8 x i64> @test_8xi64_zero_masked_shuff_mem_mask0(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %mask) {1872; CHECK-LABEL: test_8xi64_zero_masked_shuff_mem_mask0:1873; CHECK: # %bb.0:1874; CHECK-NEXT: vptestnmq %zmm1, %zmm1, %k11875; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[2,3,2,3],mem[4,5,2,3]1876; CHECK-NEXT: retq1877 %vec2 = load <8 x i64>, ptr %vec2p1878 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 2, i32 3, i32 12, i32 13, i32 10, i32 11>1879 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1880 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1881 ret <8 x i64> %res1882}1883 1884define <8 x i64> @test_8xi64_masked_shuff_mem_mask1(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %vec3, <8 x i64> %mask) {1885; CHECK-LABEL: test_8xi64_masked_shuff_mem_mask1:1886; CHECK: # %bb.0:1887; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11888; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 {%k1} = zmm0[2,3,0,1],mem[0,1,0,1]1889; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01890; CHECK-NEXT: retq1891 %vec2 = load <8 x i64>, ptr %vec2p1892 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 8, i32 9, i32 8, i32 9>1893 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1894 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31895 ret <8 x i64> %res1896}1897 1898define <8 x i64> @test_8xi64_zero_masked_shuff_mem_mask1(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %mask) {1899; CHECK-LABEL: test_8xi64_zero_masked_shuff_mem_mask1:1900; CHECK: # %bb.0:1901; CHECK-NEXT: vptestnmq %zmm1, %zmm1, %k11902; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[2,3,0,1],mem[0,1,0,1]1903; CHECK-NEXT: retq1904 %vec2 = load <8 x i64>, ptr %vec2p1905 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 8, i32 9, i32 8, i32 9>1906 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1907 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1908 ret <8 x i64> %res1909}1910 1911define <8 x i64> @test_8xi64_masked_shuff_mem_mask2(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %vec3, <8 x i64> %mask) {1912; CHECK-LABEL: test_8xi64_masked_shuff_mem_mask2:1913; CHECK: # %bb.0:1914; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11915; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 {%k1} = zmm0[4,5,0,1],mem[2,3,2,3]1916; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01917; CHECK-NEXT: retq1918 %vec2 = load <8 x i64>, ptr %vec2p1919 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 4, i32 5, i32 0, i32 1, i32 10, i32 11, i32 10, i32 11>1920 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1921 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31922 ret <8 x i64> %res1923}1924 1925define <8 x i64> @test_8xi64_zero_masked_shuff_mem_mask2(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %mask) {1926; CHECK-LABEL: test_8xi64_zero_masked_shuff_mem_mask2:1927; CHECK: # %bb.0:1928; CHECK-NEXT: vptestnmq %zmm1, %zmm1, %k11929; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[4,5,0,1],mem[2,3,2,3]1930; CHECK-NEXT: retq1931 %vec2 = load <8 x i64>, ptr %vec2p1932 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 4, i32 5, i32 0, i32 1, i32 10, i32 11, i32 10, i32 11>1933 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1934 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1935 ret <8 x i64> %res1936}1937 1938define <8 x i64> @test_8xi64_shuff_mem_mask3(<8 x i64> %vec1, ptr %vec2p) {1939; CHECK-LABEL: test_8xi64_shuff_mem_mask3:1940; CHECK: # %bb.0:1941; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[2,3,0,1],mem[6,7,2,3]1942; CHECK-NEXT: retq1943 %vec2 = load <8 x i64>, ptr %vec2p1944 %res = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 14, i32 15, i32 10, i32 11>1945 ret <8 x i64> %res1946}1947define <8 x i64> @test_8xi64_masked_shuff_mem_mask3(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %vec3, <8 x i64> %mask) {1948; CHECK-LABEL: test_8xi64_masked_shuff_mem_mask3:1949; CHECK: # %bb.0:1950; CHECK-NEXT: vptestnmq %zmm2, %zmm2, %k11951; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm1 {%k1} = zmm0[2,3,0,1],mem[6,7,2,3]1952; CHECK-NEXT: vmovdqa64 %zmm1, %zmm01953; CHECK-NEXT: retq1954 %vec2 = load <8 x i64>, ptr %vec2p1955 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 14, i32 15, i32 10, i32 11>1956 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1957 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> %vec31958 ret <8 x i64> %res1959}1960 1961define <8 x i64> @test_8xi64_zero_masked_shuff_mem_mask3(<8 x i64> %vec1, ptr %vec2p, <8 x i64> %mask) {1962; CHECK-LABEL: test_8xi64_zero_masked_shuff_mem_mask3:1963; CHECK: # %bb.0:1964; CHECK-NEXT: vptestnmq %zmm1, %zmm1, %k11965; CHECK-NEXT: vshufi64x2 {{.*#+}} zmm0 {%k1} {z} = zmm0[2,3,0,1],mem[6,7,2,3]1966; CHECK-NEXT: retq1967 %vec2 = load <8 x i64>, ptr %vec2p1968 %shuf = shufflevector <8 x i64> %vec1, <8 x i64> %vec2, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 14, i32 15, i32 10, i32 11>1969 %cmp = icmp eq <8 x i64> %mask, zeroinitializer1970 %res = select <8 x i1> %cmp, <8 x i64> %shuf, <8 x i64> zeroinitializer1971 ret <8 x i64> %res1972}1973 1974