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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -mattr=+avx512fp16 -mattr=+avx512vl | FileCheck %s3 4declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)5declare <4 x float> @llvm.x86.avx512fp16.maskz.vfmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)6declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)7declare <4 x float> @llvm.x86.avx512fp16.maskz.vfcmul.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)8declare <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)9declare <4 x float> @llvm.x86.avx512fp16.maskz.vfmadd.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)10declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)11declare <4 x float> @llvm.x86.avx512fp16.maskz.vfcmadd.csh(<4 x float>, <4 x float>, <4 x float>, i8, i32)12 13;; no mask, no rounding14 15define <4 x float> @test_nm_nr_int_x86_avx512fp16_mask_cfmul_sh(<4 x float> %x0, <4 x float> %x1) {16; CHECK-LABEL: test_nm_nr_int_x86_avx512fp16_mask_cfmul_sh:17; CHECK: ## %bb.0:18; CHECK-NEXT: vfmulcsh %xmm1, %xmm0, %xmm219; CHECK-NEXT: vmovaps %xmm2, %xmm020; CHECK-NEXT: retq21 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> undef, i8 -1, i32 4)22 ret <4 x float> %res23}24 25define <4 x float> @test_nm_nr_int_x86_avx512fp16_mask_cfcmul_sh(<4 x float> %x0, <4 x float> %x1) {26; CHECK-LABEL: test_nm_nr_int_x86_avx512fp16_mask_cfcmul_sh:27; CHECK: ## %bb.0:28; CHECK-NEXT: vfcmulcsh %xmm1, %xmm0, %xmm229; CHECK-NEXT: vmovaps %xmm2, %xmm030; CHECK-NEXT: retq31 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> undef, i8 -1, i32 4)32 ret <4 x float> %res33}34 35define <4 x float> @test_nm_nr_int_x86_avx512fp16_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2) {36; CHECK-LABEL: test_nm_nr_int_x86_avx512fp16_cfmadd_sh:37; CHECK: ## %bb.0:38; CHECK-NEXT: vfmaddcsh %xmm1, %xmm0, %xmm239; CHECK-NEXT: vmovaps %xmm2, %xmm040; CHECK-NEXT: retq41 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1, i32 4)42 ret <4 x float> %res43}44 45define <4 x float> @test_nm_nr_int_x86_avx512fp16_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2) {46; CHECK-LABEL: test_nm_nr_int_x86_avx512fp16_cfcmadd_sh:47; CHECK: ## %bb.0:48; CHECK-NEXT: vfcmaddcsh %xmm1, %xmm0, %xmm249; CHECK-NEXT: vmovaps %xmm2, %xmm050; CHECK-NEXT: retq51 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1, i32 4)52 ret <4 x float> %res53}54 55;; no mask, rounding56 57define <4 x float> @test_nm_r_int_x86_avx512fp16_mask_cfmul_sh(<4 x float> %x0, <4 x float> %x1) {58; CHECK-LABEL: test_nm_r_int_x86_avx512fp16_mask_cfmul_sh:59; CHECK: ## %bb.0:60; CHECK-NEXT: vfmulcsh {rd-sae}, %xmm1, %xmm0, %xmm261; CHECK-NEXT: vmovaps %xmm2, %xmm062; CHECK-NEXT: retq63 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> undef, i8 -1, i32 9)64 ret <4 x float> %res65}66 67define <4 x float> @test_nm_r_int_x86_avx512fp16_mask_cfcmul_sh(<4 x float> %x0, <4 x float> %x1) {68; CHECK-LABEL: test_nm_r_int_x86_avx512fp16_mask_cfcmul_sh:69; CHECK: ## %bb.0:70; CHECK-NEXT: vfcmulcsh {rd-sae}, %xmm1, %xmm0, %xmm271; CHECK-NEXT: vmovaps %xmm2, %xmm072; CHECK-NEXT: retq73 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> undef, i8 -1, i32 9)74 ret <4 x float> %res75}76 77define <4 x float> @test_nm_r_int_x86_avx512fp16_mask_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2) {78; CHECK-LABEL: test_nm_r_int_x86_avx512fp16_mask_cfmadd_sh:79; CHECK: ## %bb.0:80; CHECK-NEXT: vfmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm281; CHECK-NEXT: vmovaps %xmm2, %xmm082; CHECK-NEXT: retq83 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1, i32 9)84 ret <4 x float> %res85}86 87define <4 x float> @test_nm_r_int_x86_avx512fp16_mask_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2) {88; CHECK-LABEL: test_nm_r_int_x86_avx512fp16_mask_cfcmadd_sh:89; CHECK: ## %bb.0:90; CHECK-NEXT: vfcmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm291; CHECK-NEXT: vmovaps %xmm2, %xmm092; CHECK-NEXT: retq93 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 -1, i32 9)94 ret <4 x float> %res95}96 97;; mask, no rounding98 99define <4 x float> @test_m_nr_int_x86_avx512fp16_mask_cfmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {100; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_mask_cfmul_sh:101; CHECK: ## %bb.0:102; CHECK-NEXT: kmovd %edi, %k1103; CHECK-NEXT: vfmulcsh %xmm1, %xmm0, %xmm2 {%k1}104; CHECK-NEXT: vmovaps %xmm2, %xmm0105; CHECK-NEXT: retq106 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)107 ret <4 x float> %res108}109 110define <4 x float> @test_m_nr_int_x86_avx512fp16_mask_cfcmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {111; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_mask_cfcmul_sh:112; CHECK: ## %bb.0:113; CHECK-NEXT: kmovd %edi, %k1114; CHECK-NEXT: vfcmulcsh %xmm1, %xmm0, %xmm2 {%k1}115; CHECK-NEXT: vmovaps %xmm2, %xmm0116; CHECK-NEXT: retq117 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)118 ret <4 x float> %res119}120 121define <4 x float> @test_m_nr_int_x86_avx512fp16_mask_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {122; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_mask_cfmadd_sh:123; CHECK: ## %bb.0:124; CHECK-NEXT: kmovd %edi, %k1125; CHECK-NEXT: vfmaddcsh %xmm1, %xmm0, %xmm2 {%k1}126; CHECK-NEXT: vmovaps %xmm2, %xmm0127; CHECK-NEXT: retq128 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)129 ret <4 x float> %res130}131 132define <4 x float> @test_m_nr_int_x86_avx512fp16_mask_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {133; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_mask_cfcmadd_sh:134; CHECK: ## %bb.0:135; CHECK-NEXT: kmovd %edi, %k1136; CHECK-NEXT: vfcmaddcsh %xmm1, %xmm0, %xmm2 {%k1}137; CHECK-NEXT: vmovaps %xmm2, %xmm0138; CHECK-NEXT: retq139 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)140 ret <4 x float> %res141}142 143;; mask, rounding144 145define <4 x float> @test_int_x86_avx512fp16_mask_cfmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {146; CHECK-LABEL: test_int_x86_avx512fp16_mask_cfmul_sh:147; CHECK: ## %bb.0:148; CHECK-NEXT: kmovd %edi, %k1149; CHECK-NEXT: vfmulcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}150; CHECK-NEXT: vmovaps %xmm2, %xmm0151; CHECK-NEXT: retq152 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)153 ret <4 x float> %res154}155 156define <4 x float> @test_int_x86_avx512fp16_mask_cfcmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {157; CHECK-LABEL: test_int_x86_avx512fp16_mask_cfcmul_sh:158; CHECK: ## %bb.0:159; CHECK-NEXT: kmovd %edi, %k1160; CHECK-NEXT: vfcmulcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}161; CHECK-NEXT: vmovaps %xmm2, %xmm0162; CHECK-NEXT: retq163 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)164 ret <4 x float> %res165}166 167define <4 x float> @test_int_x86_avx512fp16_mask_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {168; CHECK-LABEL: test_int_x86_avx512fp16_mask_cfmadd_sh:169; CHECK: ## %bb.0:170; CHECK-NEXT: kmovd %edi, %k1171; CHECK-NEXT: vfmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}172; CHECK-NEXT: vmovaps %xmm2, %xmm0173; CHECK-NEXT: retq174 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)175 ret <4 x float> %res176}177 178define <4 x float> @test_int_x86_avx512fp16_mask_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {179; CHECK-LABEL: test_int_x86_avx512fp16_mask_cfcmadd_sh:180; CHECK: ## %bb.0:181; CHECK-NEXT: kmovd %edi, %k1182; CHECK-NEXT: vfcmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1}183; CHECK-NEXT: vmovaps %xmm2, %xmm0184; CHECK-NEXT: retq185 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)186 ret <4 x float> %res187}188 189;; maskz, no rounding190 191define <4 x float> @test_m_nr_int_x86_avx512fp16_maskz_cfmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {192; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_maskz_cfmul_sh:193; CHECK: ## %bb.0:194; CHECK-NEXT: kmovd %edi, %k1195; CHECK-NEXT: vfmulcsh %xmm1, %xmm0, %xmm2 {%k1} {z}196; CHECK-NEXT: vmovaps %xmm2, %xmm0197; CHECK-NEXT: retq198 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 %x3, i32 4)199 ret <4 x float> %res200}201 202define <4 x float> @test_m_nr_int_x86_avx512fp16_maskz_cfcmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {203; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_maskz_cfcmul_sh:204; CHECK: ## %bb.0:205; CHECK-NEXT: kmovd %edi, %k1206; CHECK-NEXT: vfcmulcsh %xmm1, %xmm0, %xmm2 {%k1} {z}207; CHECK-NEXT: vmovaps %xmm2, %xmm0208; CHECK-NEXT: retq209 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 %x3, i32 4)210 ret <4 x float> %res211}212 213define <4 x float> @test_m_nr_int_x86_avx512fp16_maskz_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {214; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_maskz_cfmadd_sh:215; CHECK: ## %bb.0:216; CHECK-NEXT: kmovd %edi, %k1217; CHECK-NEXT: vfmaddcsh %xmm1, %xmm0, %xmm2 {%k1} {z}218; CHECK-NEXT: vmovaps %xmm2, %xmm0219; CHECK-NEXT: retq220 %res = call <4 x float> @llvm.x86.avx512fp16.maskz.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)221 ret <4 x float> %res222}223 224define <4 x float> @test_m_nr_int_x86_avx512fp16_maskz_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {225; CHECK-LABEL: test_m_nr_int_x86_avx512fp16_maskz_cfcmadd_sh:226; CHECK: ## %bb.0:227; CHECK-NEXT: kmovd %edi, %k1228; CHECK-NEXT: vfcmaddcsh %xmm1, %xmm0, %xmm2 {%k1} {z}229; CHECK-NEXT: vmovaps %xmm2, %xmm0230; CHECK-NEXT: retq231 %res = call <4 x float> @llvm.x86.avx512fp16.maskz.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 4)232 ret <4 x float> %res233}234 235;; maskz, rounding236 237define <4 x float> @test_int_x86_avx512fp16_maskz_cfmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {238; CHECK-LABEL: test_int_x86_avx512fp16_maskz_cfmul_sh:239; CHECK: ## %bb.0:240; CHECK-NEXT: kmovd %edi, %k1241; CHECK-NEXT: vfmulcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1} {z}242; CHECK-NEXT: vmovaps %xmm2, %xmm0243; CHECK-NEXT: retq244 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 %x3, i32 9)245 ret <4 x float> %res246}247 248define <4 x float> @test_int_x86_avx512fp16_maskz_cfcmul_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {249; CHECK-LABEL: test_int_x86_avx512fp16_maskz_cfcmul_sh:250; CHECK: ## %bb.0:251; CHECK-NEXT: kmovd %edi, %k1252; CHECK-NEXT: vfcmulcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1} {z}253; CHECK-NEXT: vmovaps %xmm2, %xmm0254; CHECK-NEXT: retq255 %res = call <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> zeroinitializer, i8 %x3, i32 9)256 ret <4 x float> %res257}258 259define <4 x float> @test_int_x86_avx512fp16_maskz_cfmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {260; CHECK-LABEL: test_int_x86_avx512fp16_maskz_cfmadd_sh:261; CHECK: ## %bb.0:262; CHECK-NEXT: kmovd %edi, %k1263; CHECK-NEXT: vfmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1} {z}264; CHECK-NEXT: vmovaps %xmm2, %xmm0265; CHECK-NEXT: retq266 %res = call <4 x float> @llvm.x86.avx512fp16.maskz.vfmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)267 ret <4 x float> %res268}269 270define <4 x float> @test_int_x86_avx512fp16_maskz_cfcmadd_sh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3) {271; CHECK-LABEL: test_int_x86_avx512fp16_maskz_cfcmadd_sh:272; CHECK: ## %bb.0:273; CHECK-NEXT: kmovd %edi, %k1274; CHECK-NEXT: vfcmaddcsh {rd-sae}, %xmm1, %xmm0, %xmm2 {%k1} {z}275; CHECK-NEXT: vmovaps %xmm2, %xmm0276; CHECK-NEXT: retq277 %res = call <4 x float> @llvm.x86.avx512fp16.maskz.vfcmadd.csh(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, i8 %x3, i32 9)278 ret <4 x float> %res279}280 281define <4 x float> @PR98306(i8 %m) {282; CHECK-LABEL: PR98306:283; CHECK: ## %bb.0:284; CHECK-NEXT: kmovd %edi, %k1285; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [7.8125E-3,1.050912E+6,4.203776E+6,1.6815616E+7]286; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [3.2E+1,4.03288064E+8,8.0658432E+8,1.61318502E+9]287; CHECK-NEXT: vfmaddcsh {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0 {%k1} {z}288; CHECK-NEXT: retq289 %res = call <4 x float> @llvm.x86.avx512fp16.maskz.vfmadd.csh(<4 x float> <float 7.812500e-03, float 0x4130092000000000, float 0x4150094000000000, float 0x4170096000000000>, <4 x float> <float 2.000000e+00, float 0x4188098000000000, float 0x4198099000000000, float 0x41A809A000000000>, <4 x float> <float 3.200000e+01, float 0x41B809B000000000, float 0x41C809C000000000, float 0x41D809D000000000>, i8 %m, i32 4)290 ret <4 x float> %res291}292