151 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s3 4define dso_local <32 x half> @test1(<32 x half> %acc.coerce, <32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {5; CHECK-LABEL: test1:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vfcmaddcph %zmm1, %zmm2, %zmm08; CHECK-NEXT: retq9entry:10 %0 = bitcast <32 x half> %lhs.coerce.conj to <16 x i32>11 %xor.i.i = xor <16 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>12 %1 = bitcast <16 x i32> %xor.i.i to <16 x float>13 %2 = bitcast <32 x half> %rhs.coerce to <16 x float>14 %3 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %2, <16 x float> zeroinitializer, i16 -1, i32 4) #215 %4 = bitcast <16 x float> %3 to <32 x half>16 %add = fadd fast <32 x half> %4, %acc.coerce17 ret <32 x half> %add18}19 20define dso_local <32 x half> @test2(<32 x half> %acc.coerce, <32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {21; CHECK-LABEL: test2:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: vfcmaddcph %zmm1, %zmm2, %zmm024; CHECK-NEXT: retq25entry:26 %0 = bitcast <32 x half> %lhs.coerce.conj to <16 x i32>27 %xor.i.i = xor <16 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>28 %1 = bitcast <16 x i32> %xor.i.i to <16 x float>29 %2 = bitcast <32 x half> %rhs.coerce to <16 x float>30 %3 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %2, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4) #231 %4 = bitcast <16 x float> %3 to <32 x half>32 %add = fadd fast <32 x half> %4, %acc.coerce33 ret <32 x half> %add34}35 36define dso_local <16 x half> @test3(<16 x half> %acc.coerce, <16 x half> %lhs.coerce.conj, <16 x half> %rhs.coerce) local_unnamed_addr #0 {37; CHECK-LABEL: test3:38; CHECK: # %bb.0: # %entry39; CHECK-NEXT: vfcmaddcph %ymm1, %ymm2, %ymm040; CHECK-NEXT: retq41entry:42 %0 = bitcast <16 x half> %lhs.coerce.conj to <8 x i32>43 %xor.i.i = xor <8 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>44 %1 = bitcast <8 x i32> %xor.i.i to <8 x float>45 %2 = bitcast <16 x half> %rhs.coerce to <8 x float>46 %3 = tail call fast <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %1, <8 x float> %2, <8 x float> zeroinitializer, i8 -1) #247 %4 = bitcast <8 x float> %3 to <16 x half>48 %add = fadd fast <16 x half> %4, %acc.coerce49 ret <16 x half> %add50}51 52define dso_local <8 x half> @test4(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {53; CHECK-LABEL: test4:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vfcmaddcph %xmm1, %xmm2, %xmm056; CHECK-NEXT: retq57entry:58 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>59 %xor.i.i = xor <4 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>60 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>61 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>62 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #263 %4 = bitcast <4 x float> %3 to <8 x half>64 %add = fadd fast <8 x half> %4, %acc.coerce65 ret <8 x half> %add66}67 68define dso_local <8 x half> @test5(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {69; CHECK-LABEL: test5:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: vfcmaddcph %xmm1, %xmm2, %xmm072; CHECK-NEXT: retq73entry:74 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>75 %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %076 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>77 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>78 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #279 %4 = bitcast <4 x float> %3 to <8 x half>80 %add = fadd fast <8 x half> %4, %acc.coerce81 ret <8 x half> %add82}83 84define dso_local <8 x half> @test6(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {85; CHECK-LABEL: test6:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vpxord {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm188; CHECK-NEXT: vfmaddcph %xmm2, %xmm1, %xmm089; CHECK-NEXT: retq90entry:91 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>92 %xor.i.i = xor <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %093 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>94 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>95 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #296 %4 = bitcast <4 x float> %3 to <8 x half>97 %add = fadd fast <8 x half> %4, %acc.coerce98 ret <8 x half> %add99}100 101define dso_local <8 x half> @test7(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {102; CHECK-LABEL: test7:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: vfcmaddcph %xmm1, %xmm2, %xmm0105; CHECK-NEXT: retq106entry:107 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>108 %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %0109 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>110 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>111 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2112 %4 = bitcast <4 x float> %3 to <8 x half>113 %add = fadd fast <8 x half> %acc.coerce, %4114 ret <8 x half> %add115}116 117define dso_local <8 x half> @test8(<8 x half> %acc.coerce, <4 x float> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {118; CHECK-LABEL: test8:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vfcmaddcph %xmm1, %xmm2, %xmm0121; CHECK-NEXT: retq122entry:123 %0 = bitcast <4 x float> %lhs.coerce.conj to <4 x i32>124 %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %0125 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>126 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>127 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2128 %4 = bitcast <4 x float> %3 to <8 x half>129 %add = fadd fast <8 x half> %acc.coerce, %4130 ret <8 x half> %add131}132 133define dso_local <32 x half> @test9(<32 x half> %acc.coerce, <8 x i64> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {134; CHECK-LABEL: test9:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: vfcmaddcph %zmm1, %zmm2, %zmm0137; CHECK-NEXT: retq138entry:139 %xor1.i = xor <8 x i64> %lhs.coerce.conj, <i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160>140 %0 = bitcast <8 x i64> %xor1.i to <16 x float>141 %1 = bitcast <32 x half> %rhs.coerce to <16 x float>142 %2 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4) #2143 %3 = bitcast <16 x float> %2 to <32 x half>144 %add = fadd fast <32 x half> %3, %acc.coerce145 ret <32 x half> %add146}147 148declare <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)149declare <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)150declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)151