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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s3 4define dso_local <32 x half> @test1(<32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {5; CHECK-LABEL: test1:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vfcmulcph %zmm0, %zmm1, %zmm28; CHECK-NEXT: vmovaps %zmm2, %zmm09; CHECK-NEXT: retq10entry:11 %0 = bitcast <32 x half> %lhs.coerce.conj to <16 x i32>12 %xor.i.i = xor <16 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>13 %1 = bitcast <16 x i32> %xor.i.i to <16 x float>14 %2 = bitcast <32 x half> %rhs.coerce to <16 x float>15 %3 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %2, <16 x float> zeroinitializer, i16 -1, i32 4) #216 %4 = bitcast <16 x float> %3 to <32 x half>17 ret <32 x half> %418}19 20; Function Attrs: nounwind readnone uwtable21define dso_local <16 x half> @test2(<16 x half> %lhs.coerce.conj, <16 x half> %rhs.coerce) local_unnamed_addr #0 {22; CHECK-LABEL: test2:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vfcmulcph %ymm0, %ymm1, %ymm225; CHECK-NEXT: vmovaps %ymm2, %ymm026; CHECK-NEXT: retq27entry:28 %0 = bitcast <16 x half> %lhs.coerce.conj to <8 x i32>29 %xor.i.i = xor <8 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>30 %1 = bitcast <8 x i32> %xor.i.i to <8 x float>31 %2 = bitcast <16 x half> %rhs.coerce to <8 x float>32 %3 = tail call fast <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %1, <8 x float> %2, <8 x float> zeroinitializer, i8 -1) #233 %4 = bitcast <8 x float> %3 to <16 x half>34 ret <16 x half> %435}36 37define dso_local <8 x half> @test3(<8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {38; CHECK-LABEL: test3:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vfcmulcph %xmm0, %xmm1, %xmm241; CHECK-NEXT: vmovaps %xmm2, %xmm042; CHECK-NEXT: retq43entry:44 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>45 %xor.i.i = xor <4 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>46 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>47 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>48 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #249 %4 = bitcast <4 x float> %3 to <8 x half>50 ret <8 x half> %451}52 53define dso_local <8 x half> @test4(<8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {54; CHECK-LABEL: test4:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vfmulcph %xmm0, %xmm1, %xmm257; CHECK-NEXT: vmovaps %xmm2, %xmm058; CHECK-NEXT: retq59entry:60 %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>61 %xor.i.i = xor <4 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>62 %1 = bitcast <4 x i32> %xor.i.i to <4 x float>63 %2 = bitcast <8 x half> %rhs.coerce to <4 x float>64 %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #265 %4 = bitcast <4 x float> %3 to <8 x half>66 ret <8 x half> %467}68 69define dso_local <32 x half> @test5(<32 x half> noundef %a, <32 x half> noundef %b) local_unnamed_addr #0 {70; CHECK-LABEL: test5:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vpbroadcastw {{.*#+}} zmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]73; CHECK-NEXT: vpxorq %zmm2, %zmm1, %zmm274; CHECK-NEXT: vfmulcph %zmm2, %zmm0, %zmm175; CHECK-NEXT: vmovaps %zmm1, %zmm076; CHECK-NEXT: retq77entry:78 %fneg = fneg <32 x half> %b79 %0 = bitcast <32 x half> %a to <16 x float>80 %1 = bitcast <32 x half> %fneg to <16 x float>81 %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)82 %3 = bitcast <16 x float> %2 to <32 x half>83 ret <32 x half> %384}85 86define dso_local <32 x half> @test6(<16 x i32> %a, <16 x float> %b) local_unnamed_addr #0 {87; CHECK-LABEL: test6:88; CHECK: # %bb.0: # %entry89; CHECK-NEXT: vbroadcastss {{.*#+}} zmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]90; CHECK-NEXT: vfcmulcph %zmm0, %zmm1, %zmm391; CHECK-NEXT: vfcmaddcph %zmm0, %zmm2, %zmm392; CHECK-NEXT: vaddph %zmm1, %zmm3, %zmm093; CHECK-NEXT: retq94entry:95 %0 = xor <16 x i32> %a, splat (i32 -2147483648)96 %1 = bitcast <16 x i32> %0 to <16 x float>97 %2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> splat (float 1.000000e+00), <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)98 %3 = bitcast <16 x float> %2 to <32 x half>99 %4 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %b, <16 x float> zeroinitializer, i16 -1, i32 4)100 %5 = bitcast <16 x float> %4 to <32 x half>101 %6 = fadd contract <32 x half> %3, %5102 %7 = bitcast <16 x float> %b to <32 x half>103 %8 = fadd contract <32 x half> %6, %7104 ret <32 x half> %8105}106 107declare <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)108declare <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)109declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)110declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)111