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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X863; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512ifma | FileCheck %s --check-prefixes=CHECK,X644 5; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/avx512ifma-builtins.c6 7define <8 x i64> @test_mm512_madd52hi_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {8; CHECK-LABEL: test_mm512_madd52hi_epu64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm011; CHECK-NEXT: ret{{[l|q]}}12entry:13 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)14 ret <8 x i64> %015}16 17define <8 x i64> @test_mm512_mask_madd52hi_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) {18; X86-LABEL: test_mm512_mask_madd52hi_epu64:19; X86: # %bb.0: # %entry20; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax21; X86-NEXT: kmovw %eax, %k122; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1}23; X86-NEXT: retl24;25; X64-LABEL: test_mm512_mask_madd52hi_epu64:26; X64: # %bb.0: # %entry27; X64-NEXT: kmovw %edi, %k128; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1}29; X64-NEXT: retq30entry:31 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y)32 %1 = bitcast i8 %__M to <8 x i1>33 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W34 ret <8 x i64> %235}36 37define <8 x i64> @test_mm512_maskz_madd52hi_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {38; X86-LABEL: test_mm512_maskz_madd52hi_epu64:39; X86: # %bb.0: # %entry40; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax41; X86-NEXT: kmovw %eax, %k142; X86-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z}43; X86-NEXT: retl44;45; X64-LABEL: test_mm512_maskz_madd52hi_epu64:46; X64: # %bb.0: # %entry47; X64-NEXT: kmovw %edi, %k148; X64-NEXT: vpmadd52huq %zmm2, %zmm1, %zmm0 {%k1} {z}49; X64-NEXT: retq50entry:51 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)52 %1 = bitcast i8 %__M to <8 x i1>53 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer54 ret <8 x i64> %255}56 57define <8 x i64> @test_mm512_madd52lo_epu64(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {58; CHECK-LABEL: test_mm512_madd52lo_epu64:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm061; CHECK-NEXT: ret{{[l|q]}}62entry:63 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)64 ret <8 x i64> %065}66 67define <8 x i64> @test_mm512_mask_madd52lo_epu64(<8 x i64> %__W, i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y) {68; X86-LABEL: test_mm512_mask_madd52lo_epu64:69; X86: # %bb.0: # %entry70; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax71; X86-NEXT: kmovw %eax, %k172; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1}73; X86-NEXT: retl74;75; X64-LABEL: test_mm512_mask_madd52lo_epu64:76; X64: # %bb.0: # %entry77; X64-NEXT: kmovw %edi, %k178; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1}79; X64-NEXT: retq80entry:81 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__W, <8 x i64> %__X, <8 x i64> %__Y)82 %1 = bitcast i8 %__M to <8 x i1>83 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> %__W84 ret <8 x i64> %285}86 87define <8 x i64> @test_mm512_maskz_madd52lo_epu64(i8 zeroext %__M, <8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z) {88; X86-LABEL: test_mm512_maskz_madd52lo_epu64:89; X86: # %bb.0: # %entry90; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax91; X86-NEXT: kmovw %eax, %k192; X86-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z}93; X86-NEXT: retl94;95; X64-LABEL: test_mm512_maskz_madd52lo_epu64:96; X64: # %bb.0: # %entry97; X64-NEXT: kmovw %edi, %k198; X64-NEXT: vpmadd52luq %zmm2, %zmm1, %zmm0 {%k1} {z}99; X64-NEXT: retq100entry:101 %0 = tail call <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64> %__X, <8 x i64> %__Y, <8 x i64> %__Z)102 %1 = bitcast i8 %__M to <8 x i1>103 %2 = select <8 x i1> %1, <8 x i64> %0, <8 x i64> zeroinitializer104 ret <8 x i64> %2105}106 107declare <8 x i64> @llvm.x86.avx512.vpmadd52h.uq.512(<8 x i64>, <8 x i64>, <8 x i64>)108declare <8 x i64> @llvm.x86.avx512.vpmadd52l.uq.512(<8 x i64>, <8 x i64>, <8 x i64>)109