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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi2 | FileCheck %s --check-prefixes=CHECK,X863; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi2 -| FileCheck %s --check-prefixes=CHECK,X644 5define <8 x i64> @avx512_funnel_shift_q_512(<8 x i64> %a0, <8 x i64> %a1) {6; X86-LABEL: avx512_funnel_shift_q_512:7; X86: # %bb.0:8; X86-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm09; X86-NEXT: retl10;11; X64-LABEL: avx512_funnel_shift_q_512:12; X64: # %bb.0:13; X64-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm014; X64-NEXT: retq15 %1 = shl <8 x i64> %a0, <i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33>16 %2 = lshr <8 x i64> %a1, <i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31>17 %3 = or <8 x i64> %1, %218 ret <8 x i64> %319}20 21define <8 x i64> @avx512_funnel_shift_q_512_splat(<8 x i64> %a0, <8 x i64> %a1) {22; CHECK-LABEL: avx512_funnel_shift_q_512_splat:23; CHECK: # %bb.0:24; CHECK-NEXT: vpshldq $31, %zmm1, %zmm0, %zmm025; CHECK-NEXT: ret{{[l|q]}}26 %1 = shl <8 x i64> %a0, <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>27 %2 = lshr <8 x i64> %a1, <i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33>28 %3 = or <8 x i64> %1, %229 ret <8 x i64> %330}31 32define <16 x i32> @avx512_funnel_shift_d_512(<16 x i32> %a0, <16 x i32> %a1) {33; X86-LABEL: avx512_funnel_shift_d_512:34; X86: # %bb.0:35; X86-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm036; X86-NEXT: retl37;38; X64-LABEL: avx512_funnel_shift_d_512:39; X64: # %bb.0:40; X64-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm041; X64-NEXT: retq42 %1 = shl <16 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17>43 %2 = lshr <16 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15>44 %3 = or <16 x i32> %1, %245 ret <16 x i32> %346}47 48define <16 x i32> @avx512_funnel_shift_d_512_splat(<16 x i32> %a0, <16 x i32> %a1) {49; CHECK-LABEL: avx512_funnel_shift_d_512_splat:50; CHECK: # %bb.0:51; CHECK-NEXT: vpshldd $15, %zmm1, %zmm0, %zmm052; CHECK-NEXT: ret{{[l|q]}}53 %1 = shl <16 x i32> %a0, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>54 %2 = lshr <16 x i32> %a1, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>55 %3 = or <16 x i32> %1, %256 ret <16 x i32> %357}58 59define <32 x i16> @avx512_funnel_shift_w_512(<32 x i16> %a0, <32 x i16> %a1) {60; X86-LABEL: avx512_funnel_shift_w_512:61; X86: # %bb.0:62; X86-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm063; X86-NEXT: retl64;65; X64-LABEL: avx512_funnel_shift_w_512:66; X64: # %bb.0:67; X64-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm068; X64-NEXT: retq69 %1 = shl <32 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>70 %2 = lshr <32 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>71 %3 = or <32 x i16> %1, %272 ret <32 x i16> %373}74 75define <32 x i16> @avx512_funnel_shift_w_512_splat(<32 x i16> %a0, <32 x i16> %a1) {76; CHECK-LABEL: avx512_funnel_shift_w_512_splat:77; CHECK: # %bb.0:78; CHECK-NEXT: vpshldw $7, %zmm1, %zmm0, %zmm079; CHECK-NEXT: ret{{[l|q]}}80 %1 = shl <32 x i16> %a0, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>81 %2 = lshr <32 x i16> %a1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>82 %3 = or <32 x i16> %1, %283 ret <32 x i16> %384}85 86 87