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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s3; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512cd,+avx512vl | FileCheck %s4 5define <2 x i64> @test_mm_broadcastmb_epi64(<2 x i64> %a, <2 x i64> %b) {6; CHECK-LABEL: test_mm_broadcastmb_epi64:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k09; CHECK-NEXT: vpbroadcastmb2q %k0, %xmm010; CHECK-NEXT: ret{{[l|q]}}11entry:12 %0 = bitcast <2 x i64> %a to <4 x i32>13 %1 = bitcast <2 x i64> %b to <4 x i32>14 %2 = icmp eq <4 x i32> %0, %115 %3 = shufflevector <4 x i1> %2, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>16 %4 = bitcast <8 x i1> %3 to i817 %conv.i = zext i8 %4 to i6418 %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 019 %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer20 ret <2 x i64> %vecinit1.i.i21}22 23define <4 x i64> @test_mm256_broadcastmb_epi64(<4 x i64> %a, <4 x i64> %b) {24; CHECK-LABEL: test_mm256_broadcastmb_epi64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k027; CHECK-NEXT: vpbroadcastmb2q %k0, %ymm028; CHECK-NEXT: ret{{[l|q]}}29entry:30 %0 = icmp eq <4 x i64> %a, %b31 %1 = shufflevector <4 x i1> %0, <4 x i1> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>32 %2 = bitcast <8 x i1> %1 to i833 %conv.i = zext i8 %2 to i6434 %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 035 %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer36 ret <4 x i64> %vecinit3.i.i37}38 39define <2 x i64> @test_mm_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) {40; CHECK-LABEL: test_mm_broadcastmw_epi32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k043; CHECK-NEXT: vpbroadcastmw2d %k0, %xmm044; CHECK-NEXT: vzeroupper45; CHECK-NEXT: ret{{[l|q]}}46entry:47 %0 = bitcast <8 x i64> %a to <16 x i32>48 %1 = bitcast <8 x i64> %b to <16 x i32>49 %2 = icmp eq <16 x i32> %0, %150 %3 = bitcast <16 x i1> %2 to i1651 %conv.i = zext i16 %3 to i3252 %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 053 %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer54 %4 = bitcast <4 x i32> %vecinit3.i.i to <2 x i64>55 ret <2 x i64> %456}57 58define <4 x i64> @test_mm256_broadcastmw_epi32(<8 x i64> %a, <8 x i64> %b) {59; CHECK-LABEL: test_mm256_broadcastmw_epi32:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k062; CHECK-NEXT: vpbroadcastmw2d %k0, %ymm063; CHECK-NEXT: ret{{[l|q]}}64entry:65 %0 = bitcast <8 x i64> %a to <16 x i32>66 %1 = bitcast <8 x i64> %b to <16 x i32>67 %2 = icmp eq <16 x i32> %0, %168 %3 = bitcast <16 x i1> %2 to i1669 %conv.i = zext i16 %3 to i3270 %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 071 %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer72 %4 = bitcast <8 x i32> %vecinit7.i.i to <4 x i64>73 ret <4 x i64> %474}75 76 77