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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2,egpr --show-mc-encoding | FileCheck %s --check-prefixes=EGPR4 5define i64 @bzhi64(i64 %x, i64 %y) {6; CHECK-LABEL: bzhi64:7; CHECK: # %bb.0:8; CHECK-NEXT: bzhiq %rsi, %rdi, %rax9; CHECK-NEXT: retq10;11; EGPR-LABEL: bzhi64:12; EGPR: # %bb.0:13; EGPR-NEXT: bzhiq %rsi, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc8,0xf5,0xc7]14; EGPR-NEXT: retq # encoding: [0xc3]15 %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)16 ret i64 %tmp17}18 19define i64 @bzhi64_load(ptr %x, i64 %y) {20; CHECK-LABEL: bzhi64_load:21; CHECK: # %bb.0:22; CHECK-NEXT: bzhiq %rsi, (%rdi), %rax23; CHECK-NEXT: retq24;25; EGPR-LABEL: bzhi64_load:26; EGPR: # %bb.0:27; EGPR-NEXT: bzhiq %rsi, (%rdi), %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc8,0xf5,0x07]28; EGPR-NEXT: retq # encoding: [0xc3]29 %x1 = load i64, ptr %x30 %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x1, i64 %y)31 ret i64 %tmp32}33 34declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)35 36define i64 @pdep64(i64 %x, i64 %y) {37; CHECK-LABEL: pdep64:38; CHECK: # %bb.0:39; CHECK-NEXT: pdepq %rsi, %rdi, %rax40; CHECK-NEXT: retq41;42; EGPR-LABEL: pdep64:43; EGPR: # %bb.0:44; EGPR-NEXT: pdepq %rsi, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc3,0xf5,0xc6]45; EGPR-NEXT: retq # encoding: [0xc3]46 %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)47 ret i64 %tmp48}49 50define i64 @pdep64_load(i64 %x, ptr %y) {51; CHECK-LABEL: pdep64_load:52; CHECK: # %bb.0:53; CHECK-NEXT: pdepq (%rsi), %rdi, %rax54; CHECK-NEXT: retq55;56; EGPR-LABEL: pdep64_load:57; EGPR: # %bb.0:58; EGPR-NEXT: pdepq (%rsi), %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc3,0xf5,0x06]59; EGPR-NEXT: retq # encoding: [0xc3]60 %y1 = load i64, ptr %y61 %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y1)62 ret i64 %tmp63}64 65define i64 @pdep64_anyext(i32 %x) {66; CHECK-LABEL: pdep64_anyext:67; CHECK: # %bb.0:68; CHECK-NEXT: # kill: def $edi killed $edi def $rdi69; CHECK-NEXT: movabsq $6148914691236517205, %rax # imm = 0x555555555555555570; CHECK-NEXT: pdepq %rax, %rdi, %rax71; CHECK-NEXT: retq72;73; EGPR-LABEL: pdep64_anyext:74; EGPR: # %bb.0:75; EGPR-NEXT: # kill: def $edi killed $edi def $rdi76; EGPR-NEXT: movabsq $6148914691236517205, %rax # encoding: [0x48,0xb8,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55]77; EGPR-NEXT: # imm = 0x555555555555555578; EGPR-NEXT: pdepq %rax, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc3,0xf5,0xc0]79; EGPR-NEXT: retq # encoding: [0xc3]80 %x1 = sext i32 %x to i6481 %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x1, i64 6148914691236517205)82 ret i64 %tmp83}84 85declare i64 @llvm.x86.bmi.pdep.64(i64, i64)86 87define i64 @pext64(i64 %x, i64 %y) {88; CHECK-LABEL: pext64:89; CHECK: # %bb.0:90; CHECK-NEXT: pextq %rsi, %rdi, %rax91; CHECK-NEXT: retq92;93; EGPR-LABEL: pext64:94; EGPR: # %bb.0:95; EGPR-NEXT: pextq %rsi, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc2,0xf5,0xc6]96; EGPR-NEXT: retq # encoding: [0xc3]97 %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)98 ret i64 %tmp99}100 101define i64 @pext64_load(i64 %x, ptr %y) {102; CHECK-LABEL: pext64_load:103; CHECK: # %bb.0:104; CHECK-NEXT: pextq (%rsi), %rdi, %rax105; CHECK-NEXT: retq106;107; EGPR-LABEL: pext64_load:108; EGPR: # %bb.0:109; EGPR-NEXT: pextq (%rsi), %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc2,0xf5,0x06]110; EGPR-NEXT: retq # encoding: [0xc3]111 %y1 = load i64, ptr %y112 %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y1)113 ret i64 %tmp114}115 116define i64 @pext64_knownbits(i64 %x, i64 %y) {117; CHECK-LABEL: pext64_knownbits:118; CHECK: # %bb.0:119; CHECK-NEXT: movabsq $6148914691236517205, %rax # imm = 0x5555555555555555120; CHECK-NEXT: pextq %rax, %rdi, %rax121; CHECK-NEXT: retq122;123; EGPR-LABEL: pext64_knownbits:124; EGPR: # %bb.0:125; EGPR-NEXT: movabsq $6148914691236517205, %rax # encoding: [0x48,0xb8,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55]126; EGPR-NEXT: # imm = 0x5555555555555555127; EGPR-NEXT: pextq %rax, %rdi, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xc2,0xf5,0xc0]128; EGPR-NEXT: retq # encoding: [0xc3]129 %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 6148914691236517205)130 %tmp2 = and i64 %tmp, 4294967295131 ret i64 %tmp2132}133 134declare i64 @llvm.x86.bmi.pext.64(i64, i64)135 136define i64 @mulx64(i64 %x, i64 %y, ptr %p) {137; CHECK-LABEL: mulx64:138; CHECK: # %bb.0:139; CHECK-NEXT: movq %rdx, %rcx140; CHECK-NEXT: movq %rdi, %rdx141; CHECK-NEXT: mulxq %rsi, %rax, %rdx142; CHECK-NEXT: movq %rdx, (%rcx)143; CHECK-NEXT: retq144;145; EGPR-LABEL: mulx64:146; EGPR: # %bb.0:147; EGPR-NEXT: movq %rdx, %rcx # encoding: [0x48,0x89,0xd1]148; EGPR-NEXT: movq %rdi, %rdx # encoding: [0x48,0x89,0xfa]149; EGPR-NEXT: mulxq %rsi, %rax, %rdx # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfb,0xf6,0xd6]150; EGPR-NEXT: movq %rdx, (%rcx) # encoding: [0x48,0x89,0x11]151; EGPR-NEXT: retq # encoding: [0xc3]152 %x1 = zext i64 %x to i128153 %y1 = zext i64 %y to i128154 %r1 = mul i128 %x1, %y1155 %h1 = lshr i128 %r1, 64156 %h = trunc i128 %h1 to i64157 %l = trunc i128 %r1 to i64158 store i64 %h, ptr %p159 ret i64 %l160}161 162define i64 @mulx64_load(i64 %x, ptr %y, ptr %p) {163; CHECK-LABEL: mulx64_load:164; CHECK: # %bb.0:165; CHECK-NEXT: movq %rdx, %rcx166; CHECK-NEXT: movq %rdi, %rdx167; CHECK-NEXT: mulxq (%rsi), %rax, %rdx168; CHECK-NEXT: movq %rdx, (%rcx)169; CHECK-NEXT: retq170;171; EGPR-LABEL: mulx64_load:172; EGPR: # %bb.0:173; EGPR-NEXT: movq %rdx, %rcx # encoding: [0x48,0x89,0xd1]174; EGPR-NEXT: movq %rdi, %rdx # encoding: [0x48,0x89,0xfa]175; EGPR-NEXT: mulxq (%rsi), %rax, %rdx # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfb,0xf6,0x16]176; EGPR-NEXT: movq %rdx, (%rcx) # encoding: [0x48,0x89,0x11]177; EGPR-NEXT: retq # encoding: [0xc3]178 %y1 = load i64, ptr %y179 %x2 = zext i64 %x to i128180 %y2 = zext i64 %y1 to i128181 %r1 = mul i128 %x2, %y2182 %h1 = lshr i128 %r1, 64183 %h = trunc i128 %h1 to i64184 %l = trunc i128 %r1 to i64185 store i64 %h, ptr %p186 ret i64 %l187}188