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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE25; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE26; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX27; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX28 9define i32 @PR15215_bad(<4 x i32> %input) nounwind {10; X86-LABEL: PR15215_bad:11; X86:       # %bb.0: # %entry12; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax13; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %edx14; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %ecx15; X86-NEXT:    movb {{[0-9]+}}(%esp), %ah16; X86-NEXT:    shlb $3, %ah17; X86-NEXT:    andb $1, %cl18; X86-NEXT:    shlb $2, %cl19; X86-NEXT:    orb %ah, %cl20; X86-NEXT:    addb %dl, %dl21; X86-NEXT:    andb $1, %al22; X86-NEXT:    orb %dl, %al23; X86-NEXT:    andb $3, %al24; X86-NEXT:    orb %cl, %al25; X86-NEXT:    movzbl %al, %eax26; X86-NEXT:    andl $15, %eax27; X86-NEXT:    retl28;29; X64-LABEL: PR15215_bad:30; X64:       # %bb.0: # %entry31; X64-NEXT:    shlb $3, %cl32; X64-NEXT:    andb $1, %dl33; X64-NEXT:    shlb $2, %dl34; X64-NEXT:    orb %cl, %dl35; X64-NEXT:    addb %sil, %sil36; X64-NEXT:    andb $1, %dil37; X64-NEXT:    orb %sil, %dil38; X64-NEXT:    andb $3, %dil39; X64-NEXT:    orb %dl, %dil40; X64-NEXT:    movzbl %dil, %eax41; X64-NEXT:    andl $15, %eax42; X64-NEXT:    retq43;44; SSE2-LABEL: PR15215_bad:45; SSE2:       # %bb.0: # %entry46; SSE2-NEXT:    pslld $31, %xmm047; SSE2-NEXT:    movmskps %xmm0, %eax48; SSE2-NEXT:    ret{{[l|q]}}49;50; AVX2-LABEL: PR15215_bad:51; AVX2:       # %bb.0: # %entry52; AVX2-NEXT:    vpslld $31, %xmm0, %xmm053; AVX2-NEXT:    vmovmskps %xmm0, %eax54; AVX2-NEXT:    ret{{[l|q]}}55entry:56  %0 = trunc <4 x i32> %input to <4 x i1>57  %1 = bitcast <4 x i1> %0 to i458  %2 = zext i4 %1 to i3259  ret i32 %260}61 62define i32 @PR15215_good(<4 x i32> %input) nounwind {63; X86-LABEL: PR15215_good:64; X86:       # %bb.0: # %entry65; X86-NEXT:    pushl %esi66; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax67; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx68; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx69; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi70; X86-NEXT:    andl $1, %esi71; X86-NEXT:    andl $1, %edx72; X86-NEXT:    andl $1, %ecx73; X86-NEXT:    andl $1, %eax74; X86-NEXT:    leal (%esi,%edx,2), %edx75; X86-NEXT:    leal (%edx,%ecx,4), %ecx76; X86-NEXT:    leal (%ecx,%eax,8), %eax77; X86-NEXT:    popl %esi78; X86-NEXT:    retl79;80; X64-LABEL: PR15215_good:81; X64:       # %bb.0: # %entry82; X64-NEXT:    # kill: def $ecx killed $ecx def $rcx83; X64-NEXT:    # kill: def $edx killed $edx def $rdx84; X64-NEXT:    # kill: def $esi killed $esi def $rsi85; X64-NEXT:    # kill: def $edi killed $edi def $rdi86; X64-NEXT:    andl $1, %edi87; X64-NEXT:    andl $1, %esi88; X64-NEXT:    andl $1, %edx89; X64-NEXT:    andl $1, %ecx90; X64-NEXT:    leal (%rdi,%rsi,2), %eax91; X64-NEXT:    leal (%rax,%rdx,4), %eax92; X64-NEXT:    leal (%rax,%rcx,8), %eax93; X64-NEXT:    retq94;95; SSE2-LABEL: PR15215_good:96; SSE2:       # %bb.0: # %entry97; SSE2-NEXT:    pslld $31, %xmm098; SSE2-NEXT:    movmskps %xmm0, %eax99; SSE2-NEXT:    ret{{[l|q]}}100;101; AVX2-LABEL: PR15215_good:102; AVX2:       # %bb.0: # %entry103; AVX2-NEXT:    vpslld $31, %xmm0, %xmm0104; AVX2-NEXT:    vmovmskps %xmm0, %eax105; AVX2-NEXT:    ret{{[l|q]}}106entry:107  %0 = trunc <4 x i32> %input to <4 x i1>108  %1 = extractelement <4 x i1> %0, i32 0109  %e1 = select i1 %1, i32 1, i32 0110  %2 = extractelement <4 x i1> %0, i32 1111  %e2 = select i1 %2, i32 2, i32 0112  %3 = extractelement <4 x i1> %0, i32 2113  %e3 = select i1 %3, i32 4, i32 0114  %4 = extractelement <4 x i1> %0, i32 3115  %e4 = select i1 %4, i32 8, i32 0116  %5 = or i32 %e1, %e2117  %6 = or i32 %5, %e3118  %7 = or i32 %6, %e4119  ret i32 %7120}121