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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE-32 --check-prefix=SSE2-323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE-64 --check-prefix=SSE2-644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE-32 --check-prefix=SSE41-325; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE-64 --check-prefix=SSE41-646; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX1-327; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX1-648; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX2-329; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX2-6410 11define <2 x double> @test_buildvector_v2f64(double %a0, double %a1) {12; SSE-32-LABEL: test_buildvector_v2f64:13; SSE-32: # %bb.0:14; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm015; SSE-32-NEXT: retl16;17; SSE-64-LABEL: test_buildvector_v2f64:18; SSE-64: # %bb.0:19; SSE-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]20; SSE-64-NEXT: retq21;22; AVX-32-LABEL: test_buildvector_v2f64:23; AVX-32: # %bb.0:24; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm025; AVX-32-NEXT: retl26;27; AVX-64-LABEL: test_buildvector_v2f64:28; AVX-64: # %bb.0:29; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]30; AVX-64-NEXT: retq31 %ins0 = insertelement <2 x double> undef, double %a0, i32 032 %ins1 = insertelement <2 x double> %ins0, double %a1, i32 133 ret <2 x double> %ins134}35 36define <4 x float> @test_buildvector_v4f32(float %a0, float %a1, float %a2, float %a3) {37; SSE-32-LABEL: test_buildvector_v4f32:38; SSE-32: # %bb.0:39; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm040; SSE-32-NEXT: retl41;42; SSE2-64-LABEL: test_buildvector_v4f32:43; SSE2-64: # %bb.0:44; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]45; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]46; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]47; SSE2-64-NEXT: retq48;49; SSE41-64-LABEL: test_buildvector_v4f32:50; SSE41-64: # %bb.0:51; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]52; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]53; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]54; SSE41-64-NEXT: retq55;56; AVX-32-LABEL: test_buildvector_v4f32:57; AVX-32: # %bb.0:58; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm059; AVX-32-NEXT: retl60;61; AVX-64-LABEL: test_buildvector_v4f32:62; AVX-64: # %bb.0:63; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]64; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]65; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]66; AVX-64-NEXT: retq67 %ins0 = insertelement <4 x float> undef, float %a0, i32 068 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 169 %ins2 = insertelement <4 x float> %ins1, float %a2, i32 270 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 371 ret <4 x float> %ins372}73 74define <2 x i64> @test_buildvector_v2i64(i64 %a0, i64 %a1) {75; SSE-32-LABEL: test_buildvector_v2i64:76; SSE-32: # %bb.0:77; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm078; SSE-32-NEXT: retl79;80; SSE-64-LABEL: test_buildvector_v2i64:81; SSE-64: # %bb.0:82; SSE-64-NEXT: movq %rsi, %xmm183; SSE-64-NEXT: movq %rdi, %xmm084; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]85; SSE-64-NEXT: retq86;87; AVX-32-LABEL: test_buildvector_v2i64:88; AVX-32: # %bb.0:89; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm090; AVX-32-NEXT: retl91;92; AVX-64-LABEL: test_buildvector_v2i64:93; AVX-64: # %bb.0:94; AVX-64-NEXT: vmovq %rsi, %xmm095; AVX-64-NEXT: vmovq %rdi, %xmm196; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]97; AVX-64-NEXT: retq98 %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 099 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1100 ret <2 x i64> %ins1101}102 103define <4 x i32> @test_buildvector_v4i32(i32 %f0, i32 %f1, i32 %f2, i32 %f3) {104; SSE-32-LABEL: test_buildvector_v4i32:105; SSE-32: # %bb.0:106; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0107; SSE-32-NEXT: retl108;109; SSE2-64-LABEL: test_buildvector_v4i32:110; SSE2-64: # %bb.0:111; SSE2-64-NEXT: movd %ecx, %xmm0112; SSE2-64-NEXT: movd %edx, %xmm1113; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]114; SSE2-64-NEXT: movd %esi, %xmm2115; SSE2-64-NEXT: movd %edi, %xmm0116; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]117; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]118; SSE2-64-NEXT: retq119;120; SSE41-64-LABEL: test_buildvector_v4i32:121; SSE41-64: # %bb.0:122; SSE41-64-NEXT: movd %edi, %xmm0123; SSE41-64-NEXT: pinsrd $1, %esi, %xmm0124; SSE41-64-NEXT: pinsrd $2, %edx, %xmm0125; SSE41-64-NEXT: pinsrd $3, %ecx, %xmm0126; SSE41-64-NEXT: retq127;128; AVX-32-LABEL: test_buildvector_v4i32:129; AVX-32: # %bb.0:130; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0131; AVX-32-NEXT: retl132;133; AVX-64-LABEL: test_buildvector_v4i32:134; AVX-64: # %bb.0:135; AVX-64-NEXT: vmovd %edi, %xmm0136; AVX-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0137; AVX-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0138; AVX-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0139; AVX-64-NEXT: retq140 %ins0 = insertelement <4 x i32> undef, i32 %f0, i32 0141 %ins1 = insertelement <4 x i32> %ins0, i32 %f1, i32 1142 %ins2 = insertelement <4 x i32> %ins1, i32 %f2, i32 2143 %ins3 = insertelement <4 x i32> %ins2, i32 %f3, i32 3144 ret <4 x i32> %ins3145}146 147define <8 x i16> @test_buildvector_v8i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) {148; SSE2-32-LABEL: test_buildvector_v8i16:149; SSE2-32: # %bb.0:150; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero151; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero152; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]153; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero154; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero155; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]156; SSE2-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]157; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero158; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero159; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]160; SSE2-32-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero161; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero162; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]163; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]164; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]165; SSE2-32-NEXT: retl166;167; SSE2-64-LABEL: test_buildvector_v8i16:168; SSE2-64: # %bb.0:169; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero170; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero171; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]172; SSE2-64-NEXT: movd %r9d, %xmm0173; SSE2-64-NEXT: movd %r8d, %xmm2174; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]175; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]176; SSE2-64-NEXT: movd %ecx, %xmm0177; SSE2-64-NEXT: movd %edx, %xmm1178; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]179; SSE2-64-NEXT: movd %esi, %xmm3180; SSE2-64-NEXT: movd %edi, %xmm0181; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]182; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]183; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]184; SSE2-64-NEXT: retq185;186; SSE41-32-LABEL: test_buildvector_v8i16:187; SSE41-32: # %bb.0:188; SSE41-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero189; SSE41-32-NEXT: pinsrw $1, {{[0-9]+}}(%esp), %xmm0190; SSE41-32-NEXT: pinsrw $2, {{[0-9]+}}(%esp), %xmm0191; SSE41-32-NEXT: pinsrw $3, {{[0-9]+}}(%esp), %xmm0192; SSE41-32-NEXT: pinsrw $4, {{[0-9]+}}(%esp), %xmm0193; SSE41-32-NEXT: pinsrw $5, {{[0-9]+}}(%esp), %xmm0194; SSE41-32-NEXT: pinsrw $6, {{[0-9]+}}(%esp), %xmm0195; SSE41-32-NEXT: pinsrw $7, {{[0-9]+}}(%esp), %xmm0196; SSE41-32-NEXT: retl197;198; SSE41-64-LABEL: test_buildvector_v8i16:199; SSE41-64: # %bb.0:200; SSE41-64-NEXT: movd %edi, %xmm0201; SSE41-64-NEXT: pinsrw $1, %esi, %xmm0202; SSE41-64-NEXT: pinsrw $2, %edx, %xmm0203; SSE41-64-NEXT: pinsrw $3, %ecx, %xmm0204; SSE41-64-NEXT: pinsrw $4, %r8d, %xmm0205; SSE41-64-NEXT: pinsrw $5, %r9d, %xmm0206; SSE41-64-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0207; SSE41-64-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0208; SSE41-64-NEXT: retq209;210; AVX-32-LABEL: test_buildvector_v8i16:211; AVX-32: # %bb.0:212; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero213; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0214; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0215; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0216; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0217; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0218; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0219; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0220; AVX-32-NEXT: retl221;222; AVX-64-LABEL: test_buildvector_v8i16:223; AVX-64: # %bb.0:224; AVX-64-NEXT: vmovd %edi, %xmm0225; AVX-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0226; AVX-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0227; AVX-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0228; AVX-64-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0229; AVX-64-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0230; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0231; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0232; AVX-64-NEXT: retq233 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0234 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1235 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2236 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3237 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4238 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5239 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6240 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7241 ret <8 x i16> %ins7242}243 244define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) {245; SSE2-32-LABEL: test_buildvector_v16i8:246; SSE2-32: # %bb.0:247; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero248; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero249; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]250; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero251; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero252; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]253; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]254; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero255; SSE2-32-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero256; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]257; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero258; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero259; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]260; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3]261; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]262; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero263; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero264; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]265; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero266; SSE2-32-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero267; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]268; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]269; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero270; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero271; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]272; SSE2-32-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero273; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero274; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]275; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]276; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]277; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]278; SSE2-32-NEXT: retl279;280; SSE2-64-LABEL: test_buildvector_v16i8:281; SSE2-64: # %bb.0:282; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero283; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero284; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]285; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero286; SSE2-64-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero287; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]288; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]289; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero290; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero291; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]292; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero293; SSE2-64-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero294; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]295; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]296; SSE2-64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]297; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero298; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero299; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]300; SSE2-64-NEXT: movd %r9d, %xmm0301; SSE2-64-NEXT: movd %r8d, %xmm2302; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]303; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]304; SSE2-64-NEXT: movd %ecx, %xmm0305; SSE2-64-NEXT: movd %edx, %xmm1306; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]307; SSE2-64-NEXT: movd %esi, %xmm4308; SSE2-64-NEXT: movd %edi, %xmm0309; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]310; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]311; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]312; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]313; SSE2-64-NEXT: retq314;315; SSE41-32-LABEL: test_buildvector_v16i8:316; SSE41-32: # %bb.0:317; SSE41-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero318; SSE41-32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0319; SSE41-32-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0320; SSE41-32-NEXT: pinsrb $3, {{[0-9]+}}(%esp), %xmm0321; SSE41-32-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0322; SSE41-32-NEXT: pinsrb $5, {{[0-9]+}}(%esp), %xmm0323; SSE41-32-NEXT: pinsrb $6, {{[0-9]+}}(%esp), %xmm0324; SSE41-32-NEXT: pinsrb $7, {{[0-9]+}}(%esp), %xmm0325; SSE41-32-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0326; SSE41-32-NEXT: pinsrb $9, {{[0-9]+}}(%esp), %xmm0327; SSE41-32-NEXT: pinsrb $10, {{[0-9]+}}(%esp), %xmm0328; SSE41-32-NEXT: pinsrb $11, {{[0-9]+}}(%esp), %xmm0329; SSE41-32-NEXT: pinsrb $12, {{[0-9]+}}(%esp), %xmm0330; SSE41-32-NEXT: pinsrb $13, {{[0-9]+}}(%esp), %xmm0331; SSE41-32-NEXT: pinsrb $14, {{[0-9]+}}(%esp), %xmm0332; SSE41-32-NEXT: pinsrb $15, {{[0-9]+}}(%esp), %xmm0333; SSE41-32-NEXT: retl334;335; SSE41-64-LABEL: test_buildvector_v16i8:336; SSE41-64: # %bb.0:337; SSE41-64-NEXT: movd %edi, %xmm0338; SSE41-64-NEXT: pinsrb $1, %esi, %xmm0339; SSE41-64-NEXT: pinsrb $2, %edx, %xmm0340; SSE41-64-NEXT: pinsrb $3, %ecx, %xmm0341; SSE41-64-NEXT: pinsrb $4, %r8d, %xmm0342; SSE41-64-NEXT: pinsrb $5, %r9d, %xmm0343; SSE41-64-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0344; SSE41-64-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0345; SSE41-64-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0346; SSE41-64-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0347; SSE41-64-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0348; SSE41-64-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0349; SSE41-64-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0350; SSE41-64-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0351; SSE41-64-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0352; SSE41-64-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0353; SSE41-64-NEXT: retq354;355; AVX-32-LABEL: test_buildvector_v16i8:356; AVX-32: # %bb.0:357; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero358; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0359; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0360; AVX-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0361; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0362; AVX-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0363; AVX-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0364; AVX-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0365; AVX-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0366; AVX-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0367; AVX-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0368; AVX-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0369; AVX-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0370; AVX-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0371; AVX-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0372; AVX-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0373; AVX-32-NEXT: retl374;375; AVX-64-LABEL: test_buildvector_v16i8:376; AVX-64: # %bb.0:377; AVX-64-NEXT: vmovd %edi, %xmm0378; AVX-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0379; AVX-64-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0380; AVX-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0381; AVX-64-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0382; AVX-64-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0383; AVX-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0384; AVX-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0385; AVX-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0386; AVX-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0387; AVX-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0388; AVX-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0389; AVX-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0390; AVX-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0391; AVX-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0392; AVX-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0393; AVX-64-NEXT: retq394 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0395 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1396 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2397 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3398 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4399 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5400 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6401 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7402 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8403 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9404 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10405 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11406 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12407 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13408 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14409 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15410 ret <16 x i8> %ins15411}412 413; build vectors where integers operands are split (typically via legalization)414 415define <4 x i32> @test_buildvector_v2i64_split_v4i32(i64 %a0, i64 %a1) nounwind {416; SSE-32-LABEL: test_buildvector_v2i64_split_v4i32:417; SSE-32: # %bb.0:418; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0419; SSE-32-NEXT: retl420;421; SSE-64-LABEL: test_buildvector_v2i64_split_v4i32:422; SSE-64: # %bb.0:423; SSE-64-NEXT: movq %rsi, %xmm1424; SSE-64-NEXT: movq %rdi, %xmm0425; SSE-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]426; SSE-64-NEXT: retq427;428; AVX-32-LABEL: test_buildvector_v2i64_split_v4i32:429; AVX-32: # %bb.0:430; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0431; AVX-32-NEXT: retl432;433; AVX-64-LABEL: test_buildvector_v2i64_split_v4i32:434; AVX-64: # %bb.0:435; AVX-64-NEXT: vmovq %rsi, %xmm0436; AVX-64-NEXT: vmovq %rdi, %xmm1437; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]438; AVX-64-NEXT: retq439 %a0.lo = trunc i64 %a0 to i32440 %a1.lo = trunc i64 %a1 to i32441 %a0.shr = lshr i64 %a0, 32442 %a1.shr = lshr i64 %a1, 32443 %a0.hi = trunc i64 %a0.shr to i32444 %a1.hi = trunc i64 %a1.shr to i32445 %v0 = insertelement <4 x i32> poison, i32 %a0.lo, i64 0446 %v1 = insertelement <4 x i32> %v0, i32 %a0.hi, i64 1447 %v2 = insertelement <4 x i32> %v1, i32 %a1.lo, i64 2448 %v3 = insertelement <4 x i32> %v2, i32 %a1.hi, i64 3449 ret <4 x i32> %v3450}451 452define <8 x i16> @test_buildvector_v4i32_split_v8i16(i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind {453; SSE-32-LABEL: test_buildvector_v4i32_split_v8i16:454; SSE-32: # %bb.0:455; SSE-32-NEXT: movups {{[0-9]+}}(%esp), %xmm0456; SSE-32-NEXT: retl457;458; SSE2-64-LABEL: test_buildvector_v4i32_split_v8i16:459; SSE2-64: # %bb.0:460; SSE2-64-NEXT: movd %ecx, %xmm0461; SSE2-64-NEXT: movd %edx, %xmm1462; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]463; SSE2-64-NEXT: movd %esi, %xmm2464; SSE2-64-NEXT: movd %edi, %xmm0465; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]466; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]467; SSE2-64-NEXT: retq468;469; SSE41-64-LABEL: test_buildvector_v4i32_split_v8i16:470; SSE41-64: # %bb.0:471; SSE41-64-NEXT: movd %edi, %xmm0472; SSE41-64-NEXT: pinsrd $1, %esi, %xmm0473; SSE41-64-NEXT: pinsrd $2, %edx, %xmm0474; SSE41-64-NEXT: pinsrd $3, %ecx, %xmm0475; SSE41-64-NEXT: retq476;477; AVX-32-LABEL: test_buildvector_v4i32_split_v8i16:478; AVX-32: # %bb.0:479; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0480; AVX-32-NEXT: retl481;482; AVX-64-LABEL: test_buildvector_v4i32_split_v8i16:483; AVX-64: # %bb.0:484; AVX-64-NEXT: vmovd %edi, %xmm0485; AVX-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0486; AVX-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0487; AVX-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0488; AVX-64-NEXT: retq489 %a0.lo = trunc i32 %a0 to i16490 %a1.lo = trunc i32 %a1 to i16491 %a2.lo = trunc i32 %a2 to i16492 %a3.lo = trunc i32 %a3 to i16493 %a0.shr = lshr i32 %a0, 16494 %a1.shr = lshr i32 %a1, 16495 %a2.shr = lshr i32 %a2, 16496 %a3.shr = lshr i32 %a3, 16497 %a0.hi = trunc i32 %a0.shr to i16498 %a1.hi = trunc i32 %a1.shr to i16499 %a2.hi = trunc i32 %a2.shr to i16500 %a3.hi = trunc i32 %a3.shr to i16501 %v0 = insertelement <8 x i16> poison, i16 %a0.lo, i64 0502 %v1 = insertelement <8 x i16> %v0, i16 %a0.hi, i64 1503 %v2 = insertelement <8 x i16> %v1, i16 %a1.lo, i64 2504 %v3 = insertelement <8 x i16> %v2, i16 %a1.hi, i64 3505 %v4 = insertelement <8 x i16> %v3, i16 %a2.lo, i64 4506 %v5 = insertelement <8 x i16> %v4, i16 %a2.hi, i64 5507 %v6 = insertelement <8 x i16> %v5, i16 %a3.lo, i64 6508 %v7 = insertelement <8 x i16> %v6, i16 %a3.hi, i64 7509 ret <8 x i16> %v7510}511 512define <16 x i8> @test_buildvector_v8i16_split_v16i8(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {513; SSE2-32-LABEL: test_buildvector_v8i16_split_v16i8:514; SSE2-32: # %bb.0:515; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero516; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero517; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]518; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero519; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero520; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]521; SSE2-32-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]522; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero523; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero524; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]525; SSE2-32-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero526; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero527; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]528; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]529; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]530; SSE2-32-NEXT: retl531;532; SSE2-64-LABEL: test_buildvector_v8i16_split_v16i8:533; SSE2-64: # %bb.0:534; SSE2-64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero535; SSE2-64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero536; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]537; SSE2-64-NEXT: movd %r9d, %xmm0538; SSE2-64-NEXT: movd %r8d, %xmm2539; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]540; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]541; SSE2-64-NEXT: movd %ecx, %xmm0542; SSE2-64-NEXT: movd %edx, %xmm1543; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]544; SSE2-64-NEXT: movd %esi, %xmm3545; SSE2-64-NEXT: movd %edi, %xmm0546; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]547; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]548; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]549; SSE2-64-NEXT: retq550;551; SSE41-32-LABEL: test_buildvector_v8i16_split_v16i8:552; SSE41-32: # %bb.0:553; SSE41-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero554; SSE41-32-NEXT: pinsrw $1, {{[0-9]+}}(%esp), %xmm0555; SSE41-32-NEXT: pinsrw $2, {{[0-9]+}}(%esp), %xmm0556; SSE41-32-NEXT: pinsrw $3, {{[0-9]+}}(%esp), %xmm0557; SSE41-32-NEXT: pinsrw $4, {{[0-9]+}}(%esp), %xmm0558; SSE41-32-NEXT: pinsrw $5, {{[0-9]+}}(%esp), %xmm0559; SSE41-32-NEXT: pinsrw $6, {{[0-9]+}}(%esp), %xmm0560; SSE41-32-NEXT: pinsrw $7, {{[0-9]+}}(%esp), %xmm0561; SSE41-32-NEXT: retl562;563; SSE41-64-LABEL: test_buildvector_v8i16_split_v16i8:564; SSE41-64: # %bb.0:565; SSE41-64-NEXT: movd %edi, %xmm0566; SSE41-64-NEXT: pinsrw $1, %esi, %xmm0567; SSE41-64-NEXT: pinsrw $2, %edx, %xmm0568; SSE41-64-NEXT: pinsrw $3, %ecx, %xmm0569; SSE41-64-NEXT: pinsrw $4, %r8d, %xmm0570; SSE41-64-NEXT: pinsrw $5, %r9d, %xmm0571; SSE41-64-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0572; SSE41-64-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0573; SSE41-64-NEXT: retq574;575; AVX-32-LABEL: test_buildvector_v8i16_split_v16i8:576; AVX-32: # %bb.0:577; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero578; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0579; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0580; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0581; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0582; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0583; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0584; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0585; AVX-32-NEXT: retl586;587; AVX-64-LABEL: test_buildvector_v8i16_split_v16i8:588; AVX-64: # %bb.0:589; AVX-64-NEXT: vmovd %edi, %xmm0590; AVX-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0591; AVX-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0592; AVX-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0593; AVX-64-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0594; AVX-64-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0595; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0596; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0597; AVX-64-NEXT: retq598 %a0.lo = trunc i16 %a0 to i8599 %a1.lo = trunc i16 %a1 to i8600 %a2.lo = trunc i16 %a2 to i8601 %a3.lo = trunc i16 %a3 to i8602 %a4.lo = trunc i16 %a4 to i8603 %a5.lo = trunc i16 %a5 to i8604 %a6.lo = trunc i16 %a6 to i8605 %a7.lo = trunc i16 %a7 to i8606 %a0.shr = lshr i16 %a0, 8607 %a1.shr = lshr i16 %a1, 8608 %a2.shr = lshr i16 %a2, 8609 %a3.shr = lshr i16 %a3, 8610 %a4.shr = lshr i16 %a4, 8611 %a5.shr = lshr i16 %a5, 8612 %a6.shr = lshr i16 %a6, 8613 %a7.shr = lshr i16 %a7, 8614 %a0.hi = trunc i16 %a0.shr to i8615 %a1.hi = trunc i16 %a1.shr to i8616 %a2.hi = trunc i16 %a2.shr to i8617 %a3.hi = trunc i16 %a3.shr to i8618 %a4.hi = trunc i16 %a4.shr to i8619 %a5.hi = trunc i16 %a5.shr to i8620 %a6.hi = trunc i16 %a6.shr to i8621 %a7.hi = trunc i16 %a7.shr to i8622 %v0 = insertelement <16 x i8> poison, i8 %a0.lo, i64 0623 %v1 = insertelement <16 x i8> %v0, i8 %a0.hi, i64 1624 %v2 = insertelement <16 x i8> %v1, i8 %a1.lo, i64 2625 %v3 = insertelement <16 x i8> %v2, i8 %a1.hi, i64 3626 %v4 = insertelement <16 x i8> %v3, i8 %a2.lo, i64 4627 %v5 = insertelement <16 x i8> %v4, i8 %a2.hi, i64 5628 %v6 = insertelement <16 x i8> %v5, i8 %a3.lo, i64 6629 %v7 = insertelement <16 x i8> %v6, i8 %a3.hi, i64 7630 %v8 = insertelement <16 x i8> %v7, i8 %a4.lo, i64 8631 %v9 = insertelement <16 x i8> %v8, i8 %a4.hi, i64 9632 %v10 = insertelement <16 x i8> %v9, i8 %a5.lo, i64 10633 %v11 = insertelement <16 x i8> %v10, i8 %a5.hi, i64 11634 %v12 = insertelement <16 x i8> %v11, i8 %a6.lo, i64 12635 %v13 = insertelement <16 x i8> %v12, i8 %a6.hi, i64 13636 %v14 = insertelement <16 x i8> %v13, i8 %a7.lo, i64 14637 %v15 = insertelement <16 x i8> %v14, i8 %a7.hi, i64 15638 ret <16 x i8> %v15639}640 641; build vectors of repeated elements642 643define <4 x float> @test_buildvector_4f32_2_var(float %a0, float %a1) {644; SSE2-32-LABEL: test_buildvector_4f32_2_var:645; SSE2-32: # %bb.0:646; SSE2-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero647; SSE2-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero648; SSE2-32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]649; SSE2-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero650; SSE2-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]651; SSE2-32-NEXT: retl652;653; SSE2-64-LABEL: test_buildvector_4f32_2_var:654; SSE2-64: # %bb.0:655; SSE2-64-NEXT: movaps %xmm1, %xmm2656; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]657; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]658; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]659; SSE2-64-NEXT: retq660;661; SSE41-32-LABEL: test_buildvector_4f32_2_var:662; SSE41-32: # %bb.0:663; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero664; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]665; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]666; SSE41-32-NEXT: retl667;668; SSE41-64-LABEL: test_buildvector_4f32_2_var:669; SSE41-64: # %bb.0:670; SSE41-64-NEXT: movaps %xmm0, %xmm2671; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[2,3]672; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0],xmm2[3]673; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm0[0]674; SSE41-64-NEXT: movaps %xmm2, %xmm0675; SSE41-64-NEXT: retq676;677; AVX-32-LABEL: test_buildvector_4f32_2_var:678; AVX-32: # %bb.0:679; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero680; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]681; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]682; AVX-32-NEXT: retl683;684; AVX-64-LABEL: test_buildvector_4f32_2_var:685; AVX-64: # %bb.0:686; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[2,3]687; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]688; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]689; AVX-64-NEXT: retq690 %v0 = insertelement <4 x float> poison, float %a0, i32 0691 %v1 = insertelement <4 x float> %v0, float %a1, i32 1692 %v2 = insertelement <4 x float> %v1, float %a1, i32 2693 %v3 = insertelement <4 x float> %v2, float %a0, i32 3694 ret <4 x float> %v3695}696 697define <4 x float> @test_buildvector_4f32_2_load(ptr %p0, ptr %p1) {698; SSE2-32-LABEL: test_buildvector_4f32_2_load:699; SSE2-32: # %bb.0:700; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax701; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx702; SSE2-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero703; SSE2-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero704; SSE2-32-NEXT: movaps %xmm1, %xmm2705; SSE2-32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]706; SSE2-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]707; SSE2-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]708; SSE2-32-NEXT: retl709;710; SSE2-64-LABEL: test_buildvector_4f32_2_load:711; SSE2-64: # %bb.0:712; SSE2-64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero713; SSE2-64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero714; SSE2-64-NEXT: movaps %xmm1, %xmm2715; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]716; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]717; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]718; SSE2-64-NEXT: retq719;720; SSE41-32-LABEL: test_buildvector_4f32_2_load:721; SSE41-32: # %bb.0:722; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax723; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx724; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero725; SSE41-32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero726; SSE41-32-NEXT: movaps %xmm2, %xmm0727; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]728; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]729; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]730; SSE41-32-NEXT: retl731;732; SSE41-64-LABEL: test_buildvector_4f32_2_load:733; SSE41-64: # %bb.0:734; SSE41-64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero735; SSE41-64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero736; SSE41-64-NEXT: movaps %xmm2, %xmm0737; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]738; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]739; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]740; SSE41-64-NEXT: retq741;742; AVX-32-LABEL: test_buildvector_4f32_2_load:743; AVX-32: # %bb.0:744; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax745; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx746; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero747; AVX-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero748; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]749; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]750; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]751; AVX-32-NEXT: retl752;753; AVX-64-LABEL: test_buildvector_4f32_2_load:754; AVX-64: # %bb.0:755; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero756; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero757; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]758; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]759; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]760; AVX-64-NEXT: retq761 %a0 = load float, ptr %p0762 %a1 = load float, ptr %p1763 %v0 = insertelement <4 x float> poison, float %a0, i32 0764 %v1 = insertelement <4 x float> %v0, float %a1, i32 1765 %v2 = insertelement <4 x float> %v1, float %a1, i32 2766 %v3 = insertelement <4 x float> %v2, float %a0, i32 3767 ret <4 x float> %v3768}769 770define <8 x i16> @test_buildvector_8i16_2_var(i16 %a0, i16 %a1) {771; SSE2-32-LABEL: test_buildvector_8i16_2_var:772; SSE2-32: # %bb.0:773; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero774; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero775; SSE2-32-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]776; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]777; SSE2-32-NEXT: movdqa %xmm2, %xmm1778; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]779; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]780; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]781; SSE2-32-NEXT: retl782;783; SSE2-64-LABEL: test_buildvector_8i16_2_var:784; SSE2-64: # %bb.0:785; SSE2-64-NEXT: movd %esi, %xmm1786; SSE2-64-NEXT: movd %edi, %xmm0787; SSE2-64-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]788; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]789; SSE2-64-NEXT: movdqa %xmm2, %xmm1790; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]791; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]792; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]793; SSE2-64-NEXT: retq794;795; SSE41-32-LABEL: test_buildvector_8i16_2_var:796; SSE41-32: # %bb.0:797; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax798; SSE41-32-NEXT: movd %eax, %xmm0799; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx800; SSE41-32-NEXT: pinsrw $1, %ecx, %xmm0801; SSE41-32-NEXT: pinsrw $2, %eax, %xmm0802; SSE41-32-NEXT: pinsrw $3, %eax, %xmm0803; SSE41-32-NEXT: pinsrw $4, %eax, %xmm0804; SSE41-32-NEXT: pinsrw $5, %eax, %xmm0805; SSE41-32-NEXT: pinsrw $6, %eax, %xmm0806; SSE41-32-NEXT: pinsrw $7, %ecx, %xmm0807; SSE41-32-NEXT: retl808;809; SSE41-64-LABEL: test_buildvector_8i16_2_var:810; SSE41-64: # %bb.0:811; SSE41-64-NEXT: movd %edi, %xmm0812; SSE41-64-NEXT: pinsrw $1, %esi, %xmm0813; SSE41-64-NEXT: pinsrw $2, %edi, %xmm0814; SSE41-64-NEXT: pinsrw $3, %edi, %xmm0815; SSE41-64-NEXT: pinsrw $4, %edi, %xmm0816; SSE41-64-NEXT: pinsrw $5, %edi, %xmm0817; SSE41-64-NEXT: pinsrw $6, %edi, %xmm0818; SSE41-64-NEXT: pinsrw $7, %esi, %xmm0819; SSE41-64-NEXT: retq820;821; AVX-32-LABEL: test_buildvector_8i16_2_var:822; AVX-32: # %bb.0:823; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax824; AVX-32-NEXT: vmovd %eax, %xmm0825; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx826; AVX-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0827; AVX-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0828; AVX-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0829; AVX-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0830; AVX-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0831; AVX-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0832; AVX-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0833; AVX-32-NEXT: retl834;835; AVX-64-LABEL: test_buildvector_8i16_2_var:836; AVX-64: # %bb.0:837; AVX-64-NEXT: vmovd %edi, %xmm0838; AVX-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0839; AVX-64-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0840; AVX-64-NEXT: vpinsrw $3, %edi, %xmm0, %xmm0841; AVX-64-NEXT: vpinsrw $4, %edi, %xmm0, %xmm0842; AVX-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0843; AVX-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0844; AVX-64-NEXT: vpinsrw $7, %esi, %xmm0, %xmm0845; AVX-64-NEXT: retq846 %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0847 %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1848 %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2849 %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3850 %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4851 %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5852 %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6853 %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7854 ret <8 x i16> %v7855}856 857define <8 x i16> @test_buildvector_8i16_2_load(ptr %p0, ptr %p1) {858; SSE2-32-LABEL: test_buildvector_8i16_2_load:859; SSE2-32: # %bb.0:860; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax861; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx862; SSE2-32-NEXT: movzwl (%ecx), %ecx863; SSE2-32-NEXT: movd %ecx, %xmm1864; SSE2-32-NEXT: movzwl (%eax), %eax865; SSE2-32-NEXT: movd %eax, %xmm0866; SSE2-32-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]867; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]868; SSE2-32-NEXT: movdqa %xmm2, %xmm1869; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]870; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]871; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]872; SSE2-32-NEXT: retl873;874; SSE2-64-LABEL: test_buildvector_8i16_2_load:875; SSE2-64: # %bb.0:876; SSE2-64-NEXT: movzwl (%rsi), %eax877; SSE2-64-NEXT: movd %eax, %xmm1878; SSE2-64-NEXT: movzwl (%rdi), %eax879; SSE2-64-NEXT: movd %eax, %xmm0880; SSE2-64-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]881; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]882; SSE2-64-NEXT: movdqa %xmm2, %xmm1883; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]884; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]885; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]886; SSE2-64-NEXT: retq887;888; SSE41-32-LABEL: test_buildvector_8i16_2_load:889; SSE41-32: # %bb.0:890; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx891; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax892; SSE41-32-NEXT: movzwl (%eax), %eax893; SSE41-32-NEXT: movzwl (%ecx), %ecx894; SSE41-32-NEXT: movd %ecx, %xmm0895; SSE41-32-NEXT: pinsrw $1, %eax, %xmm0896; SSE41-32-NEXT: pinsrw $2, %ecx, %xmm0897; SSE41-32-NEXT: pinsrw $3, %ecx, %xmm0898; SSE41-32-NEXT: pinsrw $4, %ecx, %xmm0899; SSE41-32-NEXT: pinsrw $5, %ecx, %xmm0900; SSE41-32-NEXT: pinsrw $6, %ecx, %xmm0901; SSE41-32-NEXT: pinsrw $7, %eax, %xmm0902; SSE41-32-NEXT: retl903;904; SSE41-64-LABEL: test_buildvector_8i16_2_load:905; SSE41-64: # %bb.0:906; SSE41-64-NEXT: movzwl (%rsi), %eax907; SSE41-64-NEXT: movzwl (%rdi), %ecx908; SSE41-64-NEXT: movd %ecx, %xmm0909; SSE41-64-NEXT: pinsrw $1, %eax, %xmm0910; SSE41-64-NEXT: pinsrw $2, %ecx, %xmm0911; SSE41-64-NEXT: pinsrw $3, %ecx, %xmm0912; SSE41-64-NEXT: pinsrw $4, %ecx, %xmm0913; SSE41-64-NEXT: pinsrw $5, %ecx, %xmm0914; SSE41-64-NEXT: pinsrw $6, %ecx, %xmm0915; SSE41-64-NEXT: pinsrw $7, %eax, %xmm0916; SSE41-64-NEXT: retq917;918; AVX-32-LABEL: test_buildvector_8i16_2_load:919; AVX-32: # %bb.0:920; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax921; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx922; AVX-32-NEXT: movzwl (%ecx), %ecx923; AVX-32-NEXT: movzwl (%eax), %eax924; AVX-32-NEXT: vmovd %eax, %xmm0925; AVX-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0926; AVX-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0927; AVX-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0928; AVX-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0929; AVX-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0930; AVX-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0931; AVX-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0932; AVX-32-NEXT: retl933;934; AVX-64-LABEL: test_buildvector_8i16_2_load:935; AVX-64: # %bb.0:936; AVX-64-NEXT: movzwl (%rsi), %eax937; AVX-64-NEXT: movzwl (%rdi), %ecx938; AVX-64-NEXT: vmovd %ecx, %xmm0939; AVX-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0940; AVX-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0941; AVX-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0942; AVX-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0943; AVX-64-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0944; AVX-64-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0945; AVX-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0946; AVX-64-NEXT: retq947 %a0 = load i16, ptr %p0948 %a1 = load i16, ptr %p1949 %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0950 %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1951 %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2952 %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3953 %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4954 %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5955 %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6956 %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7957 ret <8 x i16> %v7958}959 960define <16 x i8> @test_buildvector_16i8_2_var(i8 %a0, i8 %a1) {961; SSE2-32-LABEL: test_buildvector_16i8_2_var:962; SSE2-32: # %bb.0:963; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero964; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero965; SSE2-32-NEXT: movdqa %xmm2, %xmm1966; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]967; SSE2-32-NEXT: movdqa %xmm0, %xmm3968; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]969; SSE2-32-NEXT: movdqa %xmm1, %xmm4970; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]971; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]972; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]973; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]974; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]975; SSE2-32-NEXT: movdqa %xmm3, %xmm2976; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]977; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]978; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]979; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]980; SSE2-32-NEXT: retl981;982; SSE2-64-LABEL: test_buildvector_16i8_2_var:983; SSE2-64: # %bb.0:984; SSE2-64-NEXT: movd %edi, %xmm0985; SSE2-64-NEXT: movd %esi, %xmm1986; SSE2-64-NEXT: movdqa %xmm1, %xmm2987; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]988; SSE2-64-NEXT: movdqa %xmm0, %xmm3989; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]990; SSE2-64-NEXT: movdqa %xmm2, %xmm4991; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]992; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]993; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]994; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]995; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]996; SSE2-64-NEXT: movdqa %xmm3, %xmm1997; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]998; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]999; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1000; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]1001; SSE2-64-NEXT: retq1002;1003; SSE41-32-LABEL: test_buildvector_16i8_2_var:1004; SSE41-32: # %bb.0:1005; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax1006; SSE41-32-NEXT: movd %eax, %xmm01007; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx1008; SSE41-32-NEXT: pinsrb $1, %ecx, %xmm01009; SSE41-32-NEXT: pinsrb $2, %eax, %xmm01010; SSE41-32-NEXT: pinsrb $3, %eax, %xmm01011; SSE41-32-NEXT: pinsrb $4, %eax, %xmm01012; SSE41-32-NEXT: pinsrb $5, %eax, %xmm01013; SSE41-32-NEXT: pinsrb $6, %eax, %xmm01014; SSE41-32-NEXT: pinsrb $7, %ecx, %xmm01015; SSE41-32-NEXT: pinsrb $8, %ecx, %xmm01016; SSE41-32-NEXT: pinsrb $9, %eax, %xmm01017; SSE41-32-NEXT: pinsrb $10, %ecx, %xmm01018; SSE41-32-NEXT: pinsrb $11, %ecx, %xmm01019; SSE41-32-NEXT: pinsrb $12, %ecx, %xmm01020; SSE41-32-NEXT: pinsrb $13, %eax, %xmm01021; SSE41-32-NEXT: pinsrb $14, %eax, %xmm01022; SSE41-32-NEXT: pinsrb $15, %eax, %xmm01023; SSE41-32-NEXT: retl1024;1025; SSE41-64-LABEL: test_buildvector_16i8_2_var:1026; SSE41-64: # %bb.0:1027; SSE41-64-NEXT: movd %edi, %xmm01028; SSE41-64-NEXT: pinsrb $1, %esi, %xmm01029; SSE41-64-NEXT: pinsrb $2, %edi, %xmm01030; SSE41-64-NEXT: pinsrb $3, %edi, %xmm01031; SSE41-64-NEXT: pinsrb $4, %edi, %xmm01032; SSE41-64-NEXT: pinsrb $5, %edi, %xmm01033; SSE41-64-NEXT: pinsrb $6, %edi, %xmm01034; SSE41-64-NEXT: pinsrb $7, %esi, %xmm01035; SSE41-64-NEXT: pinsrb $8, %esi, %xmm01036; SSE41-64-NEXT: pinsrb $9, %edi, %xmm01037; SSE41-64-NEXT: pinsrb $10, %esi, %xmm01038; SSE41-64-NEXT: pinsrb $11, %esi, %xmm01039; SSE41-64-NEXT: pinsrb $12, %esi, %xmm01040; SSE41-64-NEXT: pinsrb $13, %edi, %xmm01041; SSE41-64-NEXT: pinsrb $14, %edi, %xmm01042; SSE41-64-NEXT: pinsrb $15, %edi, %xmm01043; SSE41-64-NEXT: retq1044;1045; AVX-32-LABEL: test_buildvector_16i8_2_var:1046; AVX-32: # %bb.0:1047; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax1048; AVX-32-NEXT: vmovd %eax, %xmm01049; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx1050; AVX-32-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm01051; AVX-32-NEXT: vpinsrb $2, %eax, %xmm0, %xmm01052; AVX-32-NEXT: vpinsrb $3, %eax, %xmm0, %xmm01053; AVX-32-NEXT: vpinsrb $4, %eax, %xmm0, %xmm01054; AVX-32-NEXT: vpinsrb $5, %eax, %xmm0, %xmm01055; AVX-32-NEXT: vpinsrb $6, %eax, %xmm0, %xmm01056; AVX-32-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm01057; AVX-32-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm01058; AVX-32-NEXT: vpinsrb $9, %eax, %xmm0, %xmm01059; AVX-32-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm01060; AVX-32-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm01061; AVX-32-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm01062; AVX-32-NEXT: vpinsrb $13, %eax, %xmm0, %xmm01063; AVX-32-NEXT: vpinsrb $14, %eax, %xmm0, %xmm01064; AVX-32-NEXT: vpinsrb $15, %eax, %xmm0, %xmm01065; AVX-32-NEXT: retl1066;1067; AVX-64-LABEL: test_buildvector_16i8_2_var:1068; AVX-64: # %bb.0:1069; AVX-64-NEXT: vmovd %edi, %xmm01070; AVX-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm01071; AVX-64-NEXT: vpinsrb $2, %edi, %xmm0, %xmm01072; AVX-64-NEXT: vpinsrb $3, %edi, %xmm0, %xmm01073; AVX-64-NEXT: vpinsrb $4, %edi, %xmm0, %xmm01074; AVX-64-NEXT: vpinsrb $5, %edi, %xmm0, %xmm01075; AVX-64-NEXT: vpinsrb $6, %edi, %xmm0, %xmm01076; AVX-64-NEXT: vpinsrb $7, %esi, %xmm0, %xmm01077; AVX-64-NEXT: vpinsrb $8, %esi, %xmm0, %xmm01078; AVX-64-NEXT: vpinsrb $9, %edi, %xmm0, %xmm01079; AVX-64-NEXT: vpinsrb $10, %esi, %xmm0, %xmm01080; AVX-64-NEXT: vpinsrb $11, %esi, %xmm0, %xmm01081; AVX-64-NEXT: vpinsrb $12, %esi, %xmm0, %xmm01082; AVX-64-NEXT: vpinsrb $13, %edi, %xmm0, %xmm01083; AVX-64-NEXT: vpinsrb $14, %edi, %xmm0, %xmm01084; AVX-64-NEXT: vpinsrb $15, %edi, %xmm0, %xmm01085; AVX-64-NEXT: retq1086 %v0 = insertelement <16 x i8> poison, i8 %a0, i8 01087 %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 11088 %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 21089 %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 31090 %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 41091 %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 51092 %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 61093 %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 71094 %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 81095 %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 91096 %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 101097 %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 111098 %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 121099 %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 131100 %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 141101 %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 151102 ret <16 x i8> %v151103}1104 1105define <16 x i8> @test_buildvector_16i8_2_load(ptr %p0, ptr %p1) {1106; SSE2-32-LABEL: test_buildvector_16i8_2_load:1107; SSE2-32: # %bb.0:1108; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax1109; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx1110; SSE2-32-NEXT: movzbl (%ecx), %ecx1111; SSE2-32-NEXT: movd %ecx, %xmm01112; SSE2-32-NEXT: movzbl (%eax), %eax1113; SSE2-32-NEXT: movd %eax, %xmm21114; SSE2-32-NEXT: movdqa %xmm2, %xmm11115; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]1116; SSE2-32-NEXT: movdqa %xmm0, %xmm31117; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]1118; SSE2-32-NEXT: movdqa %xmm1, %xmm41119; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]1120; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]1121; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]1122; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]1123; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]1124; SSE2-32-NEXT: movdqa %xmm3, %xmm21125; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]1126; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]1127; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]1128; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]1129; SSE2-32-NEXT: retl1130;1131; SSE2-64-LABEL: test_buildvector_16i8_2_load:1132; SSE2-64: # %bb.0:1133; SSE2-64-NEXT: movzbl (%rdi), %eax1134; SSE2-64-NEXT: movd %eax, %xmm01135; SSE2-64-NEXT: movzbl (%rsi), %eax1136; SSE2-64-NEXT: movd %eax, %xmm11137; SSE2-64-NEXT: movdqa %xmm1, %xmm21138; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]1139; SSE2-64-NEXT: movdqa %xmm0, %xmm31140; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]1141; SSE2-64-NEXT: movdqa %xmm2, %xmm41142; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]1143; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]1144; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]1145; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]1146; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]1147; SSE2-64-NEXT: movdqa %xmm3, %xmm11148; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]1149; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]1150; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1151; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]1152; SSE2-64-NEXT: retq1153;1154; SSE41-32-LABEL: test_buildvector_16i8_2_load:1155; SSE41-32: # %bb.0:1156; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax1157; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx1158; SSE41-32-NEXT: movzbl (%ecx), %ecx1159; SSE41-32-NEXT: movzbl (%eax), %eax1160; SSE41-32-NEXT: movd %eax, %xmm01161; SSE41-32-NEXT: pinsrb $1, %ecx, %xmm01162; SSE41-32-NEXT: pinsrb $2, %eax, %xmm01163; SSE41-32-NEXT: pinsrb $3, %eax, %xmm01164; SSE41-32-NEXT: pinsrb $4, %eax, %xmm01165; SSE41-32-NEXT: pinsrb $5, %eax, %xmm01166; SSE41-32-NEXT: pinsrb $6, %eax, %xmm01167; SSE41-32-NEXT: pinsrb $7, %ecx, %xmm01168; SSE41-32-NEXT: pinsrb $8, %ecx, %xmm01169; SSE41-32-NEXT: pinsrb $9, %eax, %xmm01170; SSE41-32-NEXT: pinsrb $10, %ecx, %xmm01171; SSE41-32-NEXT: pinsrb $11, %ecx, %xmm01172; SSE41-32-NEXT: pinsrb $12, %ecx, %xmm01173; SSE41-32-NEXT: pinsrb $13, %eax, %xmm01174; SSE41-32-NEXT: pinsrb $14, %eax, %xmm01175; SSE41-32-NEXT: pinsrb $15, %eax, %xmm01176; SSE41-32-NEXT: retl1177;1178; SSE41-64-LABEL: test_buildvector_16i8_2_load:1179; SSE41-64: # %bb.0:1180; SSE41-64-NEXT: movzbl (%rsi), %ecx1181; SSE41-64-NEXT: movzbl (%rdi), %eax1182; SSE41-64-NEXT: movd %eax, %xmm01183; SSE41-64-NEXT: pinsrb $1, %ecx, %xmm01184; SSE41-64-NEXT: pinsrb $2, %eax, %xmm01185; SSE41-64-NEXT: pinsrb $3, %eax, %xmm01186; SSE41-64-NEXT: pinsrb $4, %eax, %xmm01187; SSE41-64-NEXT: pinsrb $5, %eax, %xmm01188; SSE41-64-NEXT: pinsrb $6, %eax, %xmm01189; SSE41-64-NEXT: pinsrb $7, %ecx, %xmm01190; SSE41-64-NEXT: pinsrb $8, %ecx, %xmm01191; SSE41-64-NEXT: pinsrb $9, %eax, %xmm01192; SSE41-64-NEXT: pinsrb $10, %ecx, %xmm01193; SSE41-64-NEXT: pinsrb $11, %ecx, %xmm01194; SSE41-64-NEXT: pinsrb $12, %ecx, %xmm01195; SSE41-64-NEXT: pinsrb $13, %eax, %xmm01196; SSE41-64-NEXT: pinsrb $14, %eax, %xmm01197; SSE41-64-NEXT: pinsrb $15, %eax, %xmm01198; SSE41-64-NEXT: retq1199;1200; AVX-32-LABEL: test_buildvector_16i8_2_load:1201; AVX-32: # %bb.0:1202; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax1203; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx1204; AVX-32-NEXT: movzbl (%ecx), %ecx1205; AVX-32-NEXT: movzbl (%eax), %eax1206; AVX-32-NEXT: vmovd %eax, %xmm01207; AVX-32-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm01208; AVX-32-NEXT: vpinsrb $2, %eax, %xmm0, %xmm01209; AVX-32-NEXT: vpinsrb $3, %eax, %xmm0, %xmm01210; AVX-32-NEXT: vpinsrb $4, %eax, %xmm0, %xmm01211; AVX-32-NEXT: vpinsrb $5, %eax, %xmm0, %xmm01212; AVX-32-NEXT: vpinsrb $6, %eax, %xmm0, %xmm01213; AVX-32-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm01214; AVX-32-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm01215; AVX-32-NEXT: vpinsrb $9, %eax, %xmm0, %xmm01216; AVX-32-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm01217; AVX-32-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm01218; AVX-32-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm01219; AVX-32-NEXT: vpinsrb $13, %eax, %xmm0, %xmm01220; AVX-32-NEXT: vpinsrb $14, %eax, %xmm0, %xmm01221; AVX-32-NEXT: vpinsrb $15, %eax, %xmm0, %xmm01222; AVX-32-NEXT: retl1223;1224; AVX-64-LABEL: test_buildvector_16i8_2_load:1225; AVX-64: # %bb.0:1226; AVX-64-NEXT: movzbl (%rsi), %eax1227; AVX-64-NEXT: movzbl (%rdi), %ecx1228; AVX-64-NEXT: vmovd %ecx, %xmm01229; AVX-64-NEXT: vpinsrb $1, %eax, %xmm0, %xmm01230; AVX-64-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm01231; AVX-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm01232; AVX-64-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm01233; AVX-64-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm01234; AVX-64-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm01235; AVX-64-NEXT: vpinsrb $7, %eax, %xmm0, %xmm01236; AVX-64-NEXT: vpinsrb $8, %eax, %xmm0, %xmm01237; AVX-64-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm01238; AVX-64-NEXT: vpinsrb $10, %eax, %xmm0, %xmm01239; AVX-64-NEXT: vpinsrb $11, %eax, %xmm0, %xmm01240; AVX-64-NEXT: vpinsrb $12, %eax, %xmm0, %xmm01241; AVX-64-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm01242; AVX-64-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm01243; AVX-64-NEXT: vpinsrb $15, %ecx, %xmm0, %xmm01244; AVX-64-NEXT: retq1245 %a0 = load i8, ptr %p01246 %a1 = load i8, ptr %p11247 %v0 = insertelement <16 x i8> poison, i8 %a0, i8 01248 %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 11249 %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 21250 %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 31251 %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 41252 %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 51253 %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 61254 %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 71255 %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 81256 %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 91257 %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 101258 %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 111259 %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 121260 %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 131261 %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 141262 %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 151263 ret <16 x i8> %v151264}1265 1266; PR307801267 1268define <4 x i32> @test_buildvector_v4i32_splat_sext_i8(i8 %in) {1269; SSE-32-LABEL: test_buildvector_v4i32_splat_sext_i8:1270; SSE-32: # %bb.0:1271; SSE-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax1272; SSE-32-NEXT: movd %eax, %xmm01273; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1274; SSE-32-NEXT: retl1275;1276; SSE-64-LABEL: test_buildvector_v4i32_splat_sext_i8:1277; SSE-64: # %bb.0:1278; SSE-64-NEXT: movsbl %dil, %eax1279; SSE-64-NEXT: movd %eax, %xmm01280; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1281; SSE-64-NEXT: retq1282;1283; AVX1-32-LABEL: test_buildvector_v4i32_splat_sext_i8:1284; AVX1-32: # %bb.0:1285; AVX1-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax1286; AVX1-32-NEXT: vmovd %eax, %xmm01287; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1288; AVX1-32-NEXT: retl1289;1290; AVX1-64-LABEL: test_buildvector_v4i32_splat_sext_i8:1291; AVX1-64: # %bb.0:1292; AVX1-64-NEXT: movsbl %dil, %eax1293; AVX1-64-NEXT: vmovd %eax, %xmm01294; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1295; AVX1-64-NEXT: retq1296;1297; AVX2-32-LABEL: test_buildvector_v4i32_splat_sext_i8:1298; AVX2-32: # %bb.0:1299; AVX2-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax1300; AVX2-32-NEXT: vmovd %eax, %xmm01301; AVX2-32-NEXT: vpbroadcastd %xmm0, %xmm01302; AVX2-32-NEXT: retl1303;1304; AVX2-64-LABEL: test_buildvector_v4i32_splat_sext_i8:1305; AVX2-64: # %bb.0:1306; AVX2-64-NEXT: movsbl %dil, %eax1307; AVX2-64-NEXT: vmovd %eax, %xmm01308; AVX2-64-NEXT: vpbroadcastd %xmm0, %xmm01309; AVX2-64-NEXT: retq1310 %ext = sext i8 %in to i321311 %insert = insertelement <4 x i32> undef, i32 %ext, i32 01312 %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer1313 ret <4 x i32> %splat1314}1315 1316define <4 x i32> @test_buildvector_v4i32_splat_zext_i8(i8 %in) {1317; SSE-32-LABEL: test_buildvector_v4i32_splat_zext_i8:1318; SSE-32: # %bb.0:1319; SSE-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax1320; SSE-32-NEXT: movd %eax, %xmm01321; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1322; SSE-32-NEXT: retl1323;1324; SSE-64-LABEL: test_buildvector_v4i32_splat_zext_i8:1325; SSE-64: # %bb.0:1326; SSE-64-NEXT: movzbl %dil, %eax1327; SSE-64-NEXT: movd %eax, %xmm01328; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1329; SSE-64-NEXT: retq1330;1331; AVX1-32-LABEL: test_buildvector_v4i32_splat_zext_i8:1332; AVX1-32: # %bb.0:1333; AVX1-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax1334; AVX1-32-NEXT: vmovd %eax, %xmm01335; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1336; AVX1-32-NEXT: retl1337;1338; AVX1-64-LABEL: test_buildvector_v4i32_splat_zext_i8:1339; AVX1-64: # %bb.0:1340; AVX1-64-NEXT: movzbl %dil, %eax1341; AVX1-64-NEXT: vmovd %eax, %xmm01342; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]1343; AVX1-64-NEXT: retq1344;1345; AVX2-32-LABEL: test_buildvector_v4i32_splat_zext_i8:1346; AVX2-32: # %bb.0:1347; AVX2-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax1348; AVX2-32-NEXT: vmovd %eax, %xmm01349; AVX2-32-NEXT: vpbroadcastd %xmm0, %xmm01350; AVX2-32-NEXT: retl1351;1352; AVX2-64-LABEL: test_buildvector_v4i32_splat_zext_i8:1353; AVX2-64: # %bb.0:1354; AVX2-64-NEXT: movzbl %dil, %eax1355; AVX2-64-NEXT: vmovd %eax, %xmm01356; AVX2-64-NEXT: vpbroadcastd %xmm0, %xmm01357; AVX2-64-NEXT: retq1358 %ext = zext i8 %in to i321359 %insert = insertelement <4 x i32> undef, i32 %ext, i32 01360 %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer1361 ret <4 x i32> %splat1362}1363 1364; PR37502 - https://bugs.llvm.org/show_bug.cgi?id=375021365; Don't use a series of insertps when movddup will do.1366 1367define <4 x float> @PR37502(float %x, float %y) {1368; SSE2-32-LABEL: PR37502:1369; SSE2-32: # %bb.0:1370; SSE2-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero1371; SSE2-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]1372; SSE2-32-NEXT: retl1373;1374; SSE2-64-LABEL: PR37502:1375; SSE2-64: # %bb.0:1376; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]1377; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]1378; SSE2-64-NEXT: retq1379;1380; SSE41-32-LABEL: PR37502:1381; SSE41-32: # %bb.0:1382; SSE41-32-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]1383; SSE41-32-NEXT: retl1384;1385; SSE41-64-LABEL: PR37502:1386; SSE41-64: # %bb.0:1387; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]1388; SSE41-64-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]1389; SSE41-64-NEXT: retq1390;1391; AVX-32-LABEL: PR37502:1392; AVX-32: # %bb.0:1393; AVX-32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]1394; AVX-32-NEXT: retl1395;1396; AVX-64-LABEL: PR37502:1397; AVX-64: # %bb.0:1398; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]1399; AVX-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]1400; AVX-64-NEXT: retq1401 %i0 = insertelement <4 x float> undef, float %x, i32 01402 %i1 = insertelement <4 x float> %i0, float %y, i32 11403 %i2 = insertelement <4 x float> %i1, float %x, i32 21404 %i3 = insertelement <4 x float> %i2, float %y, i32 31405 ret <4 x float> %i31406}1407 1408define void @pr60168_buildvector_of_zeros_and_undef(<2 x i32> %x, ptr %out) {1409; SSE2-32-LABEL: pr60168_buildvector_of_zeros_and_undef:1410; SSE2-32: # %bb.0:1411; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax1412; SSE2-32-NEXT: paddd %xmm0, %xmm01413; SSE2-32-NEXT: pxor %xmm1, %xmm11414; SSE2-32-NEXT: psubd %xmm0, %xmm11415; SSE2-32-NEXT: movdqa %xmm1, %xmm01416; SSE2-32-NEXT: psrad $31, %xmm01417; SSE2-32-NEXT: pxor %xmm0, %xmm11418; SSE2-32-NEXT: psubd %xmm0, %xmm11419; SSE2-32-NEXT: movq %xmm1, (%eax)1420; SSE2-32-NEXT: retl1421;1422; SSE2-64-LABEL: pr60168_buildvector_of_zeros_and_undef:1423; SSE2-64: # %bb.0:1424; SSE2-64-NEXT: paddd %xmm0, %xmm01425; SSE2-64-NEXT: pxor %xmm1, %xmm11426; SSE2-64-NEXT: psubd %xmm0, %xmm11427; SSE2-64-NEXT: movdqa %xmm1, %xmm01428; SSE2-64-NEXT: psrad $31, %xmm01429; SSE2-64-NEXT: pxor %xmm0, %xmm11430; SSE2-64-NEXT: psubd %xmm0, %xmm11431; SSE2-64-NEXT: movq %xmm1, (%rdi)1432; SSE2-64-NEXT: retq1433;1434; SSE41-32-LABEL: pr60168_buildvector_of_zeros_and_undef:1435; SSE41-32: # %bb.0:1436; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax1437; SSE41-32-NEXT: paddd %xmm0, %xmm01438; SSE41-32-NEXT: pxor %xmm1, %xmm11439; SSE41-32-NEXT: psubd %xmm0, %xmm11440; SSE41-32-NEXT: pabsd %xmm1, %xmm01441; SSE41-32-NEXT: movq %xmm0, (%eax)1442; SSE41-32-NEXT: retl1443;1444; SSE41-64-LABEL: pr60168_buildvector_of_zeros_and_undef:1445; SSE41-64: # %bb.0:1446; SSE41-64-NEXT: paddd %xmm0, %xmm01447; SSE41-64-NEXT: pxor %xmm1, %xmm11448; SSE41-64-NEXT: psubd %xmm0, %xmm11449; SSE41-64-NEXT: pabsd %xmm1, %xmm01450; SSE41-64-NEXT: movq %xmm0, (%rdi)1451; SSE41-64-NEXT: retq1452;1453; AVX-32-LABEL: pr60168_buildvector_of_zeros_and_undef:1454; AVX-32: # %bb.0:1455; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax1456; AVX-32-NEXT: vpaddd %xmm0, %xmm0, %xmm01457; AVX-32-NEXT: vpxor %xmm1, %xmm1, %xmm11458; AVX-32-NEXT: vpsubd %xmm0, %xmm1, %xmm01459; AVX-32-NEXT: vpabsd %xmm0, %xmm01460; AVX-32-NEXT: vmovq %xmm0, (%eax)1461; AVX-32-NEXT: retl1462;1463; AVX-64-LABEL: pr60168_buildvector_of_zeros_and_undef:1464; AVX-64: # %bb.0:1465; AVX-64-NEXT: vpaddd %xmm0, %xmm0, %xmm01466; AVX-64-NEXT: vpxor %xmm1, %xmm1, %xmm11467; AVX-64-NEXT: vpsubd %xmm0, %xmm1, %xmm01468; AVX-64-NEXT: vpabsd %xmm0, %xmm01469; AVX-64-NEXT: vmovq %xmm0, (%rdi)1470; AVX-64-NEXT: retq1471 %i2 = mul <2 x i32> %x, <i32 -2, i32 -2>1472 %i3 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %i2, i1 false)1473 store <2 x i32> %i3, ptr %out1474 ret void1475}1476declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1 immarg)1477