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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX1-323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX1-644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX2-325; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX2-646 7define <4 x double> @test_buildvector_v4f64(double %a0, double %a1, double %a2, double %a3) {8; AVX-32-LABEL: test_buildvector_v4f64:9; AVX-32: # %bb.0:10; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm011; AVX-32-NEXT: retl12;13; AVX-64-LABEL: test_buildvector_v4f64:14; AVX-64: # %bb.0:15; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]16; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]17; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm018; AVX-64-NEXT: retq19 %ins0 = insertelement <4 x double> undef, double %a0, i32 020 %ins1 = insertelement <4 x double> %ins0, double %a1, i32 121 %ins2 = insertelement <4 x double> %ins1, double %a2, i32 222 %ins3 = insertelement <4 x double> %ins2, double %a3, i32 323 ret <4 x double> %ins324}25 26define <8 x float> @test_buildvector_v8f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) {27; AVX-32-LABEL: test_buildvector_v8f32:28; AVX-32: # %bb.0:29; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm030; AVX-32-NEXT: retl31;32; AVX-64-LABEL: test_buildvector_v8f32:33; AVX-64: # %bb.0:34; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]35; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]36; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]37; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]38; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]39; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]40; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm041; AVX-64-NEXT: retq42 %ins0 = insertelement <8 x float> undef, float %a0, i32 043 %ins1 = insertelement <8 x float> %ins0, float %a1, i32 144 %ins2 = insertelement <8 x float> %ins1, float %a2, i32 245 %ins3 = insertelement <8 x float> %ins2, float %a3, i32 346 %ins4 = insertelement <8 x float> %ins3, float %a4, i32 447 %ins5 = insertelement <8 x float> %ins4, float %a5, i32 548 %ins6 = insertelement <8 x float> %ins5, float %a6, i32 649 %ins7 = insertelement <8 x float> %ins6, float %a7, i32 750 ret <8 x float> %ins751}52 53define <4 x i64> @test_buildvector_v4i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {54; AVX-32-LABEL: test_buildvector_v4i64:55; AVX-32: # %bb.0:56; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm057; AVX-32-NEXT: retl58;59; AVX1-64-LABEL: test_buildvector_v4i64:60; AVX1-64: # %bb.0:61; AVX1-64-NEXT: vmovq %rcx, %xmm062; AVX1-64-NEXT: vmovq %rdx, %xmm163; AVX1-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]64; AVX1-64-NEXT: vmovq %rsi, %xmm165; AVX1-64-NEXT: vmovq %rdi, %xmm266; AVX1-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]67; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm068; AVX1-64-NEXT: retq69;70; AVX2-64-LABEL: test_buildvector_v4i64:71; AVX2-64: # %bb.0:72; AVX2-64-NEXT: vmovq %rcx, %xmm073; AVX2-64-NEXT: vmovq %rdx, %xmm174; AVX2-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]75; AVX2-64-NEXT: vmovq %rsi, %xmm176; AVX2-64-NEXT: vmovq %rdi, %xmm277; AVX2-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]78; AVX2-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm079; AVX2-64-NEXT: retq80 %ins0 = insertelement <4 x i64> undef, i64 %a0, i32 081 %ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 182 %ins2 = insertelement <4 x i64> %ins1, i64 %a2, i32 283 %ins3 = insertelement <4 x i64> %ins2, i64 %a3, i32 384 ret <4 x i64> %ins385}86 87define <8 x i32> @test_buildvector_v8i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) {88; AVX-32-LABEL: test_buildvector_v8i32:89; AVX-32: # %bb.0:90; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm091; AVX-32-NEXT: retl92;93; AVX1-64-LABEL: test_buildvector_v8i32:94; AVX1-64: # %bb.0:95; AVX1-64-NEXT: vmovd %edi, %xmm096; AVX1-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm097; AVX1-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm098; AVX1-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm099; AVX1-64-NEXT: vmovd %r8d, %xmm1100; AVX1-64-NEXT: vpinsrd $1, %r9d, %xmm1, %xmm1101; AVX1-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1102; AVX1-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1103; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0104; AVX1-64-NEXT: retq105;106; AVX2-64-LABEL: test_buildvector_v8i32:107; AVX2-64: # %bb.0:108; AVX2-64-NEXT: vmovd %edi, %xmm0109; AVX2-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0110; AVX2-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0111; AVX2-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0112; AVX2-64-NEXT: vmovd %r8d, %xmm1113; AVX2-64-NEXT: vpinsrd $1, %r9d, %xmm1, %xmm1114; AVX2-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1115; AVX2-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1116; AVX2-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0117; AVX2-64-NEXT: retq118 %ins0 = insertelement <8 x i32> undef, i32 %a0, i32 0119 %ins1 = insertelement <8 x i32> %ins0, i32 %a1, i32 1120 %ins2 = insertelement <8 x i32> %ins1, i32 %a2, i32 2121 %ins3 = insertelement <8 x i32> %ins2, i32 %a3, i32 3122 %ins4 = insertelement <8 x i32> %ins3, i32 %a4, i32 4123 %ins5 = insertelement <8 x i32> %ins4, i32 %a5, i32 5124 %ins6 = insertelement <8 x i32> %ins5, i32 %a6, i32 6125 %ins7 = insertelement <8 x i32> %ins6, i32 %a7, i32 7126 ret <8 x i32> %ins7127}128 129define <16 x i16> @test_buildvector_v16i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) {130; AVX1-32-LABEL: test_buildvector_v16i16:131; AVX1-32: # %bb.0:132; AVX1-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero133; AVX1-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0134; AVX1-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0135; AVX1-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0136; AVX1-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0137; AVX1-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0138; AVX1-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0139; AVX1-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0140; AVX1-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero141; AVX1-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1142; AVX1-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1143; AVX1-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1144; AVX1-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1145; AVX1-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1146; AVX1-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1147; AVX1-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1148; AVX1-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0149; AVX1-32-NEXT: retl150;151; AVX1-64-LABEL: test_buildvector_v16i16:152; AVX1-64: # %bb.0:153; AVX1-64-NEXT: vmovd %edi, %xmm0154; AVX1-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0155; AVX1-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0156; AVX1-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0157; AVX1-64-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0158; AVX1-64-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0159; AVX1-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0160; AVX1-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0161; AVX1-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero162; AVX1-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1163; AVX1-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1164; AVX1-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1165; AVX1-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1166; AVX1-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1167; AVX1-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1168; AVX1-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1169; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0170; AVX1-64-NEXT: retq171;172; AVX2-32-LABEL: test_buildvector_v16i16:173; AVX2-32: # %bb.0:174; AVX2-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero175; AVX2-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0176; AVX2-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0177; AVX2-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0178; AVX2-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0179; AVX2-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0180; AVX2-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0181; AVX2-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0182; AVX2-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero183; AVX2-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1184; AVX2-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1185; AVX2-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1186; AVX2-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1187; AVX2-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1188; AVX2-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1189; AVX2-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1190; AVX2-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0191; AVX2-32-NEXT: retl192;193; AVX2-64-LABEL: test_buildvector_v16i16:194; AVX2-64: # %bb.0:195; AVX2-64-NEXT: vmovd %edi, %xmm0196; AVX2-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0197; AVX2-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0198; AVX2-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0199; AVX2-64-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0200; AVX2-64-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0201; AVX2-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0202; AVX2-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0203; AVX2-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero204; AVX2-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1205; AVX2-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1206; AVX2-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1207; AVX2-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1208; AVX2-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1209; AVX2-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1210; AVX2-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1211; AVX2-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0212; AVX2-64-NEXT: retq213 %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0214 %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1215 %ins2 = insertelement <16 x i16> %ins1, i16 %a2, i32 2216 %ins3 = insertelement <16 x i16> %ins2, i16 %a3, i32 3217 %ins4 = insertelement <16 x i16> %ins3, i16 %a4, i32 4218 %ins5 = insertelement <16 x i16> %ins4, i16 %a5, i32 5219 %ins6 = insertelement <16 x i16> %ins5, i16 %a6, i32 6220 %ins7 = insertelement <16 x i16> %ins6, i16 %a7, i32 7221 %ins8 = insertelement <16 x i16> %ins7, i16 %a8, i32 8222 %ins9 = insertelement <16 x i16> %ins8, i16 %a9, i32 9223 %ins10 = insertelement <16 x i16> %ins9, i16 %a10, i32 10224 %ins11 = insertelement <16 x i16> %ins10, i16 %a11, i32 11225 %ins12 = insertelement <16 x i16> %ins11, i16 %a12, i32 12226 %ins13 = insertelement <16 x i16> %ins12, i16 %a13, i32 13227 %ins14 = insertelement <16 x i16> %ins13, i16 %a14, i32 14228 %ins15 = insertelement <16 x i16> %ins14, i16 %a15, i32 15229 ret <16 x i16> %ins15230}231 232define <32 x i8> @test_buildvector_v32i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) {233; AVX1-32-LABEL: test_buildvector_v32i8:234; AVX1-32: # %bb.0:235; AVX1-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero236; AVX1-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0237; AVX1-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0238; AVX1-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0239; AVX1-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0240; AVX1-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0241; AVX1-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0242; AVX1-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0243; AVX1-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0244; AVX1-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0245; AVX1-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0246; AVX1-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0247; AVX1-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0248; AVX1-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0249; AVX1-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0250; AVX1-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0251; AVX1-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero252; AVX1-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1253; AVX1-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1254; AVX1-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1255; AVX1-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1256; AVX1-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1257; AVX1-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1258; AVX1-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1259; AVX1-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1260; AVX1-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1261; AVX1-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1262; AVX1-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1263; AVX1-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1264; AVX1-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1265; AVX1-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1266; AVX1-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1267; AVX1-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0268; AVX1-32-NEXT: retl269;270; AVX1-64-LABEL: test_buildvector_v32i8:271; AVX1-64: # %bb.0:272; AVX1-64-NEXT: vmovd %edi, %xmm0273; AVX1-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0274; AVX1-64-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0275; AVX1-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0276; AVX1-64-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0277; AVX1-64-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0278; AVX1-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0279; AVX1-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0280; AVX1-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0281; AVX1-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0282; AVX1-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0283; AVX1-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0284; AVX1-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0285; AVX1-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0286; AVX1-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0287; AVX1-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0288; AVX1-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero289; AVX1-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1290; AVX1-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1291; AVX1-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1292; AVX1-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1293; AVX1-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1294; AVX1-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1295; AVX1-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1296; AVX1-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1297; AVX1-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1298; AVX1-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1299; AVX1-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1300; AVX1-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1301; AVX1-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1302; AVX1-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1303; AVX1-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1304; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0305; AVX1-64-NEXT: retq306;307; AVX2-32-LABEL: test_buildvector_v32i8:308; AVX2-32: # %bb.0:309; AVX2-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero310; AVX2-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0311; AVX2-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0312; AVX2-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0313; AVX2-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0314; AVX2-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0315; AVX2-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0316; AVX2-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0317; AVX2-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0318; AVX2-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0319; AVX2-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0320; AVX2-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0321; AVX2-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0322; AVX2-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0323; AVX2-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0324; AVX2-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0325; AVX2-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero326; AVX2-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1327; AVX2-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1328; AVX2-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1329; AVX2-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1330; AVX2-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1331; AVX2-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1332; AVX2-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1333; AVX2-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1334; AVX2-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1335; AVX2-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1336; AVX2-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1337; AVX2-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1338; AVX2-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1339; AVX2-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1340; AVX2-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1341; AVX2-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0342; AVX2-32-NEXT: retl343;344; AVX2-64-LABEL: test_buildvector_v32i8:345; AVX2-64: # %bb.0:346; AVX2-64-NEXT: vmovd %edi, %xmm0347; AVX2-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0348; AVX2-64-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0349; AVX2-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0350; AVX2-64-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0351; AVX2-64-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0352; AVX2-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0353; AVX2-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0354; AVX2-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0355; AVX2-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0356; AVX2-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0357; AVX2-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0358; AVX2-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0359; AVX2-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0360; AVX2-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0361; AVX2-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0362; AVX2-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero363; AVX2-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1364; AVX2-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1365; AVX2-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1366; AVX2-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1367; AVX2-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1368; AVX2-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1369; AVX2-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1370; AVX2-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1371; AVX2-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1372; AVX2-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1373; AVX2-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1374; AVX2-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1375; AVX2-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1376; AVX2-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1377; AVX2-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1378; AVX2-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0379; AVX2-64-NEXT: retq380 %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0381 %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1382 %ins2 = insertelement <32 x i8> %ins1, i8 %a2, i32 2383 %ins3 = insertelement <32 x i8> %ins2, i8 %a3, i32 3384 %ins4 = insertelement <32 x i8> %ins3, i8 %a4, i32 4385 %ins5 = insertelement <32 x i8> %ins4, i8 %a5, i32 5386 %ins6 = insertelement <32 x i8> %ins5, i8 %a6, i32 6387 %ins7 = insertelement <32 x i8> %ins6, i8 %a7, i32 7388 %ins8 = insertelement <32 x i8> %ins7, i8 %a8, i32 8389 %ins9 = insertelement <32 x i8> %ins8, i8 %a9, i32 9390 %ins10 = insertelement <32 x i8> %ins9, i8 %a10, i32 10391 %ins11 = insertelement <32 x i8> %ins10, i8 %a11, i32 11392 %ins12 = insertelement <32 x i8> %ins11, i8 %a12, i32 12393 %ins13 = insertelement <32 x i8> %ins12, i8 %a13, i32 13394 %ins14 = insertelement <32 x i8> %ins13, i8 %a14, i32 14395 %ins15 = insertelement <32 x i8> %ins14, i8 %a15, i32 15396 %ins16 = insertelement <32 x i8> %ins15, i8 %a16, i32 16397 %ins17 = insertelement <32 x i8> %ins16, i8 %a17, i32 17398 %ins18 = insertelement <32 x i8> %ins17, i8 %a18, i32 18399 %ins19 = insertelement <32 x i8> %ins18, i8 %a19, i32 19400 %ins20 = insertelement <32 x i8> %ins19, i8 %a20, i32 20401 %ins21 = insertelement <32 x i8> %ins20, i8 %a21, i32 21402 %ins22 = insertelement <32 x i8> %ins21, i8 %a22, i32 22403 %ins23 = insertelement <32 x i8> %ins22, i8 %a23, i32 23404 %ins24 = insertelement <32 x i8> %ins23, i8 %a24, i32 24405 %ins25 = insertelement <32 x i8> %ins24, i8 %a25, i32 25406 %ins26 = insertelement <32 x i8> %ins25, i8 %a26, i32 26407 %ins27 = insertelement <32 x i8> %ins26, i8 %a27, i32 27408 %ins28 = insertelement <32 x i8> %ins27, i8 %a28, i32 28409 %ins29 = insertelement <32 x i8> %ins28, i8 %a29, i32 29410 %ins30 = insertelement <32 x i8> %ins29, i8 %a30, i32 30411 %ins31 = insertelement <32 x i8> %ins30, i8 %a31, i32 31412 ret <32 x i8> %ins31413}414 415; build vectors of repeated elements416 417define <4 x double> @test_buildvector_4f64_2_var(double %a0, double %a1) {418; AVX1-32-LABEL: test_buildvector_4f64_2_var:419; AVX1-32: # %bb.0:420; AVX1-32-NEXT: vmovupd {{[0-9]+}}(%esp), %xmm0421; AVX1-32-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]422; AVX1-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0423; AVX1-32-NEXT: retl424;425; AVX1-64-LABEL: test_buildvector_4f64_2_var:426; AVX1-64: # %bb.0:427; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]428; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]429; AVX1-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0430; AVX1-64-NEXT: retq431;432; AVX2-32-LABEL: test_buildvector_4f64_2_var:433; AVX2-32: # %bb.0:434; AVX2-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0435; AVX2-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm1436; AVX2-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]437; AVX2-32-NEXT: retl438;439; AVX2-64-LABEL: test_buildvector_4f64_2_var:440; AVX2-64: # %bb.0:441; AVX2-64-NEXT: vbroadcastsd %xmm1, %ymm1442; AVX2-64-NEXT: vbroadcastsd %xmm0, %ymm0443; AVX2-64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]444; AVX2-64-NEXT: retq445 %v0 = insertelement <4 x double> poison, double %a0, i32 0446 %v1 = insertelement <4 x double> %v0, double %a1, i32 1447 %v2 = insertelement <4 x double> %v1, double %a1, i32 2448 %v3 = insertelement <4 x double> %v2, double %a0, i32 3449 ret <4 x double> %v3450}451 452define <4 x double> @test_buildvector_4f64_2_load(ptr %p0, ptr %p1) {453; AVX1-32-LABEL: test_buildvector_4f64_2_load:454; AVX1-32: # %bb.0:455; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %eax456; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %ecx457; AVX1-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero458; AVX1-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero459; AVX1-32-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]460; AVX1-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]461; AVX1-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0462; AVX1-32-NEXT: retl463;464; AVX1-64-LABEL: test_buildvector_4f64_2_load:465; AVX1-64: # %bb.0:466; AVX1-64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero467; AVX1-64-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero468; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]469; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]470; AVX1-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0471; AVX1-64-NEXT: retq472;473; AVX2-32-LABEL: test_buildvector_4f64_2_load:474; AVX2-32: # %bb.0:475; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %eax476; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx477; AVX2-32-NEXT: vbroadcastsd (%ecx), %ymm0478; AVX2-32-NEXT: vbroadcastsd (%eax), %ymm1479; AVX2-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]480; AVX2-32-NEXT: retl481;482; AVX2-64-LABEL: test_buildvector_4f64_2_load:483; AVX2-64: # %bb.0:484; AVX2-64-NEXT: vbroadcastsd (%rsi), %ymm0485; AVX2-64-NEXT: vbroadcastsd (%rdi), %ymm1486; AVX2-64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]487; AVX2-64-NEXT: retq488 %a0 = load double, ptr %p0489 %a1 = load double, ptr %p1490 %v0 = insertelement <4 x double> poison, double %a0, i32 0491 %v1 = insertelement <4 x double> %v0, double %a1, i32 1492 %v2 = insertelement <4 x double> %v1, double %a1, i32 2493 %v3 = insertelement <4 x double> %v2, double %a0, i32 3494 ret <4 x double> %v3495}496 497define <8 x float> @test_buildvector_8f32_2_var(float %a0, float %a1) {498; AVX-32-LABEL: test_buildvector_8f32_2_var:499; AVX-32: # %bb.0:500; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero501; AVX-32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1502; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]503; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]504; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0505; AVX-32-NEXT: retl506;507; AVX1-64-LABEL: test_buildvector_8f32_2_var:508; AVX1-64: # %bb.0:509; AVX1-64-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0,0,3]510; AVX1-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]511; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[2,3]512; AVX1-64-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]513; AVX1-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0514; AVX1-64-NEXT: retq515;516; AVX2-64-LABEL: test_buildvector_8f32_2_var:517; AVX2-64: # %bb.0:518; AVX2-64-NEXT: vbroadcastss %xmm0, %xmm0519; AVX2-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm0[0,1,2],xmm1[0]520; AVX2-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]521; AVX2-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0522; AVX2-64-NEXT: retq523 %v0 = insertelement <8 x float> poison, float %a0, i32 0524 %v1 = insertelement <8 x float> %v0, float %a1, i32 1525 %v2 = insertelement <8 x float> %v1, float %a0, i32 2526 %v3 = insertelement <8 x float> %v2, float %a0, i32 3527 %v4 = insertelement <8 x float> %v3, float %a0, i32 4528 %v5 = insertelement <8 x float> %v4, float %a0, i32 5529 %v6 = insertelement <8 x float> %v5, float %a0, i32 6530 %v7 = insertelement <8 x float> %v6, float %a1, i32 7531 ret <8 x float> %v7532}533 534define <8 x float> @test_buildvector_8f32_2_load(ptr %p0, ptr %p1) {535; AVX-32-LABEL: test_buildvector_8f32_2_load:536; AVX-32: # %bb.0:537; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax538; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx539; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero540; AVX-32-NEXT: vbroadcastss (%eax), %xmm1541; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]542; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]543; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0544; AVX-32-NEXT: retl545;546; AVX-64-LABEL: test_buildvector_8f32_2_load:547; AVX-64: # %bb.0:548; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero549; AVX-64-NEXT: vbroadcastss (%rdi), %xmm1550; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]551; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]552; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0553; AVX-64-NEXT: retq554 %a0 = load float, ptr %p0555 %a1 = load float, ptr %p1556 %v0 = insertelement <8 x float> poison, float %a0, i32 0557 %v1 = insertelement <8 x float> %v0, float %a1, i32 1558 %v2 = insertelement <8 x float> %v1, float %a0, i32 2559 %v3 = insertelement <8 x float> %v2, float %a0, i32 3560 %v4 = insertelement <8 x float> %v3, float %a0, i32 4561 %v5 = insertelement <8 x float> %v4, float %a0, i32 5562 %v6 = insertelement <8 x float> %v5, float %a0, i32 6563 %v7 = insertelement <8 x float> %v6, float %a1, i32 7564 ret <8 x float> %v7565}566 567define <16 x i16> @test_buildvector_16i16_2_var(i16 %a0, i16 %a1) {568; AVX1-32-LABEL: test_buildvector_16i16_2_var:569; AVX1-32: # %bb.0:570; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %eax571; AVX1-32-NEXT: vmovd %eax, %xmm0572; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %ecx573; AVX1-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0574; AVX1-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0575; AVX1-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0576; AVX1-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0577; AVX1-32-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0578; AVX1-32-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0579; AVX1-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0580; AVX1-32-NEXT: vmovd %ecx, %xmm1581; AVX1-32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1582; AVX1-32-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1583; AVX1-32-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1584; AVX1-32-NEXT: vpinsrw $4, %ecx, %xmm1, %xmm1585; AVX1-32-NEXT: vpinsrw $5, %ecx, %xmm1, %xmm1586; AVX1-32-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1587; AVX1-32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1588; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0589; AVX1-32-NEXT: retl590;591; AVX1-64-LABEL: test_buildvector_16i16_2_var:592; AVX1-64: # %bb.0:593; AVX1-64-NEXT: vmovd %esi, %xmm0594; AVX1-64-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0595; AVX1-64-NEXT: vpinsrw $2, %esi, %xmm0, %xmm0596; AVX1-64-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0597; AVX1-64-NEXT: vpinsrw $4, %esi, %xmm0, %xmm0598; AVX1-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0599; AVX1-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0600; AVX1-64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0601; AVX1-64-NEXT: vmovd %edi, %xmm1602; AVX1-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1603; AVX1-64-NEXT: vpinsrw $2, %edi, %xmm1, %xmm1604; AVX1-64-NEXT: vpinsrw $3, %edi, %xmm1, %xmm1605; AVX1-64-NEXT: vpinsrw $4, %edi, %xmm1, %xmm1606; AVX1-64-NEXT: vpinsrw $5, %edi, %xmm1, %xmm1607; AVX1-64-NEXT: vpinsrw $6, %edi, %xmm1, %xmm1608; AVX1-64-NEXT: vpinsrw $7, %esi, %xmm1, %xmm1609; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0610; AVX1-64-NEXT: retq611;612; AVX2-32-LABEL: test_buildvector_16i16_2_var:613; AVX2-32: # %bb.0:614; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %eax615; AVX2-32-NEXT: vmovd %eax, %xmm0616; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx617; AVX2-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0618; AVX2-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0619; AVX2-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0620; AVX2-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0621; AVX2-32-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0622; AVX2-32-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0623; AVX2-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0624; AVX2-32-NEXT: vmovd %ecx, %xmm1625; AVX2-32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1626; AVX2-32-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1627; AVX2-32-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1628; AVX2-32-NEXT: vpinsrw $4, %ecx, %xmm1, %xmm1629; AVX2-32-NEXT: vpinsrw $5, %ecx, %xmm1, %xmm1630; AVX2-32-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1631; AVX2-32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1632; AVX2-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0633; AVX2-32-NEXT: retl634;635; AVX2-64-LABEL: test_buildvector_16i16_2_var:636; AVX2-64: # %bb.0:637; AVX2-64-NEXT: vmovd %esi, %xmm0638; AVX2-64-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0639; AVX2-64-NEXT: vpinsrw $2, %esi, %xmm0, %xmm0640; AVX2-64-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0641; AVX2-64-NEXT: vpinsrw $4, %esi, %xmm0, %xmm0642; AVX2-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0643; AVX2-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0644; AVX2-64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0645; AVX2-64-NEXT: vmovd %edi, %xmm1646; AVX2-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1647; AVX2-64-NEXT: vpinsrw $2, %edi, %xmm1, %xmm1648; AVX2-64-NEXT: vpinsrw $3, %edi, %xmm1, %xmm1649; AVX2-64-NEXT: vpinsrw $4, %edi, %xmm1, %xmm1650; AVX2-64-NEXT: vpinsrw $5, %edi, %xmm1, %xmm1651; AVX2-64-NEXT: vpinsrw $6, %edi, %xmm1, %xmm1652; AVX2-64-NEXT: vpinsrw $7, %esi, %xmm1, %xmm1653; AVX2-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0654; AVX2-64-NEXT: retq655 %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0656 %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1657 %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2658 %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3659 %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4660 %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5661 %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6662 %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7663 %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8664 %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9665 %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10666 %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11667 %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12668 %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13669 %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14670 %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15671 ret <16 x i16> %v15672}673 674define <16 x i16> @test_buildvector_16i16_2_load(ptr %p0, ptr %p1) {675; AVX1-32-LABEL: test_buildvector_16i16_2_load:676; AVX1-32: # %bb.0:677; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %ecx678; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %eax679; AVX1-32-NEXT: movzwl (%eax), %eax680; AVX1-32-NEXT: movzwl (%ecx), %ecx681; AVX1-32-NEXT: vmovd %ecx, %xmm0682; AVX1-32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0683; AVX1-32-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0684; AVX1-32-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0685; AVX1-32-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0686; AVX1-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0687; AVX1-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0688; AVX1-32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0689; AVX1-32-NEXT: vmovd %eax, %xmm1690; AVX1-32-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1691; AVX1-32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1692; AVX1-32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1693; AVX1-32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1694; AVX1-32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1695; AVX1-32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1696; AVX1-32-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1697; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0698; AVX1-32-NEXT: retl699;700; AVX1-64-LABEL: test_buildvector_16i16_2_load:701; AVX1-64: # %bb.0:702; AVX1-64-NEXT: movzwl (%rdi), %eax703; AVX1-64-NEXT: movzwl (%rsi), %ecx704; AVX1-64-NEXT: vmovd %ecx, %xmm0705; AVX1-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0706; AVX1-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0707; AVX1-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0708; AVX1-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0709; AVX1-64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0710; AVX1-64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0711; AVX1-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0712; AVX1-64-NEXT: vmovd %eax, %xmm1713; AVX1-64-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1714; AVX1-64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1715; AVX1-64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1716; AVX1-64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1717; AVX1-64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1718; AVX1-64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1719; AVX1-64-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1720; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0721; AVX1-64-NEXT: retq722;723; AVX2-32-LABEL: test_buildvector_16i16_2_load:724; AVX2-32: # %bb.0:725; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx726; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %eax727; AVX2-32-NEXT: movzwl (%eax), %eax728; AVX2-32-NEXT: movzwl (%ecx), %ecx729; AVX2-32-NEXT: vmovd %ecx, %xmm0730; AVX2-32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0731; AVX2-32-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0732; AVX2-32-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0733; AVX2-32-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0734; AVX2-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0735; AVX2-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0736; AVX2-32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0737; AVX2-32-NEXT: vmovd %eax, %xmm1738; AVX2-32-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1739; AVX2-32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1740; AVX2-32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1741; AVX2-32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1742; AVX2-32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1743; AVX2-32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1744; AVX2-32-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1745; AVX2-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0746; AVX2-32-NEXT: retl747;748; AVX2-64-LABEL: test_buildvector_16i16_2_load:749; AVX2-64: # %bb.0:750; AVX2-64-NEXT: movzwl (%rdi), %eax751; AVX2-64-NEXT: movzwl (%rsi), %ecx752; AVX2-64-NEXT: vmovd %ecx, %xmm0753; AVX2-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0754; AVX2-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0755; AVX2-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0756; AVX2-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0757; AVX2-64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0758; AVX2-64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0759; AVX2-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0760; AVX2-64-NEXT: vmovd %eax, %xmm1761; AVX2-64-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1762; AVX2-64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1763; AVX2-64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1764; AVX2-64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1765; AVX2-64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1766; AVX2-64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1767; AVX2-64-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1768; AVX2-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0769; AVX2-64-NEXT: retq770 %a0 = load i16, ptr %p0771 %a1 = load i16, ptr %p1772 %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0773 %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1774 %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2775 %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3776 %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4777 %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5778 %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6779 %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7780 %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8781 %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9782 %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10783 %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11784 %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12785 %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13786 %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14787 %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15788 ret <16 x i16> %v15789}790 791; PR30780792 793define <8 x i32> @test_buildvector_v8i32_splat_sext_i8(i8 %in) {794; AVX1-32-LABEL: test_buildvector_v8i32_splat_sext_i8:795; AVX1-32: # %bb.0:796; AVX1-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax797; AVX1-32-NEXT: vmovd %eax, %xmm0798; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]799; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0800; AVX1-32-NEXT: retl801;802; AVX1-64-LABEL: test_buildvector_v8i32_splat_sext_i8:803; AVX1-64: # %bb.0:804; AVX1-64-NEXT: movsbl %dil, %eax805; AVX1-64-NEXT: vmovd %eax, %xmm0806; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]807; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0808; AVX1-64-NEXT: retq809;810; AVX2-32-LABEL: test_buildvector_v8i32_splat_sext_i8:811; AVX2-32: # %bb.0:812; AVX2-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax813; AVX2-32-NEXT: vmovd %eax, %xmm0814; AVX2-32-NEXT: vpbroadcastd %xmm0, %ymm0815; AVX2-32-NEXT: retl816;817; AVX2-64-LABEL: test_buildvector_v8i32_splat_sext_i8:818; AVX2-64: # %bb.0:819; AVX2-64-NEXT: movsbl %dil, %eax820; AVX2-64-NEXT: vmovd %eax, %xmm0821; AVX2-64-NEXT: vpbroadcastd %xmm0, %ymm0822; AVX2-64-NEXT: retq823 %ext = sext i8 %in to i32824 %insert = insertelement <8 x i32> undef, i32 %ext, i32 0825 %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer826 ret <8 x i32> %splat827}828 829define <8 x i32> @test_buildvector_v8i32_splat_zext_i8(i8 %in) {830; AVX1-32-LABEL: test_buildvector_v8i32_splat_zext_i8:831; AVX1-32: # %bb.0:832; AVX1-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax833; AVX1-32-NEXT: vmovd %eax, %xmm0834; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]835; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0836; AVX1-32-NEXT: retl837;838; AVX1-64-LABEL: test_buildvector_v8i32_splat_zext_i8:839; AVX1-64: # %bb.0:840; AVX1-64-NEXT: movzbl %dil, %eax841; AVX1-64-NEXT: vmovd %eax, %xmm0842; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]843; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0844; AVX1-64-NEXT: retq845;846; AVX2-32-LABEL: test_buildvector_v8i32_splat_zext_i8:847; AVX2-32: # %bb.0:848; AVX2-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax849; AVX2-32-NEXT: vmovd %eax, %xmm0850; AVX2-32-NEXT: vpbroadcastd %xmm0, %ymm0851; AVX2-32-NEXT: retl852;853; AVX2-64-LABEL: test_buildvector_v8i32_splat_zext_i8:854; AVX2-64: # %bb.0:855; AVX2-64-NEXT: movzbl %dil, %eax856; AVX2-64-NEXT: vmovd %eax, %xmm0857; AVX2-64-NEXT: vpbroadcastd %xmm0, %ymm0858; AVX2-64-NEXT: retq859 %ext = zext i8 %in to i32860 %insert = insertelement <8 x i32> undef, i32 %ext, i32 0861 %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer862 ret <8 x i32> %splat863}864 865