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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX-32,AVX512F-323; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX-64,AVX512F-644; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX-32,AVX512BW-325; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX-64,AVX512BW-646 7define <8 x double> @test_buildvector_v8f64(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7) {8; AVX-32-LABEL: test_buildvector_v8f64:9; AVX-32: # %bb.0:10; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm011; AVX-32-NEXT: retl12;13; AVX-64-LABEL: test_buildvector_v8f64:14; AVX-64: # %bb.0:15; AVX-64-NEXT: vmovlhps {{.*#+}} xmm6 = xmm6[0],xmm7[0]16; AVX-64-NEXT: vmovlhps {{.*#+}} xmm4 = xmm4[0],xmm5[0]17; AVX-64-NEXT: vinsertf128 $1, %xmm6, %ymm4, %ymm418; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]19; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]20; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm021; AVX-64-NEXT: vinsertf64x4 $1, %ymm4, %zmm0, %zmm022; AVX-64-NEXT: retq23 %ins0 = insertelement <8 x double> undef, double %a0, i32 024 %ins1 = insertelement <8 x double> %ins0, double %a1, i32 125 %ins2 = insertelement <8 x double> %ins1, double %a2, i32 226 %ins3 = insertelement <8 x double> %ins2, double %a3, i32 327 %ins4 = insertelement <8 x double> %ins3, double %a4, i32 428 %ins5 = insertelement <8 x double> %ins4, double %a5, i32 529 %ins6 = insertelement <8 x double> %ins5, double %a6, i32 630 %ins7 = insertelement <8 x double> %ins6, double %a7, i32 731 ret <8 x double> %ins732}33 34define <16 x float> @test_buildvector_v16f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15) {35; AVX-32-LABEL: test_buildvector_v16f32:36; AVX-32: # %bb.0:37; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm038; AVX-32-NEXT: retl39;40; AVX-64-LABEL: test_buildvector_v16f32:41; AVX-64: # %bb.0:42; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]43; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]44; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]45; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]46; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]47; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]48; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm049; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero50; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]51; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]52; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]53; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero54; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]55; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]56; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]57; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm158; AVX-64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm059; AVX-64-NEXT: retq60 %ins0 = insertelement <16 x float> undef, float %a0, i32 061 %ins1 = insertelement <16 x float> %ins0, float %a1, i32 162 %ins2 = insertelement <16 x float> %ins1, float %a2, i32 263 %ins3 = insertelement <16 x float> %ins2, float %a3, i32 364 %ins4 = insertelement <16 x float> %ins3, float %a4, i32 465 %ins5 = insertelement <16 x float> %ins4, float %a5, i32 566 %ins6 = insertelement <16 x float> %ins5, float %a6, i32 667 %ins7 = insertelement <16 x float> %ins6, float %a7, i32 768 %ins8 = insertelement <16 x float> %ins7, float %a8, i32 869 %ins9 = insertelement <16 x float> %ins8, float %a9, i32 970 %ins10 = insertelement <16 x float> %ins9, float %a10, i32 1071 %ins11 = insertelement <16 x float> %ins10, float %a11, i32 1172 %ins12 = insertelement <16 x float> %ins11, float %a12, i32 1273 %ins13 = insertelement <16 x float> %ins12, float %a13, i32 1374 %ins14 = insertelement <16 x float> %ins13, float %a14, i32 1475 %ins15 = insertelement <16 x float> %ins14, float %a15, i32 1576 ret <16 x float> %ins1577}78 79define <8 x i64> @test_buildvector_v8i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7) {80; AVX-32-LABEL: test_buildvector_v8i64:81; AVX-32: # %bb.0:82; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm083; AVX-32-NEXT: retl84;85; AVX-64-LABEL: test_buildvector_v8i64:86; AVX-64: # %bb.0:87; AVX-64-NEXT: vmovq %rcx, %xmm088; AVX-64-NEXT: vmovq %rdx, %xmm189; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]90; AVX-64-NEXT: vmovq %rsi, %xmm191; AVX-64-NEXT: vmovq %rdi, %xmm292; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]93; AVX-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm094; AVX-64-NEXT: vmovq %r9, %xmm195; AVX-64-NEXT: vmovq %r8, %xmm296; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]97; AVX-64-NEXT: vinserti128 $1, {{[0-9]+}}(%rsp), %ymm1, %ymm198; AVX-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm099; AVX-64-NEXT: retq100 %ins0 = insertelement <8 x i64> undef, i64 %a0, i32 0101 %ins1 = insertelement <8 x i64> %ins0, i64 %a1, i32 1102 %ins2 = insertelement <8 x i64> %ins1, i64 %a2, i32 2103 %ins3 = insertelement <8 x i64> %ins2, i64 %a3, i32 3104 %ins4 = insertelement <8 x i64> %ins3, i64 %a4, i32 4105 %ins5 = insertelement <8 x i64> %ins4, i64 %a5, i32 5106 %ins6 = insertelement <8 x i64> %ins5, i64 %a6, i32 6107 %ins7 = insertelement <8 x i64> %ins6, i64 %a7, i32 7108 ret <8 x i64> %ins7109}110 111define <16 x i32> @test_buildvector_v16i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) {112; AVX-32-LABEL: test_buildvector_v16i32:113; AVX-32: # %bb.0:114; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0115; AVX-32-NEXT: retl116;117; AVX-64-LABEL: test_buildvector_v16i32:118; AVX-64: # %bb.0:119; AVX-64-NEXT: vmovd %edi, %xmm0120; AVX-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0121; AVX-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0122; AVX-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0123; AVX-64-NEXT: vmovd %r8d, %xmm1124; AVX-64-NEXT: vpinsrd $1, %r9d, %xmm1, %xmm1125; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1126; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1127; AVX-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0128; AVX-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero129; AVX-64-NEXT: vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1130; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1131; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1132; AVX-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero133; AVX-64-NEXT: vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2134; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2135; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2136; AVX-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1137; AVX-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0138; AVX-64-NEXT: retq139 %ins0 = insertelement <16 x i32> undef, i32 %a0, i32 0140 %ins1 = insertelement <16 x i32> %ins0, i32 %a1, i32 1141 %ins2 = insertelement <16 x i32> %ins1, i32 %a2, i32 2142 %ins3 = insertelement <16 x i32> %ins2, i32 %a3, i32 3143 %ins4 = insertelement <16 x i32> %ins3, i32 %a4, i32 4144 %ins5 = insertelement <16 x i32> %ins4, i32 %a5, i32 5145 %ins6 = insertelement <16 x i32> %ins5, i32 %a6, i32 6146 %ins7 = insertelement <16 x i32> %ins6, i32 %a7, i32 7147 %ins8 = insertelement <16 x i32> %ins7, i32 %a8, i32 8148 %ins9 = insertelement <16 x i32> %ins8, i32 %a9, i32 9149 %ins10 = insertelement <16 x i32> %ins9, i32 %a10, i32 10150 %ins11 = insertelement <16 x i32> %ins10, i32 %a11, i32 11151 %ins12 = insertelement <16 x i32> %ins11, i32 %a12, i32 12152 %ins13 = insertelement <16 x i32> %ins12, i32 %a13, i32 13153 %ins14 = insertelement <16 x i32> %ins13, i32 %a14, i32 14154 %ins15 = insertelement <16 x i32> %ins14, i32 %a15, i32 15155 ret <16 x i32> %ins15156}157 158define <32 x i16> @test_buildvector_v32i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15, i16 %a16, i16 %a17, i16 %a18, i16 %a19, i16 %a20, i16 %a21, i16 %a22, i16 %a23, i16 %a24, i16 %a25, i16 %a26, i16 %a27, i16 %a28, i16 %a29, i16 %a30, i16 %a31) {159; AVX-32-LABEL: test_buildvector_v32i16:160; AVX-32: # %bb.0:161; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero162; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0163; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0164; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0165; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0166; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0167; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0168; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0169; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero170; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1171; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1172; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1173; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1174; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1175; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1176; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1177; AVX-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0178; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero179; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1180; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1181; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1182; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1183; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1184; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1185; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1186; AVX-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero187; AVX-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm2, %xmm2188; AVX-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm2, %xmm2189; AVX-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm2, %xmm2190; AVX-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm2, %xmm2191; AVX-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm2, %xmm2192; AVX-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm2, %xmm2193; AVX-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm2, %xmm2194; AVX-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1195; AVX-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0196; AVX-32-NEXT: retl197;198; AVX-64-LABEL: test_buildvector_v32i16:199; AVX-64: # %bb.0:200; AVX-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero201; AVX-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0202; AVX-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0203; AVX-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0204; AVX-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0205; AVX-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0206; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0207; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0208; AVX-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero209; AVX-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1210; AVX-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1211; AVX-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1212; AVX-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1213; AVX-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1214; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1215; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1216; AVX-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0217; AVX-64-NEXT: vmovd %edi, %xmm1218; AVX-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1219; AVX-64-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1220; AVX-64-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1221; AVX-64-NEXT: vpinsrw $4, %r8d, %xmm1, %xmm1222; AVX-64-NEXT: vpinsrw $5, %r9d, %xmm1, %xmm1223; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1224; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1225; AVX-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero226; AVX-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2227; AVX-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2228; AVX-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2229; AVX-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2230; AVX-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2231; AVX-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2232; AVX-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2233; AVX-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1234; AVX-64-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0235; AVX-64-NEXT: retq236 %ins0 = insertelement <32 x i16> undef, i16 %a0, i32 0237 %ins1 = insertelement <32 x i16> %ins0, i16 %a1, i32 1238 %ins2 = insertelement <32 x i16> %ins1, i16 %a2, i32 2239 %ins3 = insertelement <32 x i16> %ins2, i16 %a3, i32 3240 %ins4 = insertelement <32 x i16> %ins3, i16 %a4, i32 4241 %ins5 = insertelement <32 x i16> %ins4, i16 %a5, i32 5242 %ins6 = insertelement <32 x i16> %ins5, i16 %a6, i32 6243 %ins7 = insertelement <32 x i16> %ins6, i16 %a7, i32 7244 %ins8 = insertelement <32 x i16> %ins7, i16 %a8, i32 8245 %ins9 = insertelement <32 x i16> %ins8, i16 %a9, i32 9246 %ins10 = insertelement <32 x i16> %ins9, i16 %a10, i32 10247 %ins11 = insertelement <32 x i16> %ins10, i16 %a11, i32 11248 %ins12 = insertelement <32 x i16> %ins11, i16 %a12, i32 12249 %ins13 = insertelement <32 x i16> %ins12, i16 %a13, i32 13250 %ins14 = insertelement <32 x i16> %ins13, i16 %a14, i32 14251 %ins15 = insertelement <32 x i16> %ins14, i16 %a15, i32 15252 %ins16 = insertelement <32 x i16> %ins15, i16 %a16, i32 16253 %ins17 = insertelement <32 x i16> %ins16, i16 %a17, i32 17254 %ins18 = insertelement <32 x i16> %ins17, i16 %a18, i32 18255 %ins19 = insertelement <32 x i16> %ins18, i16 %a19, i32 19256 %ins20 = insertelement <32 x i16> %ins19, i16 %a20, i32 20257 %ins21 = insertelement <32 x i16> %ins20, i16 %a21, i32 21258 %ins22 = insertelement <32 x i16> %ins21, i16 %a22, i32 22259 %ins23 = insertelement <32 x i16> %ins22, i16 %a23, i32 23260 %ins24 = insertelement <32 x i16> %ins23, i16 %a24, i32 24261 %ins25 = insertelement <32 x i16> %ins24, i16 %a25, i32 25262 %ins26 = insertelement <32 x i16> %ins25, i16 %a26, i32 26263 %ins27 = insertelement <32 x i16> %ins26, i16 %a27, i32 27264 %ins28 = insertelement <32 x i16> %ins27, i16 %a28, i32 28265 %ins29 = insertelement <32 x i16> %ins28, i16 %a29, i32 29266 %ins30 = insertelement <32 x i16> %ins29, i16 %a30, i32 30267 %ins31 = insertelement <32 x i16> %ins30, i16 %a31, i32 31268 ret <32 x i16> %ins31269}270 271define <64 x i8> @test_buildvector_v64i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31, i8 %a32, i8 %a33, i8 %a34, i8 %a35, i8 %a36, i8 %a37, i8 %a38, i8 %a39, i8 %a40, i8 %a41, i8 %a42, i8 %a43, i8 %a44, i8 %a45, i8 %a46, i8 %a47, i8 %a48, i8 %a49, i8 %a50, i8 %a51, i8 %a52, i8 %a53, i8 %a54, i8 %a55, i8 %a56, i8 %a57, i8 %a58, i8 %a59, i8 %a60, i8 %a61, i8 %a62, i8 %a63) {272; AVX-32-LABEL: test_buildvector_v64i8:273; AVX-32: # %bb.0:274; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero275; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0276; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0277; AVX-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0278; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0279; AVX-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0280; AVX-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0281; AVX-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0282; AVX-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0283; AVX-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0284; AVX-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0285; AVX-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0286; AVX-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0287; AVX-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0288; AVX-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0289; AVX-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0290; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero291; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1292; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1293; AVX-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1294; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1295; AVX-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1296; AVX-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1297; AVX-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1298; AVX-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1299; AVX-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1300; AVX-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1301; AVX-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1302; AVX-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1303; AVX-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1304; AVX-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1305; AVX-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1306; AVX-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0307; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero308; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1309; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1310; AVX-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1311; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1312; AVX-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1313; AVX-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1314; AVX-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1315; AVX-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1316; AVX-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1317; AVX-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1318; AVX-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1319; AVX-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1320; AVX-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1321; AVX-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1322; AVX-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1323; AVX-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero324; AVX-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm2, %xmm2325; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm2, %xmm2326; AVX-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm2, %xmm2327; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm2, %xmm2328; AVX-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm2, %xmm2329; AVX-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm2, %xmm2330; AVX-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm2, %xmm2331; AVX-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm2, %xmm2332; AVX-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm2, %xmm2333; AVX-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm2, %xmm2334; AVX-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm2, %xmm2335; AVX-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm2, %xmm2336; AVX-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm2, %xmm2337; AVX-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm2, %xmm2338; AVX-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm2, %xmm2339; AVX-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1340; AVX-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0341; AVX-32-NEXT: retl342;343; AVX-64-LABEL: test_buildvector_v64i8:344; AVX-64: # %bb.0:345; AVX-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero346; AVX-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0347; AVX-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0348; AVX-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0349; AVX-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0350; AVX-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0351; AVX-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0352; AVX-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0353; AVX-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0354; AVX-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0355; AVX-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0356; AVX-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0357; AVX-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0358; AVX-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0359; AVX-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0360; AVX-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0361; AVX-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero362; AVX-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1363; AVX-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1364; AVX-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1365; AVX-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1366; AVX-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1367; AVX-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1368; AVX-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1369; AVX-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1370; AVX-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1371; AVX-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1372; AVX-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1373; AVX-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1374; AVX-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1375; AVX-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1376; AVX-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1377; AVX-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0378; AVX-64-NEXT: vmovd %edi, %xmm1379; AVX-64-NEXT: vpinsrb $1, %esi, %xmm1, %xmm1380; AVX-64-NEXT: vpinsrb $2, %edx, %xmm1, %xmm1381; AVX-64-NEXT: vpinsrb $3, %ecx, %xmm1, %xmm1382; AVX-64-NEXT: vpinsrb $4, %r8d, %xmm1, %xmm1383; AVX-64-NEXT: vpinsrb $5, %r9d, %xmm1, %xmm1384; AVX-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1385; AVX-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1386; AVX-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1387; AVX-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1388; AVX-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1389; AVX-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1390; AVX-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1391; AVX-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1392; AVX-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1393; AVX-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1394; AVX-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero395; AVX-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2396; AVX-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2397; AVX-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2398; AVX-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2399; AVX-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2400; AVX-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2401; AVX-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2402; AVX-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2403; AVX-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2404; AVX-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2405; AVX-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2406; AVX-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2407; AVX-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2408; AVX-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2409; AVX-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2410; AVX-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1411; AVX-64-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0412; AVX-64-NEXT: retq413 %ins0 = insertelement <64 x i8> undef, i8 %a0, i32 0414 %ins1 = insertelement <64 x i8> %ins0, i8 %a1, i32 1415 %ins2 = insertelement <64 x i8> %ins1, i8 %a2, i32 2416 %ins3 = insertelement <64 x i8> %ins2, i8 %a3, i32 3417 %ins4 = insertelement <64 x i8> %ins3, i8 %a4, i32 4418 %ins5 = insertelement <64 x i8> %ins4, i8 %a5, i32 5419 %ins6 = insertelement <64 x i8> %ins5, i8 %a6, i32 6420 %ins7 = insertelement <64 x i8> %ins6, i8 %a7, i32 7421 %ins8 = insertelement <64 x i8> %ins7, i8 %a8, i32 8422 %ins9 = insertelement <64 x i8> %ins8, i8 %a9, i32 9423 %ins10 = insertelement <64 x i8> %ins9, i8 %a10, i32 10424 %ins11 = insertelement <64 x i8> %ins10, i8 %a11, i32 11425 %ins12 = insertelement <64 x i8> %ins11, i8 %a12, i32 12426 %ins13 = insertelement <64 x i8> %ins12, i8 %a13, i32 13427 %ins14 = insertelement <64 x i8> %ins13, i8 %a14, i32 14428 %ins15 = insertelement <64 x i8> %ins14, i8 %a15, i32 15429 %ins16 = insertelement <64 x i8> %ins15, i8 %a16, i32 16430 %ins17 = insertelement <64 x i8> %ins16, i8 %a17, i32 17431 %ins18 = insertelement <64 x i8> %ins17, i8 %a18, i32 18432 %ins19 = insertelement <64 x i8> %ins18, i8 %a19, i32 19433 %ins20 = insertelement <64 x i8> %ins19, i8 %a20, i32 20434 %ins21 = insertelement <64 x i8> %ins20, i8 %a21, i32 21435 %ins22 = insertelement <64 x i8> %ins21, i8 %a22, i32 22436 %ins23 = insertelement <64 x i8> %ins22, i8 %a23, i32 23437 %ins24 = insertelement <64 x i8> %ins23, i8 %a24, i32 24438 %ins25 = insertelement <64 x i8> %ins24, i8 %a25, i32 25439 %ins26 = insertelement <64 x i8> %ins25, i8 %a26, i32 26440 %ins27 = insertelement <64 x i8> %ins26, i8 %a27, i32 27441 %ins28 = insertelement <64 x i8> %ins27, i8 %a28, i32 28442 %ins29 = insertelement <64 x i8> %ins28, i8 %a29, i32 29443 %ins30 = insertelement <64 x i8> %ins29, i8 %a30, i32 30444 %ins31 = insertelement <64 x i8> %ins30, i8 %a31, i32 31445 %ins32 = insertelement <64 x i8> %ins31, i8 %a32, i32 32446 %ins33 = insertelement <64 x i8> %ins32, i8 %a33, i32 33447 %ins34 = insertelement <64 x i8> %ins33, i8 %a34, i32 34448 %ins35 = insertelement <64 x i8> %ins34, i8 %a35, i32 35449 %ins36 = insertelement <64 x i8> %ins35, i8 %a36, i32 36450 %ins37 = insertelement <64 x i8> %ins36, i8 %a37, i32 37451 %ins38 = insertelement <64 x i8> %ins37, i8 %a38, i32 38452 %ins39 = insertelement <64 x i8> %ins38, i8 %a39, i32 39453 %ins40 = insertelement <64 x i8> %ins39, i8 %a40, i32 40454 %ins41 = insertelement <64 x i8> %ins40, i8 %a41, i32 41455 %ins42 = insertelement <64 x i8> %ins41, i8 %a42, i32 42456 %ins43 = insertelement <64 x i8> %ins42, i8 %a43, i32 43457 %ins44 = insertelement <64 x i8> %ins43, i8 %a44, i32 44458 %ins45 = insertelement <64 x i8> %ins44, i8 %a45, i32 45459 %ins46 = insertelement <64 x i8> %ins45, i8 %a46, i32 46460 %ins47 = insertelement <64 x i8> %ins46, i8 %a47, i32 47461 %ins48 = insertelement <64 x i8> %ins47, i8 %a48, i32 48462 %ins49 = insertelement <64 x i8> %ins48, i8 %a49, i32 49463 %ins50 = insertelement <64 x i8> %ins49, i8 %a50, i32 50464 %ins51 = insertelement <64 x i8> %ins50, i8 %a51, i32 51465 %ins52 = insertelement <64 x i8> %ins51, i8 %a52, i32 52466 %ins53 = insertelement <64 x i8> %ins52, i8 %a53, i32 53467 %ins54 = insertelement <64 x i8> %ins53, i8 %a54, i32 54468 %ins55 = insertelement <64 x i8> %ins54, i8 %a55, i32 55469 %ins56 = insertelement <64 x i8> %ins55, i8 %a56, i32 56470 %ins57 = insertelement <64 x i8> %ins56, i8 %a57, i32 57471 %ins58 = insertelement <64 x i8> %ins57, i8 %a58, i32 58472 %ins59 = insertelement <64 x i8> %ins58, i8 %a59, i32 59473 %ins60 = insertelement <64 x i8> %ins59, i8 %a60, i32 60474 %ins61 = insertelement <64 x i8> %ins60, i8 %a61, i32 61475 %ins62 = insertelement <64 x i8> %ins61, i8 %a62, i32 62476 %ins63 = insertelement <64 x i8> %ins62, i8 %a63, i32 63477 ret <64 x i8> %ins63478}479 480; build vectors of repeated elements481 482define <8 x double> @test_buildvector_8f64_2_var(double %a0, double %a1) {483; AVX512F-32-LABEL: test_buildvector_8f64_2_var:484; AVX512F-32: # %bb.0:485; AVX512F-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %zmm0486; AVX512F-32-NEXT: movb $-126, %al487; AVX512F-32-NEXT: kmovw %eax, %k1488; AVX512F-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %zmm0 {%k1}489; AVX512F-32-NEXT: retl490;491; AVX512F-64-LABEL: test_buildvector_8f64_2_var:492; AVX512F-64: # %bb.0:493; AVX512F-64-NEXT: vbroadcastsd %xmm0, %zmm0494; AVX512F-64-NEXT: movb $-126, %al495; AVX512F-64-NEXT: kmovw %eax, %k1496; AVX512F-64-NEXT: vbroadcastsd %xmm1, %zmm0 {%k1}497; AVX512F-64-NEXT: retq498;499; AVX512BW-32-LABEL: test_buildvector_8f64_2_var:500; AVX512BW-32: # %bb.0:501; AVX512BW-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %zmm0502; AVX512BW-32-NEXT: movb $-126, %al503; AVX512BW-32-NEXT: kmovd %eax, %k1504; AVX512BW-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %zmm0 {%k1}505; AVX512BW-32-NEXT: retl506;507; AVX512BW-64-LABEL: test_buildvector_8f64_2_var:508; AVX512BW-64: # %bb.0:509; AVX512BW-64-NEXT: vbroadcastsd %xmm0, %zmm0510; AVX512BW-64-NEXT: movb $-126, %al511; AVX512BW-64-NEXT: kmovd %eax, %k1512; AVX512BW-64-NEXT: vbroadcastsd %xmm1, %zmm0 {%k1}513; AVX512BW-64-NEXT: retq514 %v0 = insertelement <8 x double> poison, double %a0, i32 0515 %v1 = insertelement <8 x double> %v0, double %a1, i32 1516 %v2 = insertelement <8 x double> %v1, double %a0, i32 2517 %v3 = insertelement <8 x double> %v2, double %a0, i32 3518 %v4 = insertelement <8 x double> %v3, double %a0, i32 4519 %v5 = insertelement <8 x double> %v4, double %a0, i32 5520 %v6 = insertelement <8 x double> %v5, double %a0, i32 6521 %v7 = insertelement <8 x double> %v6, double %a1, i32 7522 ret <8 x double> %v7523}524 525define <8 x double> @test_buildvector_8f64_2_load(ptr %p0, ptr %p1) {526; AVX512F-32-LABEL: test_buildvector_8f64_2_load:527; AVX512F-32: # %bb.0:528; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax529; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %ecx530; AVX512F-32-NEXT: vbroadcastsd (%ecx), %zmm0531; AVX512F-32-NEXT: movb $-126, %cl532; AVX512F-32-NEXT: kmovw %ecx, %k1533; AVX512F-32-NEXT: vbroadcastsd (%eax), %zmm0 {%k1}534; AVX512F-32-NEXT: retl535;536; AVX512F-64-LABEL: test_buildvector_8f64_2_load:537; AVX512F-64: # %bb.0:538; AVX512F-64-NEXT: vbroadcastsd (%rdi), %zmm0539; AVX512F-64-NEXT: movb $-126, %al540; AVX512F-64-NEXT: kmovw %eax, %k1541; AVX512F-64-NEXT: vbroadcastsd (%rsi), %zmm0 {%k1}542; AVX512F-64-NEXT: retq543;544; AVX512BW-32-LABEL: test_buildvector_8f64_2_load:545; AVX512BW-32: # %bb.0:546; AVX512BW-32-NEXT: movl {{[0-9]+}}(%esp), %eax547; AVX512BW-32-NEXT: movl {{[0-9]+}}(%esp), %ecx548; AVX512BW-32-NEXT: vbroadcastsd (%ecx), %zmm0549; AVX512BW-32-NEXT: movb $-126, %cl550; AVX512BW-32-NEXT: kmovd %ecx, %k1551; AVX512BW-32-NEXT: vbroadcastsd (%eax), %zmm0 {%k1}552; AVX512BW-32-NEXT: retl553;554; AVX512BW-64-LABEL: test_buildvector_8f64_2_load:555; AVX512BW-64: # %bb.0:556; AVX512BW-64-NEXT: vbroadcastsd (%rdi), %zmm0557; AVX512BW-64-NEXT: movb $-126, %al558; AVX512BW-64-NEXT: kmovd %eax, %k1559; AVX512BW-64-NEXT: vbroadcastsd (%rsi), %zmm0 {%k1}560; AVX512BW-64-NEXT: retq561 %a0 = load double, ptr %p0562 %a1 = load double, ptr %p1563 %v0 = insertelement <8 x double> poison, double %a0, i32 0564 %v1 = insertelement <8 x double> %v0, double %a1, i32 1565 %v2 = insertelement <8 x double> %v1, double %a0, i32 2566 %v3 = insertelement <8 x double> %v2, double %a0, i32 3567 %v4 = insertelement <8 x double> %v3, double %a0, i32 4568 %v5 = insertelement <8 x double> %v4, double %a0, i32 5569 %v6 = insertelement <8 x double> %v5, double %a0, i32 6570 %v7 = insertelement <8 x double> %v6, double %a1, i32 7571 ret <8 x double> %v7572}573 574define <16 x float> @test_buildvector_16f32_2_var(float %a0, float %a1) {575; AVX-32-LABEL: test_buildvector_16f32_2_var:576; AVX-32: # %bb.0:577; AVX-32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0578; AVX-32-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,17,0,0]579; AVX-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero580; AVX-32-NEXT: vpermi2ps %zmm0, %zmm2, %zmm1581; AVX-32-NEXT: vmovss {{.*#+}} xmm3 = xmm2[0],xmm0[1,2,3]582; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1583; AVX-32-NEXT: vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm2[0]584; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3]585; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0586; AVX-32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0587; AVX-32-NEXT: retl588;589; AVX-64-LABEL: test_buildvector_16f32_2_var:590; AVX-64: # %bb.0:591; AVX-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1592; AVX-64-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,16,0,0]593; AVX-64-NEXT: vbroadcastss %xmm0, %xmm0594; AVX-64-NEXT: vpermi2ps %zmm1, %zmm0, %zmm2595; AVX-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm1[0]596; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2597; AVX-64-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,16,0,0,0,17,18,19]598; AVX-64-NEXT: vpermi2ps %zmm0, %zmm1, %zmm3599; AVX-64-NEXT: vinsertf64x4 $1, %ymm3, %zmm2, %zmm0600; AVX-64-NEXT: retq601 %v0 = insertelement <16 x float> poison, float %a0, i32 0602 %v1 = insertelement <16 x float> %v0, float %a1, i32 1603 %v2 = insertelement <16 x float> %v1, float %a0, i32 2604 %v3 = insertelement <16 x float> %v2, float %a0, i32 3605 %v4 = insertelement <16 x float> %v3, float %a0, i32 4606 %v5 = insertelement <16 x float> %v4, float %a0, i32 5607 %v6 = insertelement <16 x float> %v5, float %a0, i32 6608 %v7 = insertelement <16 x float> %v6, float %a1, i32 7609 %v8 = insertelement <16 x float> %v7, float %a1, i32 8610 %v9 = insertelement <16 x float> %v8, float %a0, i32 9611 %v10 = insertelement <16 x float> %v9, float %a1, i32 10612 %v11 = insertelement <16 x float> %v10, float %a1, i32 11613 %v12 = insertelement <16 x float> %v11, float %a1, i32 12614 %v13 = insertelement <16 x float> %v12, float %a0, i32 13615 %v14 = insertelement <16 x float> %v13, float %a0, i32 14616 %v15 = insertelement <16 x float> %v14, float %a0, i32 15617 ret <16 x float> %v15618}619 620define <16 x float> @test_buildvector_16f32_2_load(ptr %p0, ptr %p1) {621; AVX-32-LABEL: test_buildvector_16f32_2_load:622; AVX-32: # %bb.0:623; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax624; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx625; AVX-32-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]626; AVX-32-NEXT: vbroadcastss (%ecx), %xmm1627; AVX-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero628; AVX-32-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0629; AVX-32-NEXT: vmovss {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]630; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0631; AVX-32-NEXT: vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]632; AVX-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]633; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1634; AVX-32-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0635; AVX-32-NEXT: retl636;637; AVX-64-LABEL: test_buildvector_16f32_2_load:638; AVX-64: # %bb.0:639; AVX-64-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]640; AVX-64-NEXT: vbroadcastss (%rdi), %xmm1641; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero642; AVX-64-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0643; AVX-64-NEXT: vmovss {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]644; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0645; AVX-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]646; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]647; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1648; AVX-64-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0649; AVX-64-NEXT: retq650 %a0 = load float, ptr %p0651 %a1 = load float, ptr %p1652 %v0 = insertelement <16 x float> poison, float %a0, i32 0653 %v1 = insertelement <16 x float> %v0, float %a1, i32 1654 %v2 = insertelement <16 x float> %v1, float %a0, i32 2655 %v3 = insertelement <16 x float> %v2, float %a0, i32 3656 %v4 = insertelement <16 x float> %v3, float %a0, i32 4657 %v5 = insertelement <16 x float> %v4, float %a0, i32 5658 %v6 = insertelement <16 x float> %v5, float %a0, i32 6659 %v7 = insertelement <16 x float> %v6, float %a1, i32 7660 %v8 = insertelement <16 x float> %v7, float %a1, i32 8661 %v9 = insertelement <16 x float> %v8, float %a0, i32 9662 %v10 = insertelement <16 x float> %v9, float %a1, i32 10663 %v11 = insertelement <16 x float> %v10, float %a1, i32 11664 %v12 = insertelement <16 x float> %v11, float %a1, i32 12665 %v13 = insertelement <16 x float> %v12, float %a0, i32 13666 %v14 = insertelement <16 x float> %v13, float %a0, i32 14667 %v15 = insertelement <16 x float> %v14, float %a0, i32 15668 ret <16 x float> %v15669}670