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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX15; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX26 7define void @foo(<3 x float> %in, ptr nocapture %out) nounwind {8; SSE2-LABEL: foo:9; SSE2: # %bb.0:10; SSE2-NEXT: cvttps2dq %xmm0, %xmm011; SSE2-NEXT: packuswb %xmm0, %xmm012; SSE2-NEXT: packuswb %xmm0, %xmm013; SSE2-NEXT: movd %xmm0, %eax14; SSE2-NEXT: orl $-16777216, %eax # imm = 0xFF00000015; SSE2-NEXT: movl %eax, (%rdi)16; SSE2-NEXT: retq17;18; SSE41-LABEL: foo:19; SSE41: # %bb.0:20; SSE41-NEXT: cvttps2dq %xmm0, %xmm021; SSE41-NEXT: packusdw %xmm0, %xmm022; SSE41-NEXT: packuswb %xmm0, %xmm023; SSE41-NEXT: movl $255, %eax24; SSE41-NEXT: pinsrb $3, %eax, %xmm025; SSE41-NEXT: movd %xmm0, (%rdi)26; SSE41-NEXT: retq27;28; AVX-LABEL: foo:29; AVX: # %bb.0:30; AVX-NEXT: vcvttps2dq %xmm0, %xmm031; AVX-NEXT: vpackusdw %xmm0, %xmm0, %xmm032; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm033; AVX-NEXT: movl $255, %eax34; AVX-NEXT: vpinsrb $3, %eax, %xmm0, %xmm035; AVX-NEXT: vmovd %xmm0, (%rdi)36; AVX-NEXT: retq37 %t0 = fptoui <3 x float> %in to <3 x i8>38 %t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>39 %t2 = insertelement <4 x i8> %t1, i8 -1, i32 340 store <4 x i8> %t2, ptr %out, align 441 ret void42}43 44; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a45; blend with a zero vector if the build_vector contains negative zero.46 47define <4 x float> @test_negative_zero_1(<4 x float> %A) {48; SSE2-LABEL: test_negative_zero_1:49; SSE2: # %bb.0: # %entry50; SSE2-NEXT: xorps %xmm1, %xmm151; SSE2-NEXT: movaps %xmm0, %xmm252; SSE2-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]53; SSE2-NEXT: movss {{.*#+}} xmm1 = [-0.0E+0,0.0E+0,0.0E+0,0.0E+0]54; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]55; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]56; SSE2-NEXT: retq57;58; SSE41-LABEL: test_negative_zero_1:59; SSE41: # %bb.0: # %entry60; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero61; SSE41-NEXT: retq62;63; AVX-LABEL: test_negative_zero_1:64; AVX: # %bb.0: # %entry65; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero66; AVX-NEXT: retq67entry:68 %0 = extractelement <4 x float> %A, i32 069 %1 = insertelement <4 x float> undef, float %0, i32 070 %2 = insertelement <4 x float> %1, float -0.0, i32 171 %3 = extractelement <4 x float> %A, i32 272 %4 = insertelement <4 x float> %2, float %3, i32 273 %5 = insertelement <4 x float> %4, float 0.0, i32 374 ret <4 x float> %575}76 77; FIXME: This could be 'movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]'.78 79define <2 x double> @test_negative_zero_2(<2 x double> %A) {80; SSE2-LABEL: test_negative_zero_2:81; SSE2: # %bb.0: # %entry82; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1]83; SSE2-NEXT: retq84;85; SSE41-LABEL: test_negative_zero_2:86; SSE41: # %bb.0: # %entry87; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]88; SSE41-NEXT: retq89;90; AVX-LABEL: test_negative_zero_2:91; AVX: # %bb.0: # %entry92; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]93; AVX-NEXT: retq94entry:95 %0 = extractelement <2 x double> %A, i32 096 %1 = insertelement <2 x double> undef, double %0, i32 097 %2 = insertelement <2 x double> %1, double -0.0, i32 198 ret <2 x double> %299}100 101define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float %f2, float %f3) {102; SSE2-LABEL: test_buildvector_v4f32_register:103; SSE2: # %bb.0:104; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]105; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]106; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]107; SSE2-NEXT: retq108;109; SSE41-LABEL: test_buildvector_v4f32_register:110; SSE41: # %bb.0:111; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]112; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]113; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]114; SSE41-NEXT: retq115;116; AVX-LABEL: test_buildvector_v4f32_register:117; AVX: # %bb.0:118; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]119; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]120; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]121; AVX-NEXT: retq122 %ins0 = insertelement <4 x float> undef, float %f0, i32 0123 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1124 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2125 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3126 ret <4 x float> %ins3127}128 129define <4 x float> @test_buildvector_v4f32_load(ptr %p0, ptr %p1, ptr %p2, ptr %p3) {130; SSE2-LABEL: test_buildvector_v4f32_load:131; SSE2: # %bb.0:132; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero133; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero134; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]135; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero136; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero137; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]138; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]139; SSE2-NEXT: retq140;141; SSE41-LABEL: test_buildvector_v4f32_load:142; SSE41: # %bb.0:143; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero144; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]145; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]146; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]147; SSE41-NEXT: retq148;149; AVX-LABEL: test_buildvector_v4f32_load:150; AVX: # %bb.0:151; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero152; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]153; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]154; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]155; AVX-NEXT: retq156 %f0 = load float, ptr %p0, align 4157 %f1 = load float, ptr %p1, align 4158 %f2 = load float, ptr %p2, align 4159 %f3 = load float, ptr %p3, align 4160 %ins0 = insertelement <4 x float> undef, float %f0, i32 0161 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1162 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2163 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3164 ret <4 x float> %ins3165}166 167define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, ptr %p3) {168; SSE2-LABEL: test_buildvector_v4f32_partial_load:169; SSE2: # %bb.0:170; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero171; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]172; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]173; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]174; SSE2-NEXT: retq175;176; SSE41-LABEL: test_buildvector_v4f32_partial_load:177; SSE41: # %bb.0:178; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]179; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]180; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]181; SSE41-NEXT: retq182;183; AVX-LABEL: test_buildvector_v4f32_partial_load:184; AVX: # %bb.0:185; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]186; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]187; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]188; AVX-NEXT: retq189 %f3 = load float, ptr %p3, align 4190 %ins0 = insertelement <4 x float> undef, float %f0, i32 0191 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1192 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2193 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3194 ret <4 x float> %ins3195}196 197define <4 x i32> @test_buildvector_v4i32_register(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {198; SSE2-LABEL: test_buildvector_v4i32_register:199; SSE2: # %bb.0:200; SSE2-NEXT: movd %ecx, %xmm0201; SSE2-NEXT: movd %edx, %xmm1202; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]203; SSE2-NEXT: movd %esi, %xmm2204; SSE2-NEXT: movd %edi, %xmm0205; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]206; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]207; SSE2-NEXT: retq208;209; SSE41-LABEL: test_buildvector_v4i32_register:210; SSE41: # %bb.0:211; SSE41-NEXT: movd %edi, %xmm0212; SSE41-NEXT: pinsrd $1, %esi, %xmm0213; SSE41-NEXT: pinsrd $2, %edx, %xmm0214; SSE41-NEXT: pinsrd $3, %ecx, %xmm0215; SSE41-NEXT: retq216;217; AVX-LABEL: test_buildvector_v4i32_register:218; AVX: # %bb.0:219; AVX-NEXT: vmovd %edi, %xmm0220; AVX-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0221; AVX-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0222; AVX-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0223; AVX-NEXT: retq224 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0225 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1226 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2227 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3228 ret <4 x i32> %ins3229}230 231define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) {232; SSE2-LABEL: test_buildvector_v4i32_partial:233; SSE2: # %bb.0:234; SSE2-NEXT: movd %edi, %xmm0235; SSE2-NEXT: movd %esi, %xmm1236; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]237; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]238; SSE2-NEXT: retq239;240; SSE41-LABEL: test_buildvector_v4i32_partial:241; SSE41: # %bb.0:242; SSE41-NEXT: movd %edi, %xmm0243; SSE41-NEXT: pinsrd $3, %esi, %xmm0244; SSE41-NEXT: retq245;246; AVX-LABEL: test_buildvector_v4i32_partial:247; AVX: # %bb.0:248; AVX-NEXT: vmovd %edi, %xmm0249; AVX-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0250; AVX-NEXT: retq251 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0252 %ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1253 %ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2254 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3255 ret <4 x i32> %ins3256}257 258define <4 x i32> @test_buildvector_v4i32_register_zero(i32 %a0, i32 %a2, i32 %a3) {259; SSE-LABEL: test_buildvector_v4i32_register_zero:260; SSE: # %bb.0:261; SSE-NEXT: movd %edx, %xmm0262; SSE-NEXT: movd %esi, %xmm1263; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]264; SSE-NEXT: movd %edi, %xmm0265; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]266; SSE-NEXT: retq267;268; AVX-LABEL: test_buildvector_v4i32_register_zero:269; AVX: # %bb.0:270; AVX-NEXT: vmovd %edx, %xmm0271; AVX-NEXT: vmovd %esi, %xmm1272; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]273; AVX-NEXT: vmovd %edi, %xmm1274; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]275; AVX-NEXT: retq276 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0277 %ins1 = insertelement <4 x i32> %ins0, i32 0, i32 1278 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2279 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3280 ret <4 x i32> %ins3281}282 283define <4 x i32> @test_buildvector_v4i32_register_zero_2(i32 %a1, i32 %a2, i32 %a3) {284; SSE-LABEL: test_buildvector_v4i32_register_zero_2:285; SSE: # %bb.0:286; SSE-NEXT: movd %edx, %xmm0287; SSE-NEXT: movd %esi, %xmm1288; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]289; SSE-NEXT: movd %edi, %xmm0290; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]291; SSE-NEXT: retq292;293; AVX-LABEL: test_buildvector_v4i32_register_zero_2:294; AVX: # %bb.0:295; AVX-NEXT: vmovd %edx, %xmm0296; AVX-NEXT: vmovd %esi, %xmm1297; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]298; AVX-NEXT: vmovd %edi, %xmm1299; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,0],xmm0[0,1]300; AVX-NEXT: retq301 %ins0 = insertelement <4 x i32> undef, i32 0, i32 0302 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1303 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2304 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3305 ret <4 x i32> %ins3306}307 308define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) {309; SSE2-LABEL: test_buildvector_v8i16_register:310; SSE2: # %bb.0:311; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero312; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero313; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]314; SSE2-NEXT: movd %r9d, %xmm0315; SSE2-NEXT: movd %r8d, %xmm2316; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]317; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]318; SSE2-NEXT: movd %ecx, %xmm0319; SSE2-NEXT: movd %edx, %xmm1320; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]321; SSE2-NEXT: movd %esi, %xmm3322; SSE2-NEXT: movd %edi, %xmm0323; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]324; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]325; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]326; SSE2-NEXT: retq327;328; SSE41-LABEL: test_buildvector_v8i16_register:329; SSE41: # %bb.0:330; SSE41-NEXT: movd %edi, %xmm0331; SSE41-NEXT: pinsrw $1, %esi, %xmm0332; SSE41-NEXT: pinsrw $2, %edx, %xmm0333; SSE41-NEXT: pinsrw $3, %ecx, %xmm0334; SSE41-NEXT: pinsrw $4, %r8d, %xmm0335; SSE41-NEXT: pinsrw $5, %r9d, %xmm0336; SSE41-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0337; SSE41-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0338; SSE41-NEXT: retq339;340; AVX-LABEL: test_buildvector_v8i16_register:341; AVX: # %bb.0:342; AVX-NEXT: vmovd %edi, %xmm0343; AVX-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0344; AVX-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0345; AVX-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0346; AVX-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0347; AVX-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0348; AVX-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0349; AVX-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0350; AVX-NEXT: retq351 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0352 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1353 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2354 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3355 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4356 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5357 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6358 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7359 ret <8 x i16> %ins7360}361 362define <8 x i16> @test_buildvector_v8i16_partial(i16 %a1, i16 %a3, i16 %a4, i16 %a5) {363; SSE-LABEL: test_buildvector_v8i16_partial:364; SSE: # %bb.0:365; SSE-NEXT: pxor %xmm0, %xmm0366; SSE-NEXT: pinsrw $1, %edi, %xmm0367; SSE-NEXT: pinsrw $3, %esi, %xmm0368; SSE-NEXT: pinsrw $4, %edx, %xmm0369; SSE-NEXT: pinsrw $5, %ecx, %xmm0370; SSE-NEXT: retq371;372; AVX-LABEL: test_buildvector_v8i16_partial:373; AVX: # %bb.0:374; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0375; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0376; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0377; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0378; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0379; AVX-NEXT: retq380 %ins0 = insertelement <8 x i16> undef, i16 undef, i32 0381 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1382 %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2383 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3384 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4385 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5386 %ins6 = insertelement <8 x i16> %ins5, i16 undef, i32 6387 %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7388 ret <8 x i16> %ins7389}390 391define <8 x i16> @test_buildvector_v8i16_register_zero(i16 %a0, i16 %a3, i16 %a4, i16 %a5) {392; SSE-LABEL: test_buildvector_v8i16_register_zero:393; SSE: # %bb.0:394; SSE-NEXT: movzwl %di, %eax395; SSE-NEXT: movd %eax, %xmm0396; SSE-NEXT: pinsrw $3, %esi, %xmm0397; SSE-NEXT: pinsrw $4, %edx, %xmm0398; SSE-NEXT: pinsrw $5, %ecx, %xmm0399; SSE-NEXT: retq400;401; AVX-LABEL: test_buildvector_v8i16_register_zero:402; AVX: # %bb.0:403; AVX-NEXT: movzwl %di, %eax404; AVX-NEXT: vmovd %eax, %xmm0405; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0406; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0407; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0408; AVX-NEXT: retq409 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0410 %ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1411 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2412 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3413 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4414 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5415 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6416 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7417 ret <8 x i16> %ins7418}419 420define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) {421; SSE-LABEL: test_buildvector_v8i16_register_zero_2:422; SSE: # %bb.0:423; SSE-NEXT: pxor %xmm0, %xmm0424; SSE-NEXT: pinsrw $1, %edi, %xmm0425; SSE-NEXT: pinsrw $3, %esi, %xmm0426; SSE-NEXT: pinsrw $4, %edx, %xmm0427; SSE-NEXT: pinsrw $5, %ecx, %xmm0428; SSE-NEXT: retq429;430; AVX-LABEL: test_buildvector_v8i16_register_zero_2:431; AVX: # %bb.0:432; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0433; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0434; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0435; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0436; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0437; AVX-NEXT: retq438 %ins0 = insertelement <8 x i16> undef, i16 0, i32 0439 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1440 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2441 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3442 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4443 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5444 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6445 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7446 ret <8 x i16> %ins7447}448 449define <16 x i8> @test_buildvector_v16i8_register(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) {450; SSE2-LABEL: test_buildvector_v16i8_register:451; SSE2: # %bb.0:452; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero453; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero454; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]455; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero456; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero457; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]458; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]459; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero460; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero461; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]462; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero463; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero464; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]465; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]466; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]467; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero468; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero469; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]470; SSE2-NEXT: movd %r9d, %xmm0471; SSE2-NEXT: movd %r8d, %xmm2472; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]473; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]474; SSE2-NEXT: movd %ecx, %xmm0475; SSE2-NEXT: movd %edx, %xmm1476; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]477; SSE2-NEXT: movd %esi, %xmm4478; SSE2-NEXT: movd %edi, %xmm0479; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]480; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]481; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]482; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0]483; SSE2-NEXT: retq484;485; SSE41-LABEL: test_buildvector_v16i8_register:486; SSE41: # %bb.0:487; SSE41-NEXT: movd %edi, %xmm0488; SSE41-NEXT: pinsrb $1, %esi, %xmm0489; SSE41-NEXT: pinsrb $2, %edx, %xmm0490; SSE41-NEXT: pinsrb $3, %ecx, %xmm0491; SSE41-NEXT: pinsrb $4, %r8d, %xmm0492; SSE41-NEXT: pinsrb $5, %r9d, %xmm0493; SSE41-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0494; SSE41-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0495; SSE41-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0496; SSE41-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0497; SSE41-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0498; SSE41-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0499; SSE41-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0500; SSE41-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0501; SSE41-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0502; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0503; SSE41-NEXT: retq504;505; AVX-LABEL: test_buildvector_v16i8_register:506; AVX: # %bb.0:507; AVX-NEXT: vmovd %edi, %xmm0508; AVX-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0509; AVX-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0510; AVX-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0511; AVX-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0512; AVX-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0513; AVX-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0514; AVX-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0515; AVX-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0516; AVX-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0517; AVX-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0518; AVX-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0519; AVX-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0520; AVX-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0521; AVX-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0522; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0523; AVX-NEXT: retq524 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0525 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1526 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2527 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3528 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4529 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5530 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6531 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7532 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8533 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9534 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10535 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11536 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12537 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13538 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14539 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15540 ret <16 x i8> %ins15541}542 543define <16 x i8> @test_buildvector_v16i8_partial(i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {544; SSE2-LABEL: test_buildvector_v16i8_partial:545; SSE2: # %bb.0:546; SSE2-NEXT: pxor %xmm0, %xmm0547; SSE2-NEXT: pinsrw $1, %edi, %xmm0548; SSE2-NEXT: pinsrw $3, %esi, %xmm0549; SSE2-NEXT: pinsrw $4, %edx, %xmm0550; SSE2-NEXT: shll $8, %ecx551; SSE2-NEXT: pinsrw $5, %ecx, %xmm0552; SSE2-NEXT: pinsrw $6, %r8d, %xmm0553; SSE2-NEXT: shll $8, %r9d554; SSE2-NEXT: pinsrw $7, %r9d, %xmm0555; SSE2-NEXT: retq556;557; SSE41-LABEL: test_buildvector_v16i8_partial:558; SSE41: # %bb.0:559; SSE41-NEXT: pxor %xmm0, %xmm0560; SSE41-NEXT: pinsrb $2, %edi, %xmm0561; SSE41-NEXT: pinsrb $6, %esi, %xmm0562; SSE41-NEXT: pinsrb $8, %edx, %xmm0563; SSE41-NEXT: pinsrb $11, %ecx, %xmm0564; SSE41-NEXT: pinsrb $12, %r8d, %xmm0565; SSE41-NEXT: pinsrb $15, %r9d, %xmm0566; SSE41-NEXT: retq567;568; AVX-LABEL: test_buildvector_v16i8_partial:569; AVX: # %bb.0:570; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0571; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0572; AVX-NEXT: vpinsrb $6, %esi, %xmm0, %xmm0573; AVX-NEXT: vpinsrb $8, %edx, %xmm0, %xmm0574; AVX-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0575; AVX-NEXT: vpinsrb $12, %r8d, %xmm0, %xmm0576; AVX-NEXT: vpinsrb $15, %r9d, %xmm0, %xmm0577; AVX-NEXT: retq578 %ins0 = insertelement <16 x i8> undef, i8 undef, i32 0579 %ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1580 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2581 %ins3 = insertelement <16 x i8> %ins2, i8 undef, i32 3582 %ins4 = insertelement <16 x i8> %ins3, i8 undef, i32 4583 %ins5 = insertelement <16 x i8> %ins4, i8 undef, i32 5584 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6585 %ins7 = insertelement <16 x i8> %ins6, i8 undef, i32 7586 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8587 %ins9 = insertelement <16 x i8> %ins8, i8 undef, i32 9588 %ins10 = insertelement <16 x i8> %ins9, i8 undef, i32 10589 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11590 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12591 %ins13 = insertelement <16 x i8> %ins12, i8 undef, i32 13592 %ins14 = insertelement <16 x i8> %ins13, i8 undef, i32 14593 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15594 ret <16 x i8> %ins15595}596 597define <16 x i8> @test_buildvector_v16i8_register_zero(i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {598; SSE2-LABEL: test_buildvector_v16i8_register_zero:599; SSE2: # %bb.0:600; SSE2-NEXT: movzbl %sil, %eax601; SSE2-NEXT: movzbl %dil, %esi602; SSE2-NEXT: movd %esi, %xmm0603; SSE2-NEXT: pinsrw $2, %eax, %xmm0604; SSE2-NEXT: movzbl %dl, %eax605; SSE2-NEXT: pinsrw $3, %eax, %xmm0606; SSE2-NEXT: movzbl %cl, %eax607; SSE2-NEXT: pinsrw $4, %eax, %xmm0608; SSE2-NEXT: shll $8, %r8d609; SSE2-NEXT: pinsrw $5, %r8d, %xmm0610; SSE2-NEXT: movzbl %r9b, %eax611; SSE2-NEXT: pinsrw $6, %eax, %xmm0612; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax613; SSE2-NEXT: shll $8, %eax614; SSE2-NEXT: pinsrw $7, %eax, %xmm0615; SSE2-NEXT: retq616;617; SSE41-LABEL: test_buildvector_v16i8_register_zero:618; SSE41: # %bb.0:619; SSE41-NEXT: movzbl %dil, %eax620; SSE41-NEXT: movd %eax, %xmm0621; SSE41-NEXT: pinsrb $4, %esi, %xmm0622; SSE41-NEXT: pinsrb $6, %edx, %xmm0623; SSE41-NEXT: pinsrb $8, %ecx, %xmm0624; SSE41-NEXT: pinsrb $11, %r8d, %xmm0625; SSE41-NEXT: pinsrb $12, %r9d, %xmm0626; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0627; SSE41-NEXT: retq628;629; AVX-LABEL: test_buildvector_v16i8_register_zero:630; AVX: # %bb.0:631; AVX-NEXT: movzbl %dil, %eax632; AVX-NEXT: vmovd %eax, %xmm0633; AVX-NEXT: vpinsrb $4, %esi, %xmm0, %xmm0634; AVX-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0635; AVX-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0636; AVX-NEXT: vpinsrb $11, %r8d, %xmm0, %xmm0637; AVX-NEXT: vpinsrb $12, %r9d, %xmm0, %xmm0638; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0639; AVX-NEXT: retq640 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0641 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1642 %ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2643 %ins3 = insertelement <16 x i8> %ins2, i8 0, i32 3644 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4645 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5646 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6647 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7648 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8649 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9650 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10651 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11652 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12653 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13654 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14655 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15656 ret <16 x i8> %ins15657}658 659define <16 x i8> @test_buildvector_v16i8_register_zero_2(i8 %a2, i8 %a3, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) {660; SSE2-LABEL: test_buildvector_v16i8_register_zero_2:661; SSE2: # %bb.0:662; SSE2-NEXT: shll $8, %esi663; SSE2-NEXT: movzbl %dil, %eax664; SSE2-NEXT: orl %esi, %eax665; SSE2-NEXT: pxor %xmm0, %xmm0666; SSE2-NEXT: pinsrw $1, %eax, %xmm0667; SSE2-NEXT: movzbl %dl, %eax668; SSE2-NEXT: pinsrw $3, %eax, %xmm0669; SSE2-NEXT: movzbl %cl, %eax670; SSE2-NEXT: pinsrw $4, %eax, %xmm0671; SSE2-NEXT: shll $8, %r8d672; SSE2-NEXT: pinsrw $5, %r8d, %xmm0673; SSE2-NEXT: movzbl %r9b, %eax674; SSE2-NEXT: pinsrw $6, %eax, %xmm0675; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax676; SSE2-NEXT: shll $8, %eax677; SSE2-NEXT: pinsrw $7, %eax, %xmm0678; SSE2-NEXT: retq679;680; SSE41-LABEL: test_buildvector_v16i8_register_zero_2:681; SSE41: # %bb.0:682; SSE41-NEXT: pxor %xmm0, %xmm0683; SSE41-NEXT: pinsrb $2, %edi, %xmm0684; SSE41-NEXT: pinsrb $3, %esi, %xmm0685; SSE41-NEXT: pinsrb $6, %edx, %xmm0686; SSE41-NEXT: pinsrb $8, %ecx, %xmm0687; SSE41-NEXT: pinsrb $11, %r8d, %xmm0688; SSE41-NEXT: pinsrb $12, %r9d, %xmm0689; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0690; SSE41-NEXT: retq691;692; AVX-LABEL: test_buildvector_v16i8_register_zero_2:693; AVX: # %bb.0:694; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0695; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0696; AVX-NEXT: vpinsrb $3, %esi, %xmm0, %xmm0697; AVX-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0698; AVX-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0699; AVX-NEXT: vpinsrb $11, %r8d, %xmm0, %xmm0700; AVX-NEXT: vpinsrb $12, %r9d, %xmm0, %xmm0701; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0702; AVX-NEXT: retq703 %ins0 = insertelement <16 x i8> undef, i8 0, i32 0704 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1705 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2706 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3707 %ins4 = insertelement <16 x i8> %ins3, i8 0, i32 4708 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5709 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6710 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7711 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8712 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9713 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10714 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11715 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12716 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13717 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14718 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15719 ret <16 x i8> %ins15720}721 722; PR46461 - Don't let reduceBuildVecExtToExtBuildVec break splat(zero_extend) patterns,723; resulting in the BUILD_VECTOR lowering to individual insertions into a zero vector.724 725define void @PR46461(i16 %x, ptr %y) {726; SSE-LABEL: PR46461:727; SSE: # %bb.0:728; SSE-NEXT: movzwl %di, %eax729; SSE-NEXT: movd %eax, %xmm0730; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]731; SSE-NEXT: psrld $1, %xmm0732; SSE-NEXT: movdqa %xmm0, 48(%rsi)733; SSE-NEXT: movdqa %xmm0, 32(%rsi)734; SSE-NEXT: movdqa %xmm0, 16(%rsi)735; SSE-NEXT: movdqa %xmm0, (%rsi)736; SSE-NEXT: retq737;738; AVX1-LABEL: PR46461:739; AVX1: # %bb.0:740; AVX1-NEXT: movzwl %di, %eax741; AVX1-NEXT: vmovd %eax, %xmm0742; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]743; AVX1-NEXT: vpsrld $1, %xmm0, %xmm0744; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0745; AVX1-NEXT: vmovaps %ymm0, 32(%rsi)746; AVX1-NEXT: vmovaps %ymm0, (%rsi)747; AVX1-NEXT: vzeroupper748; AVX1-NEXT: retq749;750; AVX2-LABEL: PR46461:751; AVX2: # %bb.0:752; AVX2-NEXT: movzwl %di, %eax753; AVX2-NEXT: shrl %eax754; AVX2-NEXT: vmovd %eax, %xmm0755; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0756; AVX2-NEXT: vmovdqa %ymm0, 32(%rsi)757; AVX2-NEXT: vmovdqa %ymm0, (%rsi)758; AVX2-NEXT: vzeroupper759; AVX2-NEXT: retq760 %z = lshr i16 %x, 1761 %a = zext i16 %z to i32762 %b = insertelement <16 x i32> undef, i32 %a, i32 0763 %c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer764 store <16 x i32> %c, ptr %y765 ret void766}767 768; OSS-Fuzz #5688769; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5688770define <4 x i32> @ossfuzz5688(i32 %a0) {771; CHECK-LABEL: ossfuzz5688:772; CHECK: # %bb.0:773; CHECK-NEXT: retq774 %1 = insertelement <4 x i32> zeroinitializer, i32 -2147483648, i32 %a0775 %2 = extractelement <4 x i32> %1, i32 %a0776 %3 = extractelement <4 x i32> <i32 30, i32 53, i32 42, i32 12>, i32 %2777 %4 = extractelement <4 x i32> zeroinitializer, i32 %2778 %5 = insertelement <4 x i32> undef, i32 %3, i32 undef779 store i32 %4, ptr undef780 ret <4 x i32> %5781}782 783; If we do not define all bytes that are extracted, this is a miscompile.784 785define i32 @PR46586(ptr %p, <4 x i32> %v) {786; SSE2-LABEL: PR46586:787; SSE2: # %bb.0:788; SSE2-NEXT: movzbl 3(%rdi), %eax789; SSE2-NEXT: pxor %xmm1, %xmm1790; SSE2-NEXT: pinsrw $6, %eax, %xmm1791; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]792; SSE2-NEXT: movd %xmm1, %eax793; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]794; SSE2-NEXT: movd %xmm0, %ecx795; SSE2-NEXT: xorl %edx, %edx796; SSE2-NEXT: divl %ecx797; SSE2-NEXT: movl %edx, %eax798; SSE2-NEXT: retq799;800; SSE41-LABEL: PR46586:801; SSE41: # %bb.0:802; SSE41-NEXT: movzbl 3(%rdi), %eax803; SSE41-NEXT: extractps $3, %xmm0, %ecx804; SSE41-NEXT: xorl %edx, %edx805; SSE41-NEXT: divl %ecx806; SSE41-NEXT: movl %edx, %eax807; SSE41-NEXT: retq808;809; AVX-LABEL: PR46586:810; AVX: # %bb.0:811; AVX-NEXT: movzbl 3(%rdi), %eax812; AVX-NEXT: vextractps $3, %xmm0, %ecx813; AVX-NEXT: xorl %edx, %edx814; AVX-NEXT: divl %ecx815; AVX-NEXT: movl %edx, %eax816; AVX-NEXT: retq817 %p3 = getelementptr inbounds i8, ptr %p, i64 3818 %t25 = load i8, ptr %p819 %t28 = load i8, ptr %p3820 %t29 = insertelement <4 x i8> undef, i8 %t25, i32 0821 %t32 = insertelement <4 x i8> %t29, i8 %t28, i32 3822 %t33 = zext <4 x i8> %t32 to <4 x i32>823 %t34 = urem <4 x i32> %t33, %v824 %t35 = extractelement <4 x i32> %t34, i32 3825 ret i32 %t35826}827 828define void @pr59781(ptr %in, ptr %out) {829; CHECK-LABEL: pr59781:830; CHECK: # %bb.0:831; CHECK-NEXT: movzwl (%rdi), %eax832; CHECK-NEXT: movzbl 2(%rdi), %ecx833; CHECK-NEXT: shll $16, %ecx834; CHECK-NEXT: orq %rax, %rcx835; CHECK-NEXT: movq %rcx, (%rsi)836; CHECK-NEXT: retq837 %bf.load = load i24, ptr %in, align 8838 %conv = zext i24 %bf.load to i64839 %splat.splatinsert = insertelement <1 x i64> zeroinitializer, i64 %conv, i64 0840 store <1 x i64> %splat.splatinsert, ptr %out, align 8841 ret void842}843