233 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; Check that 32-bit division is bypassed correctly.3; RUN: llc < %s -mattr=+idivl-to-divb -mtriple=i686-linux | FileCheck %s4 5define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {6; CHECK-LABEL: Test_get_quotient:7; CHECK: # %bb.0:8; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx9; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax10; CHECK-NEXT: movl %eax, %edx11; CHECK-NEXT: orl %ecx, %edx12; CHECK-NEXT: testl $-256, %edx13; CHECK-NEXT: je .LBB0_114; CHECK-NEXT: # %bb.2:15; CHECK-NEXT: cltd16; CHECK-NEXT: idivl %ecx17; CHECK-NEXT: retl18; CHECK-NEXT: .LBB0_1:19; CHECK-NEXT: movzbl %al, %eax20; CHECK-NEXT: divb %cl21; CHECK-NEXT: movzbl %al, %eax22; CHECK-NEXT: retl23 %result = sdiv i32 %a, %b24 ret i32 %result25}26 27define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {28; CHECK-LABEL: Test_get_remainder:29; CHECK: # %bb.0:30; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx31; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax32; CHECK-NEXT: movl %eax, %edx33; CHECK-NEXT: orl %ecx, %edx34; CHECK-NEXT: testl $-256, %edx35; CHECK-NEXT: je .LBB1_136; CHECK-NEXT: # %bb.2:37; CHECK-NEXT: cltd38; CHECK-NEXT: idivl %ecx39; CHECK-NEXT: movl %edx, %eax40; CHECK-NEXT: retl41; CHECK-NEXT: .LBB1_1:42; CHECK-NEXT: movzbl %al, %eax43; CHECK-NEXT: divb %cl44; CHECK-NEXT: movzbl %ah, %eax45; CHECK-NEXT: retl46 %result = srem i32 %a, %b47 ret i32 %result48}49 50define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {51; CHECK-LABEL: Test_get_quotient_and_remainder:52; CHECK: # %bb.0:53; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx54; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax55; CHECK-NEXT: movl %eax, %edx56; CHECK-NEXT: orl %ecx, %edx57; CHECK-NEXT: testl $-256, %edx58; CHECK-NEXT: je .LBB2_159; CHECK-NEXT: # %bb.2:60; CHECK-NEXT: cltd61; CHECK-NEXT: idivl %ecx62; CHECK-NEXT: addl %edx, %eax63; CHECK-NEXT: retl64; CHECK-NEXT: .LBB2_1:65; CHECK-NEXT: movzbl %al, %eax66; CHECK-NEXT: divb %cl67; CHECK-NEXT: movzbl %ah, %edx68; CHECK-NEXT: movzbl %al, %eax69; CHECK-NEXT: addl %edx, %eax70; CHECK-NEXT: retl71 %resultdiv = sdiv i32 %a, %b72 %resultrem = srem i32 %a, %b73 %result = add i32 %resultdiv, %resultrem74 ret i32 %result75}76 77define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {78; CHECK-LABEL: Test_use_div_and_idiv:79; CHECK: # %bb.0:80; CHECK-NEXT: pushl %ebx81; CHECK-NEXT: pushl %edi82; CHECK-NEXT: pushl %esi83; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx84; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx85; CHECK-NEXT: movl %ecx, %edi86; CHECK-NEXT: orl %ebx, %edi87; CHECK-NEXT: testl $-256, %edi88; CHECK-NEXT: je .LBB3_189; CHECK-NEXT: # %bb.2:90; CHECK-NEXT: movl %ecx, %eax91; CHECK-NEXT: cltd92; CHECK-NEXT: idivl %ebx93; CHECK-NEXT: movl %eax, %esi94; CHECK-NEXT: testl $-256, %edi95; CHECK-NEXT: je .LBB3_496; CHECK-NEXT: .LBB3_5:97; CHECK-NEXT: movl %ecx, %eax98; CHECK-NEXT: xorl %edx, %edx99; CHECK-NEXT: divl %ebx100; CHECK-NEXT: jmp .LBB3_6101; CHECK-NEXT: .LBB3_1:102; CHECK-NEXT: movzbl %cl, %eax103; CHECK-NEXT: divb %bl104; CHECK-NEXT: movzbl %al, %esi105; CHECK-NEXT: testl $-256, %edi106; CHECK-NEXT: jne .LBB3_5107; CHECK-NEXT: .LBB3_4:108; CHECK-NEXT: movzbl %cl, %eax109; CHECK-NEXT: divb %bl110; CHECK-NEXT: movzbl %al, %eax111; CHECK-NEXT: .LBB3_6:112; CHECK-NEXT: addl %eax, %esi113; CHECK-NEXT: movl %esi, %eax114; CHECK-NEXT: popl %esi115; CHECK-NEXT: popl %edi116; CHECK-NEXT: popl %ebx117; CHECK-NEXT: retl118 %resultidiv = sdiv i32 %a, %b119 %resultdiv = udiv i32 %a, %b120 %result = add i32 %resultidiv, %resultdiv121 ret i32 %result122}123 124define i32 @Test_use_div_imm_imm() nounwind {125; CHECK-LABEL: Test_use_div_imm_imm:126; CHECK: # %bb.0:127; CHECK-NEXT: movl $64, %eax128; CHECK-NEXT: retl129 %resultdiv = sdiv i32 256, 4130 ret i32 %resultdiv131}132 133define i32 @Test_use_div_reg_imm(i32 %a) nounwind {134; CHECK-LABEL: Test_use_div_reg_imm:135; CHECK: # %bb.0:136; CHECK-NEXT: movl $1041204193, %eax # imm = 0x3E0F83E1137; CHECK-NEXT: imull {{[0-9]+}}(%esp)138; CHECK-NEXT: movl %edx, %eax139; CHECK-NEXT: shrl $31, %eax140; CHECK-NEXT: sarl $3, %edx141; CHECK-NEXT: addl %edx, %eax142; CHECK-NEXT: retl143 %resultdiv = sdiv i32 %a, 33144 ret i32 %resultdiv145}146 147define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {148; CHECK-LABEL: Test_use_rem_reg_imm:149; CHECK: # %bb.0:150; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx151; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1152; CHECK-NEXT: movl %ecx, %eax153; CHECK-NEXT: imull %edx154; CHECK-NEXT: movl %edx, %eax155; CHECK-NEXT: shrl $31, %eax156; CHECK-NEXT: sarl $3, %edx157; CHECK-NEXT: addl %eax, %edx158; CHECK-NEXT: movl %edx, %eax159; CHECK-NEXT: shll $5, %eax160; CHECK-NEXT: addl %edx, %eax161; CHECK-NEXT: subl %eax, %ecx162; CHECK-NEXT: movl %ecx, %eax163; CHECK-NEXT: retl164 %resultrem = srem i32 %a, 33165 ret i32 %resultrem166}167 168define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {169; CHECK-LABEL: Test_use_divrem_reg_imm:170; CHECK: # %bb.0:171; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx172; CHECK-NEXT: movl $1041204193, %edx # imm = 0x3E0F83E1173; CHECK-NEXT: movl %ecx, %eax174; CHECK-NEXT: imull %edx175; CHECK-NEXT: movl %edx, %eax176; CHECK-NEXT: shrl $31, %eax177; CHECK-NEXT: sarl $3, %edx178; CHECK-NEXT: addl %edx, %eax179; CHECK-NEXT: movl %eax, %edx180; CHECK-NEXT: shll $5, %edx181; CHECK-NEXT: addl %eax, %edx182; CHECK-NEXT: subl %edx, %ecx183; CHECK-NEXT: addl %eax, %ecx184; CHECK-NEXT: movl %ecx, %eax185; CHECK-NEXT: retl186 %resultdiv = sdiv i32 %a, 33187 %resultrem = srem i32 %a, 33188 %result = add i32 %resultdiv, %resultrem189 ret i32 %result190}191 192define i32 @Test_use_div_imm_reg(i32 %a) nounwind {193; CHECK-LABEL: Test_use_div_imm_reg:194; CHECK: # %bb.0:195; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx196; CHECK-NEXT: testl $-256, %ecx197; CHECK-NEXT: je .LBB8_1198; CHECK-NEXT: # %bb.2:199; CHECK-NEXT: movl $4, %eax200; CHECK-NEXT: xorl %edx, %edx201; CHECK-NEXT: idivl %ecx202; CHECK-NEXT: retl203; CHECK-NEXT: .LBB8_1:204; CHECK-NEXT: movb $4, %al205; CHECK-NEXT: movzbl %al, %eax206; CHECK-NEXT: divb %cl207; CHECK-NEXT: movzbl %al, %eax208; CHECK-NEXT: retl209 %resultdiv = sdiv i32 4, %a210 ret i32 %resultdiv211}212 213define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {214; CHECK-LABEL: Test_use_rem_imm_reg:215; CHECK: # %bb.0:216; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx217; CHECK-NEXT: testl $-256, %ecx218; CHECK-NEXT: je .LBB9_1219; CHECK-NEXT: # %bb.2:220; CHECK-NEXT: movl $4, %eax221; CHECK-NEXT: xorl %edx, %edx222; CHECK-NEXT: idivl %ecx223; CHECK-NEXT: retl224; CHECK-NEXT: .LBB9_1:225; CHECK-NEXT: movb $4, %al226; CHECK-NEXT: movzbl %al, %eax227; CHECK-NEXT: divb %cl228; CHECK-NEXT: movzbl %al, %eax229; CHECK-NEXT: retl230 %resultdiv = sdiv i32 4, %a231 ret i32 %resultdiv232}233