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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=x86_64 -run-pass=register-coalescer -o - %s | FileCheck %s3 4# When the coalescer removes the COPY by commuting the operands of the AND, it should also update the `implicit-def` of the destination register.5---6name: implicit_def_dst7tracksRegLiveness: true8body: |9 bb.0:10 ; CHECK-LABEL: name: implicit_def_dst11 ; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)12 ; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)13 ; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]]14 ; CHECK-NEXT: RET 0, implicit [[MOV64rm]]15 %0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)16 %1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)17 %1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit18 %0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit19 RET 0, implicit %020...21# In case the MIR for some reason contains more than one implicit-def of the destination reg, then all should be updated.22---23name: two_implicit_defs_dst24tracksRegLiveness: true25body: |26 bb.0:27 ; CHECK-LABEL: name: two_implicit_defs_dst28 ; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)29 ; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)30 ; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]], implicit-def [[MOV64rm]]31 ; CHECK-NEXT: RET 0, implicit [[MOV64rm]]32 %0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)33 %1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)34 %1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit, implicit-def %1:gr64_with_sub_8bit35 %0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit36 RET 0, implicit %037...38# Commuting instruction with 3 ops is handled correctly.39---40name: commuting_3_ops41tracksRegLiveness: true42body: |43 bb.0:44 liveins: $ymm0, $ymm145 46 ; CHECK-LABEL: name: commuting_3_ops47 ; CHECK: liveins: $ymm0, $ymm148 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm150 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm051 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = contract nofpexcept VFMADD213PSYr [[COPY1]], [[COPY]], [[COPY]], implicit $mxcsr52 ; CHECK-NEXT: RET 0, implicit [[COPY1]]53 %0:vr256 = COPY $ymm154 %1:vr256 = COPY $ymm055 %0:vr256 = contract nofpexcept VFMADD231PSYr %0:vr256, %0:vr256, %1:vr256, implicit $mxcsr56 %1:vr256 = COPY %0:vr25657 RET 0, implicit %158...59