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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3; PR45724 5; Don't coalesce with %esp if it would end up putting %esp in6; the index position of an address, because that can't be7; encoded on x86. It would actually be slightly better to8; swap the address operands though, since there's no scale.9 10target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"11target triple = "i386-pc-mingw32"12 %"struct.std::valarray<unsigned int>" = type { i32, ptr }13 14define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, ptr nocapture %__l, ptr nocapture %__s, ptr nocapture %__i) nounwind {15; CHECK-LABEL: _ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: pushl %ebp18; CHECK-NEXT: movl %esp, %ebp19; CHECK-NEXT: movl %esp, %eax20; CHECK-NEXT: xorl %ecx, %ecx21; CHECK-NEXT: testb %cl, %cl22; CHECK-NEXT: je .LBB0_123; CHECK-NEXT: # %bb.5: # %return24; CHECK-NEXT: movl %ebp, %esp25; CHECK-NEXT: popl %ebp26; CHECK-NEXT: retl27; CHECK-NEXT: .LBB0_1: # %bb4.preheader28; CHECK-NEXT: xorl %edx, %edx29; CHECK-NEXT: jmp .LBB0_230; CHECK-NEXT: .p2align 431; CHECK-NEXT: .LBB0_4: # %bb7.backedge32; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=133; CHECK-NEXT: addl $-4, %edx34; CHECK-NEXT: .LBB0_2: # %bb435; CHECK-NEXT: # =>This Inner Loop Header: Depth=136; CHECK-NEXT: testb %cl, %cl37; CHECK-NEXT: jne .LBB0_438; CHECK-NEXT: # %bb.3: # %bb539; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=140; CHECK-NEXT: movl $0, (%eax,%edx)41; CHECK-NEXT: jmp .LBB0_442entry:43 %0 = alloca i32, i32 undef, align 4 ; <ptr> [#uses=1]44 br i1 undef, label %return, label %bb445 46bb4: ; preds = %bb7.backedge, %entry47 %indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ] ; <i32> [#uses=2]48 %scevgep24.sum = sub i32 undef, %indvar ; <i32> [#uses=2]49 %scevgep25 = getelementptr i32, ptr %0, i32 %scevgep24.sum ; <ptr> [#uses=1]50 %scevgep27 = getelementptr i32, ptr undef, i32 %scevgep24.sum ; <ptr> [#uses=1]51 %1 = load i32, ptr %scevgep27, align 4 ; <i32> [#uses=0]52 br i1 undef, label %bb7.backedge, label %bb553 54bb5: ; preds = %bb455 store i32 0, ptr %scevgep25, align 456 br label %bb7.backedge57 58bb7.backedge: ; preds = %bb5, %bb459 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]60 br label %bb461 62return: ; preds = %entry63 ret void64}65