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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s3 4; Not from issue 76416, but separate testcase reported on the same5; regressing commit.6define void @other_regression(i1 %cmp.not.i.i.i) {7; CHECK-LABEL: other_regression:8; CHECK: # %bb.0: # %entry9; CHECK-NEXT: pushq %rax10; CHECK-NEXT: .cfi_def_cfa_offset 1611; CHECK-NEXT: movl 0, %eax12; CHECK-NEXT: xorl %ecx, %ecx13; CHECK-NEXT: sarl %cl, %eax14; CHECK-NEXT: movl $1, %edx15; CHECK-NEXT: xorl %ecx, %ecx16; CHECK-NEXT: shrl %cl, %edx17; CHECK-NEXT: imull %eax, %edx18; CHECK-NEXT: movslq %edx, %rsi19; CHECK-NEXT: xorl %eax, %eax20; CHECK-NEXT: xorl %edi, %edi21; CHECK-NEXT: xorl %edx, %edx22; CHECK-NEXT: callq *%rax23entry:24 br label %for.cond10.preheader25 26trap: ; preds = %for.body1327 unreachable28 29for.cond10.preheader: ; preds = %while.cond.i.i.i, %entry30 %indvars.iv = phi i64 [ 0, %entry ], [ 1, %while.cond.i.i.i ]31 %i = trunc i64 %indvars.iv to i3232 br label %for.body1333 34for.body13: ; preds = %for.cond10.preheader35 %i1 = load i32, ptr null, align 436 %shr = ashr i32 %i1, %i37 %shr15 = ashr i32 1, %i38 %mul16 = mul i32 %shr15, %shr39 %conv = sext i32 %mul16 to i6440 call void null(ptr null, i64 %conv, ptr null)41 br i1 false, label %while.cond.i.i.i, label %trap42 43while.cond.i.i.i: ; preds = %while.cond.i.i.i, %for.body1344 br i1 %cmp.not.i.i.i, label %for.cond10.preheader, label %while.cond.i.i.i45}46