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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s3 4# The %1 = MOV32r0 is rematerialized as a subregister of %2. The5# implicit-def %1 operand needs to have an undef added, just like the6# main result operand.7 8---9name: remat_into_subregister_set_undef_implicit_operand_subregisters10tracksRegLiveness: true11body: |12 ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters13 ; CHECK: bb.0:14 ; CHECK-NEXT: successors: %bb.1(0x80000000)15 ; CHECK-NEXT: liveins: $rdi16 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]18 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_1]]19 ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]]20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: bb.1:22 ; CHECK-NEXT: successors: %bb.2(0x80000000)23 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags25 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.2:27 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)28 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags30 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: bb.3:32 ; CHECK-NEXT: successors: %bb.4(0x80000000)33 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: bb.4:35 ; CHECK-NEXT: successors: %bb.1(0x80000000)36 ; CHECK-NEXT: {{ $}}37 ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]]38 ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags39 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit40 ; CHECK-NEXT: JMP_1 %bb.141 bb.0:42 liveins: $rdi43 44 undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %045 %1:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def %146 undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %247 48 bb.1:49 %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags50 51 bb.2:52 JCC_1 %bb.4, 5, implicit killed undef $eflags53 54 bb.3:55 56 bb.4:57 dead %3:gr32 = MOV32rr %158 dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags59 %1:gr32 = COPY %2.sub_32bit60 JMP_1 %bb.161 62...63 64# Same, except the implicit-def on the original instruction already65# has a subregister index.66 67---68name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg69tracksRegLiveness: true70body: |71 ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg72 ; CHECK: bb.0:73 ; CHECK-NEXT: successors: %bb.1(0x80000000)74 ; CHECK-NEXT: liveins: $rdi75 ; CHECK-NEXT: {{ $}}76 ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]77 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_1]].sub_8bit78 ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]]79 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: bb.1:81 ; CHECK-NEXT: successors: %bb.2(0x80000000)82 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags84 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: bb.2:86 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)87 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags89 ; CHECK-NEXT: {{ $}}90 ; CHECK-NEXT: bb.3:91 ; CHECK-NEXT: successors: %bb.4(0x80000000)92 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: bb.4:94 ; CHECK-NEXT: successors: %bb.1(0x80000000)95 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]]97 ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags98 ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit99 ; CHECK-NEXT: JMP_1 %bb.1100 bb.0:101 liveins: $rdi102 103 undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0104 %1:gr32 = MOV32r0 implicit-def dead $eflags, undef implicit-def %1.sub_8bit105 undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2106 107 bb.1:108 %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags109 110 bb.2:111 JCC_1 %bb.4, 5, implicit killed undef $eflags112 113 bb.3:114 115 bb.4:116 dead %3:gr32 = MOV32rr %1117 dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags118 %1:gr32 = COPY %2.sub_32bit119 JMP_1 %bb.1120 121...122