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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE413 4define double @test1_add(double %A, double %B) {5; SSE41-LABEL: test1_add:6; SSE41: # %bb.0:7; SSE41-NEXT: paddd %xmm1, %xmm08; SSE41-NEXT: retq9 %1 = bitcast double %A to <2 x i32>10 %2 = bitcast double %B to <2 x i32>11 %add = add <2 x i32> %1, %212 %3 = bitcast <2 x i32> %add to double13 ret double %314}15 16define double @test2_add(double %A, double %B) {17; SSE41-LABEL: test2_add:18; SSE41: # %bb.0:19; SSE41-NEXT: paddw %xmm1, %xmm020; SSE41-NEXT: retq21 %1 = bitcast double %A to <4 x i16>22 %2 = bitcast double %B to <4 x i16>23 %add = add <4 x i16> %1, %224 %3 = bitcast <4 x i16> %add to double25 ret double %326}27 28define double @test3_add(double %A, double %B) {29; SSE41-LABEL: test3_add:30; SSE41: # %bb.0:31; SSE41-NEXT: paddb %xmm1, %xmm032; SSE41-NEXT: retq33 %1 = bitcast double %A to <8 x i8>34 %2 = bitcast double %B to <8 x i8>35 %add = add <8 x i8> %1, %236 %3 = bitcast <8 x i8> %add to double37 ret double %338}39 40define double @test1_sub(double %A, double %B) {41; SSE41-LABEL: test1_sub:42; SSE41: # %bb.0:43; SSE41-NEXT: psubd %xmm1, %xmm044; SSE41-NEXT: retq45 %1 = bitcast double %A to <2 x i32>46 %2 = bitcast double %B to <2 x i32>47 %sub = sub <2 x i32> %1, %248 %3 = bitcast <2 x i32> %sub to double49 ret double %350}51 52define double @test2_sub(double %A, double %B) {53; SSE41-LABEL: test2_sub:54; SSE41: # %bb.0:55; SSE41-NEXT: psubw %xmm1, %xmm056; SSE41-NEXT: retq57 %1 = bitcast double %A to <4 x i16>58 %2 = bitcast double %B to <4 x i16>59 %sub = sub <4 x i16> %1, %260 %3 = bitcast <4 x i16> %sub to double61 ret double %362}63 64define double @test3_sub(double %A, double %B) {65; SSE41-LABEL: test3_sub:66; SSE41: # %bb.0:67; SSE41-NEXT: psubb %xmm1, %xmm068; SSE41-NEXT: retq69 %1 = bitcast double %A to <8 x i8>70 %2 = bitcast double %B to <8 x i8>71 %sub = sub <8 x i8> %1, %272 %3 = bitcast <8 x i8> %sub to double73 ret double %374}75 76define double @test1_mul(double %A, double %B) {77; SSE41-LABEL: test1_mul:78; SSE41: # %bb.0:79; SSE41-NEXT: pmulld %xmm1, %xmm080; SSE41-NEXT: retq81 %1 = bitcast double %A to <2 x i32>82 %2 = bitcast double %B to <2 x i32>83 %mul = mul <2 x i32> %1, %284 %3 = bitcast <2 x i32> %mul to double85 ret double %386}87 88define double @test2_mul(double %A, double %B) {89; SSE41-LABEL: test2_mul:90; SSE41: # %bb.0:91; SSE41-NEXT: pmullw %xmm1, %xmm092; SSE41-NEXT: retq93 %1 = bitcast double %A to <4 x i16>94 %2 = bitcast double %B to <4 x i16>95 %mul = mul <4 x i16> %1, %296 %3 = bitcast <4 x i16> %mul to double97 ret double %398}99 100; There is no legal ISD::MUL with type MVT::v16i8.101define double @test3_mul(double %A, double %B) {102; SSE41-LABEL: test3_mul:103; SSE41: # %bb.0:104; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero105; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero106; SSE41-NEXT: pmullw %xmm1, %xmm0107; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]108; SSE41-NEXT: retq109 %1 = bitcast double %A to <8 x i8>110 %2 = bitcast double %B to <8 x i8>111 %mul = mul <8 x i8> %1, %2112 %3 = bitcast <8 x i8> %mul to double113 ret double %3114}115 116define double @test1_and(double %A, double %B) {117; SSE41-LABEL: test1_and:118; SSE41: # %bb.0:119; SSE41-NEXT: andps %xmm1, %xmm0120; SSE41-NEXT: retq121 %1 = bitcast double %A to <2 x i32>122 %2 = bitcast double %B to <2 x i32>123 %and = and <2 x i32> %1, %2124 %3 = bitcast <2 x i32> %and to double125 ret double %3126}127 128define double @test2_and(double %A, double %B) {129; SSE41-LABEL: test2_and:130; SSE41: # %bb.0:131; SSE41-NEXT: andps %xmm1, %xmm0132; SSE41-NEXT: retq133 %1 = bitcast double %A to <4 x i16>134 %2 = bitcast double %B to <4 x i16>135 %and = and <4 x i16> %1, %2136 %3 = bitcast <4 x i16> %and to double137 ret double %3138}139 140define double @test3_and(double %A, double %B) {141; SSE41-LABEL: test3_and:142; SSE41: # %bb.0:143; SSE41-NEXT: andps %xmm1, %xmm0144; SSE41-NEXT: retq145 %1 = bitcast double %A to <8 x i8>146 %2 = bitcast double %B to <8 x i8>147 %and = and <8 x i8> %1, %2148 %3 = bitcast <8 x i8> %and to double149 ret double %3150}151 152define double @test1_or(double %A, double %B) {153; SSE41-LABEL: test1_or:154; SSE41: # %bb.0:155; SSE41-NEXT: orps %xmm1, %xmm0156; SSE41-NEXT: retq157 %1 = bitcast double %A to <2 x i32>158 %2 = bitcast double %B to <2 x i32>159 %or = or <2 x i32> %1, %2160 %3 = bitcast <2 x i32> %or to double161 ret double %3162}163 164define double @test2_or(double %A, double %B) {165; SSE41-LABEL: test2_or:166; SSE41: # %bb.0:167; SSE41-NEXT: orps %xmm1, %xmm0168; SSE41-NEXT: retq169 %1 = bitcast double %A to <4 x i16>170 %2 = bitcast double %B to <4 x i16>171 %or = or <4 x i16> %1, %2172 %3 = bitcast <4 x i16> %or to double173 ret double %3174}175 176define double @test3_or(double %A, double %B) {177; SSE41-LABEL: test3_or:178; SSE41: # %bb.0:179; SSE41-NEXT: orps %xmm1, %xmm0180; SSE41-NEXT: retq181 %1 = bitcast double %A to <8 x i8>182 %2 = bitcast double %B to <8 x i8>183 %or = or <8 x i8> %1, %2184 %3 = bitcast <8 x i8> %or to double185 ret double %3186}187 188define double @test1_xor(double %A, double %B) {189; SSE41-LABEL: test1_xor:190; SSE41: # %bb.0:191; SSE41-NEXT: xorps %xmm1, %xmm0192; SSE41-NEXT: retq193 %1 = bitcast double %A to <2 x i32>194 %2 = bitcast double %B to <2 x i32>195 %xor = xor <2 x i32> %1, %2196 %3 = bitcast <2 x i32> %xor to double197 ret double %3198}199 200define double @test2_xor(double %A, double %B) {201; SSE41-LABEL: test2_xor:202; SSE41: # %bb.0:203; SSE41-NEXT: xorps %xmm1, %xmm0204; SSE41-NEXT: retq205 %1 = bitcast double %A to <4 x i16>206 %2 = bitcast double %B to <4 x i16>207 %xor = xor <4 x i16> %1, %2208 %3 = bitcast <4 x i16> %xor to double209 ret double %3210}211 212define double @test3_xor(double %A, double %B) {213; SSE41-LABEL: test3_xor:214; SSE41: # %bb.0:215; SSE41-NEXT: xorps %xmm1, %xmm0216; SSE41-NEXT: retq217 %1 = bitcast double %A to <8 x i8>218 %2 = bitcast double %B to <8 x i8>219 %xor = xor <8 x i8> %1, %2220 %3 = bitcast <8 x i8> %xor to double221 ret double %3222}223 224define double @test_fadd(double %A, double %B) {225; SSE41-LABEL: test_fadd:226; SSE41: # %bb.0:227; SSE41-NEXT: addps %xmm1, %xmm0228; SSE41-NEXT: retq229 %1 = bitcast double %A to <2 x float>230 %2 = bitcast double %B to <2 x float>231 %add = fadd <2 x float> %1, %2232 %3 = bitcast <2 x float> %add to double233 ret double %3234}235 236define double @test_fsub(double %A, double %B) {237; SSE41-LABEL: test_fsub:238; SSE41: # %bb.0:239; SSE41-NEXT: subps %xmm1, %xmm0240; SSE41-NEXT: retq241 %1 = bitcast double %A to <2 x float>242 %2 = bitcast double %B to <2 x float>243 %sub = fsub <2 x float> %1, %2244 %3 = bitcast <2 x float> %sub to double245 ret double %3246}247 248define double @test_fmul(double %A, double %B) {249; SSE41-LABEL: test_fmul:250; SSE41: # %bb.0:251; SSE41-NEXT: mulps %xmm1, %xmm0252; SSE41-NEXT: retq253 %1 = bitcast double %A to <2 x float>254 %2 = bitcast double %B to <2 x float>255 %mul = fmul <2 x float> %1, %2256 %3 = bitcast <2 x float> %mul to double257 ret double %3258}259 260